SRAM

SOVERAN S. DHAKADSOVERAN S. DHAKAD

Asst Professor Asst Professor Asst. Professor Asst. Professor

Electronics & Communication Engg. Deptt.Electronics & Communication Engg. Deptt.

((MM--TechTech-- Embedded System & VLSI DesignEmbedded System & VLSI Design))

[email protected][email protected]

ContactContact-- 09685396020 ,075109685396020 ,0751--2387520(O)2387520(O)

NAGAJI INSTITUTE OF TECHNOLOGY & MANAGEMENT,THAKUR BABA CAMPUS ,JHANSI ROAD , NH-75 ,SITHOLI ,GWALIOR-474001E-Mail –[email protected] ,website:- nitmindia.org.@ g , gContact No. -0751-2410201 ,2387520 ,9685396020

A HIGH DENSITY, LOW LEAKAGE, 5T SRAM A HIGH DENSITY, LOW LEAKAGE, 5T SRAM A HIGH DENSITY, LOW LEAKAGE, 5T SRAM A HIGH DENSITY, LOW LEAKAGE, 5T SRAM FOR EMBEDDED CACHE MEMORYFOR EMBEDDED CACHE MEMORY

MemoryMemoryOperationSense Amplifier pCache MemoryLeakage In SRAM Cell Why 5T SRAM CellStructure Diagram Of 5T SRAM Operation in 5T SRAM Cell Operation in 5T SRAM Cell Implementation & Result Conclusion & Future Work Conclusion & Future Work Reference

A memory in terms of computer hardware is a storage unitA memory in terms of computer hardware is a storage unit.

Storage devices such as magnetic device, hard disk, CDs,DVDs etcDVDs etc

The memory of a computer stores the programs and datawhile being processed.g p

It is built up of small units called bits which can hold onebinary symbol of data (referred to as a ’1’ or a ’0’).

Also it helps to boot the system.

Memory directly accessible by CPUMemory directly accessible by CPU.

There are Various types of basic operations that have tobe supported by a RAM. These are the writing and reading

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pp y g gof ’0’ and ’1’ respectively .

MEMORY

ROMROMRAM

RAM (Random Access Memory)-Random Access Memory, a memory where information

can be stored and retrieved in non-sequential ordercan be stored and retrieved in non sequential order.

ROM (Read Only Memory)-ROM l k fi i i t t d i itROM, also known as firmware, is an integrated circuit

programmed with specific data when it is manufactured.ROM chips are used not only in computers, but in most other

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electronic items as well.

It is an array of elements

which can either store 1 or 0.

It is dynamic in nature.

It is volatile It is volatile .

It is made either of

i d i semiconductors or capacitors

as required.

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bitline conditioning

bitlines

wordlines

row memory cells:

bitlines

decoder

memory cells:2n-k rows x2m+k columns

r

n-kk column

circuitrycolumndecoder

n

2m bits

circuitry

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The memory cells in a SRAM are organized in rows and

columns.

Memory Cell = 2n-k Row Ҳ 2m+k Columns

I th it ti th W d li i i ti t t iIn the write operation , the Word line is in active state, in

that cause each data bit to be stored in a selected cell in the

associated column.

In the read operation the read line is in active state inIn the read operation, the read line is in active state, in

that cause the data bits stored in the selected row to appear

th D t I/O li

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on the Data I/O lines.

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The 6T SRAM cell has a differential read operation. This

means that both the stored value and its inverse are used inmeans that both the stored value and its inverse are used in

evaluation to determine the stored value. Before the onset of

d ti th W d li i h ld l d th ta read operation, the Word line is held low and the two

bitlines connected to the cell through transistors M5 and M6

are precharged high . Since the gates of M5 and M6 are held

low, these access transistors are off and the cross-coupled

latch is isolated from the bitlines.

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A_b bit_b

1.0

1.5

word bit

0 0

0.5

word

A

0.00 100 200 300 400 500 600

time (ps)

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Read Operation:-If the value is a 1, stored at Q.The read cycle is started by pre charging both the bitThe read cycle is started by pre charging both the bit

lines to a logical 1, then asserting the word line WL,enabling both the access transistors.

Th d t h th l t d i Q dThe second step occurs when the values stored in Q andQ are transferred to the bit lines by leaving BL at its precharged value and discharging BL through M1 and M5 to ag g g g 1 5

logical 0.On the BL side, the transistors M4 and M6 pull the bit line

toward VDD a logical 1toward VDD, a logical 1.If the content of the memory was a 0, the opposite would

happen and BL would be pulled toward 1 and BL toward 0.

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A b

A

A_b

bit b

1.5

word

bit_b

0.5

1.0

time (ps)

0.00 100 200 300 400 500 600 700

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Write Operation:-The start of a write cycle begins by applying the value to beitt t th bit liwritten to the bit lines.

If we wish to write a 0, we would apply a 0 to the bit lines, i.e.setting BL to 1 and BL to 0.This is similar to applying a reset pulse to a SR-latch , whichcauses the flip flop to change state.

A 1 is written by inverting the values of the bit lines. WL isA 1 is written by inverting the values of the bit lines. WL isthen asserted and the value that is to be stored is latched in.

Note that the reason this works is that the bit line input-d i d i d t b h t th th l ti ldrivers are designed to be much stronger than the relativelyweak transistors in the cell itself, so that they can easilyoverride the previous state of the cross-coupled inverters.

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It is practically embedded in every application that

requires electronic use interface such as digital camerasrequires electronic use interface such as digital cameras,

cell phones, etc.

I t l CPU h h d di k b ff t b ffInternal CPU caches , hard disk buffers, router buffers,

LCD screens and printers also normally employ static RAM

to hold the image displayed .

Small SRAM buffers are also found in CDROM and CDRW

drives; usually 256 kB.

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A S A lifi i i lA Sense Amplifier is an essentialcircuit in designing memory chips.

The resulting signal in the event of aThe resulting signal, in the event of aRead operation, has a much lowervoltage swing. To compensate for thatswing a sense amplifier is used toamplify voltage coming off Bit Line.

Th lt i t f thThe voltage coming out of the senseamplifier typically has a fully swing (0 -2.5V) voltage.) g

Sense amplifier also helps reduce thedelay times and power dissipation in

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the overall SRAM chip.

There are many versions of senseamplifiers used in memory chips :-

The one that we will use in ourdesign is called a Cross-coupledSense Amplifier demonstrated on apblock diagram below.

During a read sequence, Bit Lineand Bit Line are directed into X andX inputs. Once SE has been set tologic 1, the amplifier turns on, andlogic 1, the amplifier turns on, andgives Y and Y as its outputs.

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Cache memory is basically a cost-effective method ofimproving system performance.

Cache memory is a relatively small, high-speed memorythat stores the most recently used instructions or data.

Cache e o ca al o e d a ic RAM (DRAM)Cache memory can also use dynamic RAM (DRAM).

Cache memory stored information to the microprocessormuch faster than if only high-capacity DRAM is usedmuch faster than if only high-capacity DRAM is used.

Cache memory used to store data or instructions likely tobe used soon by the CPU. Its purpose is to speed upbe used soon by the CPU. Its purpose is to speed upoperation by bridging the performance gap between theCPU and the main memory.

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Two types of cache level are used in cache memory:-Two types of cache level are used in cache memory:

L1 :- It usually integrated into the processor chip and has avery limited storage capacity.y g p y

It gives an extremely short access time, and thereforeprovides the highest performance

This cache usually runs at the same clock frequency asthe CPU

L2 :-It is separate memory chip or set of chips external tothe processor and usually has a larger storage capacityth L1 hthan L1 cache.

This is connected to CPU through an internal bus

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Some higher-level caches (L3. L4, .), but L1 and L2 are themost common.

There are some very important requirements for a memorywhen it is to be embedded as on-chip cache:

It has to be reliable and stable. This is of course true forall memories, but is specially important for cache due tothe more extreme performance requirements and areathe more extreme performance requirements and arealimitations.

Memory provide high performance gap between mainMemory provide high performance gap between mainmemory and the CPU.

Another important requirement is low powerp q pconsumption.

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Low power design is important from three differentreasons-

Technology driven forcesTechnology driven forcesMinimum feature size,Minimize parasitic capacitanceHigher operating speed

Design driven forcesPower consumption in digital circuitsp gPower consumption in analog circuits

Market driven forcesThe growing demand for long life portableThe growing demand for long life portableequipment.

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There are various types of applications of low power-

Battery-powered portable systems, for example laptops,CDs, ,DVDs

Electronic packet communication products such as;cordless and cellular telephones, PDAs (Personal DigitalAssistants), pagers.

S b GH f hi h f k t tiSub-GHz processors for high-performance workstationsand computers.

Other applications such as WLANs (Wireless Local AreaOther applications such as WLANs (Wireless Local AreaNetwork) and electronic goals (calculators, hearing aids,watches, etc.).

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The supply voltage must be reduced.

The threshold voltage (VT) must be reduced proportionally ith th l lt th t ffi i t t d i i with the supply voltage so that a sufficient gate overdrive is

maintained.

Reduction in the threshold voltage causes increase in

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Reduction in the threshold voltage causes increase in leakage current.

During an idle phase the word lines are deselected (WL =During an idle phase, the word lines are deselected (WL =‘0’) and the bit lines are precharged (BL = ‘1’ and BL = ‘1’).

The memory cell data either transistors N4 P1 N2 (for bitThe memory cell data, either transistors N4, P1, N2 (for bit= ‘1’) or N3, P2, N1 (for bit = ‘0’) will be leaking .

The transistors in the off state in bold for bit = ‘0’. In thiscase N3,N1 and P2 are off and will be leaking. The leakagecurrent in the memory cell would be as shown in equation:

ImemcellIdle = IDsub(N1) + IDsub(N3) + IDsub(P2)

where, IDsub is the sub threshold leakage current ofthe MOSFET , which is given by the equation :-

IDsub = Is e VGS/(nKT)/q [1-VDS/eKT/q ]

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where, Is and n are imperial parameters with n ≥ 1.

The sub threshold leakage in the whole memory coreis given by equation .

ImemcoreIdle = Nrows. Cools . ImemcellIdle

where, Nrows and Ncols are the number of rows andcolumns respectively in the memory core.

Thus to reduce the leakage of a memory cell we havet t t t t f l kto concentrate on two components of leakage :-

1. one is the leakage inside the cell .

2. Second is leakage to bit lines.

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T h i d d h l k iTechniques are used to reduce the leakage current is:-

Dual VT :-

This technique requires no additional control circuitryand can substantially reduce the leakage current whencompared to low V devicescompared to low VT devices.

No data are discarded and no additional cachesmisses are incurred. However , high- transistors havemisses are incurred. However , high transistors haveslower switching speed and lower current drive.

ABC-MTCMOS :-

It can reduce the leakage current significantly using asimple circuit while in the sleep mode.

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I d d d i bl l k i hIn order to reduce undesirable leakage current in thesleep mode, the back gate bias is automaticallycontrolled to increase the threshold voltage.g

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DVS (Dynamic Voltage Scaling):-

In this method to reduce the leakage power of SRAM cells,in active mode.

When cells are not intended to be accessed for a timee iod the a e laced i a lee odeperiod, they are placed in a sleep mode.

In a sleep mode the leakage power is significantlyreduced due to the decreases in both leakage currentreduced due to the decreases in both leakage currentand supply voltage.

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We have to used Two PMOS transistor P1,P2, to control thesupply voltage of the memory cell based on theoperating.p g

1. Active Mode 2. Sleep Mode

If cell is active mode P1 supplies a standard supplyIf cell is active mode , P1 supplies a standard supplyvoltage, and P2 supplies a standby voltage.

If cell is Sleep mode, P1 and P2 are controlled by

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If cell is Sleep mode, P1 and P2 are controlled bycomplementary supply voltage control signals.

E b dd d Embedded memory-

Easy to implement in generic CMOS process.

Easy to design as logic circuit.

Easy to test by finite-state machine.

Compliable design-

Fixed cell size to allow us dedicating in peripheral circuit ed ce s e to a ow us ded cat g pe p e a c cu t

design

Synchronous interface since 0 35µm generation simplifies Synchronous interface since 0.35µm generation simplifies

the design

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A larger number of instances required

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In the 5T SRAM cell differs fundamentally from the cell

used in 2PMOS & 3 NMOS Transistors.

The latch of the cell is disconnected from the gnd supply to

f ilit t itfacilitate write.

This requires an additional metal wire and also destabilizesq

all cells on the bit line during write.

The design and all simulations are carried out at 100nm

technology.

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Read Operation-The operation scheme when reading a 5T

cell is very similar to the 6T SRAM.

Before the onset of a read operation, the word line is held

low and the bitline is precharged.

The bitline is not precharged to VCC, So another value is

carefully chosen according to stability and performancecarefully chosen according to stability and performance

requirements.

If di ’0’ BL ill b ll d d th h thIf reading a ’0’, BL will now be pulled down through the

transistor combination. If instead a ’1’ is to be read, the

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situation is slightly different from the 6T case.

Write Operation-Writing in the 5T SRAM cell differs from

the 6T cell mainly by the fact that it is done from only one

bitline.

In the 5T cell the value to be written is held on the bitline,In the 5T cell the value to be written is held on the bitline,

and the word line is asserted.

The 6T cell was sized so that a ’1’ could not be written byThe 6T cell was sized so that a 1 could not be written by

a high voltage on the bitline, the 5T cell has to be sized

differently.

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The difference between the 5T SRAM and the 6T SRAM isThe difference between the 5T SRAM and the 6T SRAM ishow the sensing of the stored value is done.

The 6T cell has two bit lines and the stored value is senseddifferentially.

The 5T cell only has one bitline. Depending on the valuestored, the 5T bitline is either raised or lowered.

A few different techniques can be used for this. One ideamight be to use a type of sample and hold circuit that wouldSample the value before the read and then use this value as areference in a differential sense amplifier.

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Table 5.1: Leakage power and performance of 6T cell

Metrics Standard 6T cell

Read time (WL high up to 100mV difference in bit lines) 336ps

Write time (WL high up to node flips) 76ps

Leakage Power/cell 2.03nW

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Table 5.2: Comparison of leakage power reduction techniques

Leakage ReductionTechnique

Leakage PowerDissipation/Cell (in Percentage

ReductionTechnique Dissipation/Cell (in n W)

Reduction

Conventional 2.030 -

DVS 0.230 88.7

G t d VDD 0 033 98 3Gated-VDD 0.033 98.3

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Table 5 3: Leakage power and performance of 5T cellTable 5.3: Leakage power and performance of 5T cell

Metrics Standard 6T cell

Read time (WL high up to 100mV difference in bit lines) 365psRead time (WL high up to 100mV difference in bit lines) 365ps

Write time (WL high up to node flips) 102ps

Leakage Power/cell 1.79nW

Table 5.4: Comparison of leakage power dissipation in 6T Table 5.4: Comparison of leakage power dissipation in 6T and 5T cell

Leakage ReductionTechnique

Leakage PowerDissipation/Cell (in nW)

Percentage Reduction

6T 5TConventional 2.030 1.790 11.8

DVS 0.230 0.170 26.0

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. . 7Gated-VDD 0.033 0.029 12.1

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Various circuit level techniques have been applied to 6TVarious circuit level techniques have been applied to 6Tand designed 5T SRAM cell for leakage power reductionand compared. Out of all the techniques discussed DVS hasf d t b th b t it d l k bl tfound to be the best as it reduces leakage comparable toGated VDD as well as retain the cell information.

It has been found that in conventional 6T SRAM cell upto 98% reduction in leakage power can be achieved usingthese techniques. With conventional 5T cell about 11.8%these techniques. With conventional 5T cell about 11.8%leakage power reduction has been achieved thanconventional 6T cell. Further applying the leakage

d ti t h i t th 5T ll h h 26%reduction techniques to the 5T cell has shown 26% morereduction in leakage than in the case of 6T cell.

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In this thesis various circuit level leakage powerg preduction techniques have been analyzed with 6T and 5TSRAM cell at 180nm technology. A large reduction inleakage has been observed As memory cells beingleakage has been observed. As memory cells beingdiscussed have to be used in cache memory their stability isalso very important. So stability analysis of both 6T and 5T

f i i icells after applying leakage reduction techniques can beanalyzed.

Device level techniques such as retrograde well; Haloq g ;doping and LDD (Light Doped Drain) implantation can beemployed for leakage reduction in individual MOSFETswhich eventually will reduce in large reduction As leakagewhich eventually will reduce in large reduction. As leakagewill be more significant beyond 100nm technology so thiswork should be extended to higher technologies such as90 70 b d

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90nm, 70nm or beyond.

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[27] Soveran Singh Dhakad, Shyam Akashe, Sanjay Sharma “Cache Leakage : A Leakage aware cache simulator” International Journals of Computing and Applications, vol 5 no.2 (july-Dec-2010).

[28] Soveran Singh Dhakad, Shyam Akashe, Sanjay Sharma “Dynamic Zero compression for Cache Energy Reduction ” International Journals of power engineering ,vol 2 no.2 (july-Dec-2010).

[29] Soveran Singh Dhakad Shyam Akashe “CMOS VLSI Design” National Conference in NEE Gwalior[29] Soveran Singh Dhakad, Shyam Akashe, CMOS VLSI Design National Conference in NEE, Gwalior, Ist Oct. 2009.

[30] Soveran Singh Dhakad, Shyam Akashe, “Cache Memory cell for Leakage Power” National Conference in NEE, Gwalior, 26th June. 2010.

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THANK YOUTHANK YOU AND

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