-
Signal Processing Technologies, Inc.4755 Forge Road, Colorado
Springs, Colorado 80907, USA
Phone: 719-528-2300 Fax: 719-528-2370 Web Site:
http://www.spt.com e-mail: [email protected]
AN7610EVALUATION BOARD
APPLICATION NOTE
FEATURES
1 GSPS conversion rate On-board reconstruction DAC On-board
reference circuit On-board adjustable reference Decimated digital
data output Selectable decimation divide by 16/32/64 options
APPLICATIONS
Evaluation of SPT7610 6-bit ADCs Engineering system prototype
aid Guide for design of SPT7610 interface circuitry Guide for
design of SPT7610 PCB layout
SPECIAL REQUIREMENTS
The SPT7610 device requires adequate heat sinkingand air flow
for optimum performance.
GENERAL DESCRIPTION
The EB7610 evaluation board is specifically designed fordevice
characterization and demonstration of the perfor-mance of the
SPT7610 A/D converter. The SPT7610 hasa guaranteed sample rate of 1
GSPS. At this high conver-sion speed, hand-crafted bread boards
will not performeffectively, and a printed circuit board is a must.
This appli-cation note should be used as a supplement to theSPT7610
data sheet to aid designers in achieving optimaldevice
performance.
Figure 1 Block Diagram, Rev C
The EB7610 comes with the SPT7610SIQ in an 44-leadcerquad
surface mount package directly soldered to theboard for optimum
performance. The EB7610 is capableof operating at clock rates up to
1 GSPS. (Clock rateshigher than 1 GSPS are possible but not
guaranteed.) Theblock diagram of the board is shown in figure 1.
Note thatadequate air flow and a heat sink are necessary for
opti-mum performance of the ADC.
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SPT 2 1/12/01AN7610
SPT7610 ADC OVERVIEW
The SPT7610 has a guaranteed minimum sample rate of1 GSPS. Only
one 5.2 V power supply is required. Twoexternal references are
applied across the internal refer-ence ladder, which has a
resistance of 80 typical (60 minimum). The top reference is
typically 0 V or con-nected to AGND (analog ground). The device has
topforce and sense pins (VRFT and VRST) that are
internallyconnected together. These voltage force and sense pinscan
be used to minimize the voltage drop across theparasitic line
resistance.
The bottom reference is typically 1 V. The device alsohas bottom
force and sense pins (VRFB and VRSB) thatare internally connected
together. These can also beused to minimize the voltage drop across
the parasiticline resistance. Three additional reference taps (VR3
=0.25 V typ, VRM = 0.5 V typ, and VR1 = 0.75 V typ)are brought out.
These taps can be used to control thelinearity error.
All logic levels are compatible with both 10K ECL or 100KECL. It
is recommended that the clock input be driven dif-ferentially (CLK
and NCLK) to improve noise immunityand reduce aperture jitter.
The digital outputs are split into two banks of 6-bit wordsand
an overrange bit. Each bank is updated at 1/2 of theclock rate and
are 180 out of phase from each other. Thedifferential data ready
signals for each bank are providedto accurately latch each data
bank into the register. Theoutput data is in a straight binary,
inverted binary, twoscomplement or inverted twos complement format.
(Refer
to the data sheet for details.) Figure 2 shows a timing dia-gram
of the device and shows the input to output relation-ship,
clock-to-output delay and output latency. TheSPT7610 has a built-in
offset in the 2 clock divider (Dflip-flop) to assure that output
bank A will come up firstafter power turn on.
The full-scale analog input bandwidth is 750 MHz(1.4 GHz for
small signal bandwidth). The input capaci-tance is 8 pF (typical).
Power dissipation is specified at2.85 W maximum at +25 C. Adequate
air flow and aheat sink are necessary. The data sheet provides
therequired information necessary for heat sink selectionand
indicates the required air flow rates. Refer to theThermal
Management section of the SPT7610 datasheet.
SPT7610 TEST MODE FUNCTION
The SPT7610 supports a special test mode function thatoverrides
the SPT7610s internal data output latch stageand exercises the
digital outputs in an alternating test pat-tern. This enables the
user to test digital interface logicdownstream from the SPT7610
with a known set of digitaltest patterns.
Test mode pin 3 controls the SPT7610 mode of operationsuch that
when it is low, the SPT7610 operates in normalmode. When test mode
pin 3 is brought high, theSPT7610 will begin to output test pattern
1 (see table I) onthe next rising edge of the clock. (See figure
2.) It will out-put the test patterns alternating between test
pattern 1and test pattern 2, as long as test mode pin 3 is held
high.The minimum set-up time (tsu) can be as low as 0 nsec.
Figure 2 SPT7610 Timing Diagram
2
FIRSTRISING EDGE
POWER ON
8
OUTPUTBANK A(DA0-6)
OUTPUTBANK B(DB0-6)
DRA
CLK IN
DRB
VIN
NDRA
NDRB
TEST
3 54
2
16
INVALID DATA 1
ADC (Normal Operation)
910
11
8
TEST MODE
7
tsu
tdr
tod
tdr
tod
ADC (Normal Operation)
INVALID DATA
INVALID DATA INVALID DATA
7 9Bank A Test Pattern 1: - Even Bits = Hi - Odd Bits = Low
Bank B Test Pattern 1: - Even Bits = Hi - Odd Bits = Low
Bank A Test Pattern 2: - Even Bits = Low - Odd Bits = Hi
Bank B Test Pattern 2: - Even Bits = Low - Odd Bits = Hi
LOGIC LOW
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SPT 3 1/12/01AN7610
Only the digital output stage is involved in the test
modeoperation. All ADC stages before the digital output
stagecontinue normal data conversion operation while testmode is
active. When test mode pin 3 is brought back low,the SPT7610 will
resume output of valid data on the nextrising edge of the clock.
The valid data output will corre-spond to a two-clock-cycle
pipeline delay as shown infigure 2.
Table I SPT7610 Test Mode Output Bit Patterns
D6 D5 D4 D3 D2 D1 D0Test Pattern 1 1 0 1 0 1 0 1Test Pattern 2 0
1 0 1 0 1 0
OPERATION AND CALIBRATION
POWER SUPPLIES AND GROUNDING
Inside the SPT7610 every circuit is biased from AGND toAVEE
(analog), except the DGND pins. This includes theclock input
circuitry. To minimize any ground loops and tooptimize performance,
all interfacing circuits must bereferenced to the appropriate
grounds.
The reference, analog input, and clock input drivers are tobe
referenced to AGND. The DGND pins, digital outputloads, and all
logic interfacing circuits are to be referencedto DGND. The block
diagram on page 1 indicates clearlywhere the AGND and DGND are
split. The AGND andDGND are tied to each other through a ferrite
bead asclose to the converter as possible. The EB7610 requiresthree
power supplies as listed in the table below.
Table II EB7610 Power Supply Requirements
Supply Voltage Range (V) Typical CurrentMin Typ Max (mA)
A5.2V 4.95 5.2 5.45 1000D2V 1.95 2.0 2.2 1200D4.5V 4.20 4.5 4.8
500
Figure 3 is the recommended power supply hookup for
theevaluation board. SPT recommends that all power sup-plies be
turned on and off at the same time via a powerstrip.
Table III Initial Setup of Board Jumpers/DipSwitches
OptionJumpers Status Switch Status
JB1 ..................... Short J6A,
JA1............................ OpenJ2 ........................
Short J6B .................................... OpenJ3
........................ Short J9A
.................................... ShortJ4
........................ Short A/B SEL ....................... LO
or HIJ5A ..................... Short S0
........................................... HIJ5B
..................... Short S1
........................................... HI
SW5, SW6, SW7, SW8 ........ LO
PROCEDURE FOR VERIFYING BOARD OPERATION
To verify correct board operation: Connect power supplies and
generators (leave off). Set jumpers and dip switches to proper
configurations.
(See table III.) Turn on clock generator and set to 499.712 MHz
and
1 VP-P. Turn on analog input generator and set to 3.965 MHz
and 1 VP-P. Turn on all power supplies and observe the 61
kHz
sinewave at the scope (64 points/period).Refer to Beat Frequency
Technique section for moredetail.
REFERENCE CIRCUIT
Referring to the detailed schematic (see figure 8), D1 is a1.2 V
Zener diode. R1 potentiometer is used as a refer-ence adjustable
voltage to give 1.0 V 0.005 V at theVREF test point. This voltage
is then buffered with U4A anddrives Q1, which is set up as an
emitter follower. The emit-ter follower is necessary to sink up to
17 mA through thereference ladder (based on 1 V reference and 60
mini-mum ladder resistance). U4 (a low voltage rail-to-rail
quadop-amp) is powered from GND to 5.2 V. The selection ofU4
prevents the reference from going positive duringpower on and keeps
it to within the maximum rating(+0.5 V to AVEE).
The top reference is connected to AGND if JB1 is in-stalled. The
top reference may be driven externallythrough the VRT banana jack
(with respect to AG3 bananajack) by installing a jumper at JA1
instead of a jumper atJB1.
The SPT7610 has three reference ladder taps broughtout. These
taps can be forced to their theoretical voltageto correct the bow
in the transfer curve due to the injectionof the pre-amp input bias
currents into the reference lad-der. VR3 is the 1/4 scale tap, VRM
is the mid-scale tap, andVR1 is the 3/4 scale tap. For example,
when VRTF = 0 V andVRBF = 1.0 V, VR3, VRM and VR1 should be forced
to0.250 V, 0.500 V and 0.750 V respectively. Each tap isprovided
with its test point. The potentiometers R2, R3,and R4 are provided
for voltage adjustments to the taps.
Figure 3 Configuration of Power Supplies
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SPT 4 1/12/01AN7610
A 2.2 F decoupling capacitor in parallel with 0.1 F and100 pF
surface-mount capacitors is recommended for allreference pins
(VRTF, VR1, VRM, VR3, and VRBF). These ca-pacitors should be placed
as close to the pin as possible.(The smallest value should be the
closest.)
ANALOG INPUT
SPT was not able to locate an op-amp suitable to drive
theSPT7610. It requires a bandwidth of at least 800 MHz andat least
40 dB of distortion. Given an input capacitanceof 8 pF, the
required peak driving current is 2C=20 mA,for =400 MHz.
For AC input into the EB7610, connect the analog inputinto the
VIN SMA. C51 is for coupling to the DUT. Applying0.5 V to the VOS
banana jack (referenced to AGND) willoffset the input to meet the 0
to 1 V input range of theADC.
If DC input is required, inject the analog input through theVOS
test point and place a ground cap on the VIN BNC.Figure 4 shows the
DC-coupled input circuit with this con-figuration. Note: R34 is
socketed.
Turn all power supplies on. Monitor the A2 test point with DVM
and adjust the R5
potentiometer for 2 V 10 mV. Monitor the SB test point with DVM
and adjust the R1
potentiometer for 1 V 5 mV. Measure/record VFT and VFB test
points with DVM. Monitor the VR3 test point with DVM and adjust the
R2
potentiometer for $-3%$-
+ VFT.
Monitor the VRM test point with DVM and adjust the R3
potentiometer for $-3%$-
+ VFT.
Monitor the VR1 test point with DVM and adjust the R4
potentiometer for $-3%$-#
+ VFT.
DIGITAL OUTPUT BUFFER/DECIMATION CIRCUIT
With the exception of U3 (10K logic family), all
interfacinglogic chips (U8U16) are 100K logic family. The
SPT7610requires an immediate digital output buffer. The digital
out-puts are compatible with both 10K or 100K ECL logic fami-lies.
All digital outputs are pulled down to digital 2 Vthrough 49.9
resistors. U8 is the Motorola MC100E167,2:1 MUX register. Each
6-bit digital output bank A or bankB is selected through U8 with an
A/B switch. The selecteddata bank is updated at the rate of the
data ready signaldivided by 4:
U11 is a programmable delay. U12 is the exclusive-or acting as a
buffer or inverter
with the A/B switch (S2). U13 is the divide-by-4 counter.
Note that the data ready signals for bank A and for bank Bare
opposite in phase. (See the SPT7610 timing diagram.)
U8 requires a minimum of 100 ps of setup time and 300 psof hold
time. To meet these requirements, set delayswitches S0S3 to logic 0
(down) and set R7 to mid-range.R7 is a fine-tune delay control for
U11, which gives arange of 0 to 80 ps from 0 to 4 V.
The second decimation is through U9 which is a hex D flipflop.
U14 is the 2, 4, 8 clock generation chip. The de-sired divider
value is selected through U15 (4:1 MUX) withS0 and S1 switches.
(See table V.)
U16 is a clock distributor for U9, U5 (DAC) and the
P1connector.
Table IV S0, S1 Setup
Overall Decimation (N)S1 S0 with Respect to CLK0 0 640 1 641 0
321 1 16
CLOCK CIRCUIT
The clock input driver uses a MC10EL16 (U3), which is asingle
10K ECL family logic differential line receiver. Its in-put is set
up for AC coupling from a 1 VP-P (CLK IN) withR35 (49.9 terminating
resistor) connected to VBB. TheCLK IN signal (1 VP-P 10%) must be
present to pre-vent U3 from oscillating as the two inputs are
bal-anced. It is important to note that the input commonmode range
for U3 is 0.4 V maximum. U2 is a 2 Vregulator (from analog 5.2 V)
used only for U3 outputload pulldown. Note that the clock circuits
are biased fromthe analog supply. This is critical to maintain the
optimumperformance.
CLK and NCLK test points are provided on board. Thesetest points
physically resemble those in the schematic.The physical layout of
the test points provides a shortground path to the scope probe
ground.
EB7610 CALIBRATION
All measurements are with respect to AGND. Hook up power
supplies as shown in figure 3. Refer to the initial setup section
for jumper/switch
setup.
Figure 4 DC-Coupled Input Configuration
.
/
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SPT 5 1/12/01AN7610
DATA RECONSTRUCTION DAC
The decimated encoded data is reconstructed and thesignal can be
viewed through the DAC OUT SMA. U24(SPT1018 or SPT1019) is a 275
MWPS, 8-bit video DAC.It is set up for a fixed gain with an output
range from 0 to19 mA into a 51 load (R90 socket) or 0 to 960 mV.
Alarger output voltage range can be attained by replacingR90 with a
larger value as long as the output stays withinthe DAC output
compliance voltage range of 1.2 V.
BOARD LAYOUT AND DESIGNCONSIDERATIONS
Both Microstrip and Strip Line PCB board technologieshave
predictable characteristic impedances that can becontrolled to
within 5%. Figure 5 shows the basic crosssection of each
technology. For G-10 dielectric material,the propagation delay of
the line is typically 148 ps/in forMicrostrip and 188 ps/in for
Strip Line. Note that thepropagation delay is independent of line
width.
The following is an outline of some of the key guidelinesused in
the design of the EB7610 evaluation board:
1. Minimize the logic fan-out. Most of them have a fan-outof
only one.
2. Avoid, if possible, any through-hole vias between thesending
and receiving end of any high-speed lines. Apin-out pattern of the
logic that requires criss-crossingof high-speed lines should be
avoided if possible.
3. The loading resistor should be as close to the receivingend
as possible on all high-speed lines.
4. All unterminated (open) lines must be less than 1/4 ofthe
rise time of the signal divided by the transmissionline propagation
delay to assure minimal reflection:
Open Line Length (inches) < 1/4 x (trise / tpd)
where: trise = rise time of the signal (ns)
tpd = 0.188 ns/in (Strip Line characteristic)
tpd = 0.148 ns/in (Microstrip)
Table V shows the typical rise times versus the majorhigh-speed
logic families with a fan-out of one.
5. Use a series damping resistor when an open line ex-ceeds the
1/4 x (trise / tpd) maximum.
6. Keep the analog circuitry separate from the digital
cir-cuitry, including isolation of grounds. AGND and DGNDmust be
tied together through a ferrite bead or an in-ductor as close to
the ADC as possible.
7. Ensure adequate decoupling of the supplies.
8. Surface mount resistors and capacitors work better
forhigh-speed designs.
Table V Typical Rise Times versusMajor High-Speed Logic
Families
ECL ECL SYNERGY SYNERGY SPECL10K 10KH 100E 100S SONY
trise (ns) 23.5 1.1 0.30.4 0.7 0.30.4
CHARACTERIZATION OF THE SPT7610USING THE EB7610 EVALUATION
BOARD
This section has recommendations for how best to char-acterize
the SPT7610 using the EB7610 evaluation board.The intent is to
provide some basic principles and meth-ods of characterization that
will enable the optimal perfor-mance of the SPT7610 to be viewed
and characterized sothe proper design considerations can be
made.
RECOMMENDED TEST SETUP
Figure 6 shows a simple block diagram of the recom-mended test
setup.
Due to the complexity of the EB7610 design, both tech-niques
were used to make routing easier. The line width is10 mil and has a
50 characteristic impedance. It is aneight-layer board stacked in
the following manner:
Layer 1 = First controlled impedance signal
layer(Microstrip)
Layer 2 = Ground layer*Layer 3 = Second controlled impedance
signal layer
(Strip Line)Layer 4 = Ground layer*Layer 5 = Third controlled
impedance signal layer (Strip
Line)Layer 6 = Ground layer*Layer 7 = Power layer (all supplies
share the same layer)Layer 8 = Fourth controlled impedance signal
layer
(Microstrip)*AGND and DGND share the same layer.
To minimize the logic skew, the line lengths in each stageare
closely matched to within 0.05 inch, especially be-tween the A/D
output and the second decimation circuit(U8).
Figure 5 Cross Sections of Microstrip andStrip Line PCB Board
Technologies
Ground
Dielectric
Signal
Dielectric
Ground
Ground
Dielectric
Signal
Microstrip Strip Line
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SPT 6 1/12/01AN7610
Figure 6 AC Test Setup Block Diagram
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SPT 7 1/12/01AN7610
The input frequency is calculated as follows:
IN = n C B
where:C = S/N Capture frequency
(Decimated frequency at P1)n = integerB = C / S Beat frequencyS
= Number of sample points
EXAMPLECapturing a 4096 point FFT at the P1 connector with
thefollowing constraints is desired:
S = 750 MHzIN = 50 MHz and 100 MHzMaximum update rate of the
memory = 20 MHz
Solution:
a. For N = 64C = S/N = (750 x 106) / 64 = 11.71875 MHz < 20
MHz
b. The beat frequency:B = C/4096 = 2861.022949 Hz
c. Round off B to eliminate round off errors and toimprove
source resolution:B = 2860, then work backwards:C = B x 4096 =
11.71456 MHzS = C x 64 = 749.73184 MHz
d. For n = 4, IN = 4 x C + B = 46.8611 MHzFor n = 9, IN = 9 x C
B = 105.4339 MHz
e. ConclusionsS = 749.73184 MHzIN = 46.861101 MHz and 105.4339
MHzN = 64
For convenience, table VII shows example setup param-eters for
4096-point beat frequency tests.
Method 1 Characterization Through the DACOutputWith the setup in
table VII, the DAC output signal would bea sinewave at B and
consists of 4096 points/period(1/B). The DAC reconstruction signal
is used to ensureproper setup of the evaluation board and can be
useddirectly for characterization purposes. The performance ofthe
device can be viewed from DAC Out signal with aspectrum
analyzer.
The analog input offset and gain can be adjusted by moni-toring
the DAC Out with a scope.
The DAC Out signal can be used to verify the delay of theclock
to the first stage decimation so that the setup andhold times are
met. Refer to the Digital Output Buffer/
Decimation Circuit section and set the delay line
switchesaccordingly until no glitches or spikes appear in the
DACoutput signal.
Method 2 Noise Characterization Through DACOutputNoise is
inherent to an ADC as a DC noise or noise floor. Itcould be
identified simply by inputting a DC input andmeasuring the number
of code counts. The simpler andmore accurate way to measure this
noise is to input a slowramp and measure the code transition noise
through theDAC output. The slope of the ramp input suggests at
least10 capture data per LSB or slope (LSB x C)/10.
With certain types of ADCs, this transition code noisechanges
with the input frequency. The beat frequencytechnique offers a tool
for characterizing the code transi-tion noise at higher input
frequencies. Table VII is thesetup for S = 4096 points per beat
period. The code transi-tion noise could be viewed through DAC Out
with a scopeby reducing S to a much smaller number of points
perperiod (32 or 64 points).
Method 3 Characterization Through the P1ConnectorFrom table VII,
4096 points FFT can be performed fromthe data output at P1 (37-pin
D shell connector). Refer tothe detailed schematic in figure 8 for
the pin assignment.Note that the reconstruction DAC output signal
should beused before an FFT is taken to verify proper setup of
theevaluation board (decimation setup and delay lineswitches) and
analog input signal (offset and gain).
Table VII 4096-Point Beat Frequency Test Setup
N (Deci- BS (MHz) IN (MHz) mation) C (MHz) (Hz) n
500.039680 46.882535 32 15.62624 3815 3500.039680 109.387495 32
15.62624 3815 7500.039680 156.266215 32 15.62624 3815 10500.039680
203.144935 32 15.62624 3815 13500.039680 296.902375 32 15.62624
3815 19500.039680 406.286055 32 15.62624 3815 26749.731840
46.861100 64 11.71456 2860 4749.731840 105.4339 64 11.71456 2860
9749.731840 152.29214 64 11.71456 2860 13749.731840 199.15038 64
11.71456 2860 17749.731840 304.58142 64 11.71456 2860 26749.731840
398.2979 64 11.71456 2860 341001.39008 46.94398 64 15.64672 3820
31001.39008 93.88414 64 15.64672 3820 61001.39008 156.47102 64
15.64672 3820 101001.39008 203.41118 64 15.64672 3820 131001.39008
297.2915 64 15.64672 3820 191001.39008 406.81854 64 15.64672 3820
26
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SPT 8 1/12/01AN7610
Figure 8 EB7610 Detailed Schematic, Rev C
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C48
C17
C26
C18
2.2 F
100 pF
0.1 F
+2.2 F
100 pF
0.1 F
+2.2 F
100 pF
0.1 F
+
C9
C10
N
OT
ES
:
1)X
= 4
9.9
r
esis
tors
to -
D2
or 5
1
for
SIP
2)
= T
est P
oint
3)
= S
peci
al P
robe
Tes
t Poi
nt
(phy
sica
lly a
s sh
own)
4)F
Bx
= F
errit
e B
ead
# x
5)U
nspe
cifie
d ca
paci
tors
are
0.0
1 F
sur
face
mou
nt c
aps
6)U
nspe
cifie
d re
sist
ors
are
49.9
s
urfa
ce m
ount
res
isto
rs
CLK
RE
FLSB+
10C
11
2.2 F
100 pF
0.1 F
+
33
1N29
07A
100
pF
100
pF
100
pF
100
pF
0.1
F
0.1
F
0.1
F
0.1
F
-A5.
2
-A5.
2
10 F
+
.1 F
C2
AG
NDC
28
FB
9
C86
C82
C88
C89
FB
10
C40
C41
C42
C43
C50
C51
C52
C53
C54 C
55
C56
C57
C58
C59
C1
C61
C62
C63
C64
C65
C66
C68
C69
C74
C75
C76
R1
R2
R3
R4
R10
R11
R12
R13
R14
R15
R18
R19
R20
R21
R22
R25
200
120
+
+
-A2
VOUT
VIN
Adj
LM33
7
2
10 F
-A5.
2
D2
D3
C8
C19
R5
R26
R27
R28 R
29
R30
R33
R34
1 k
R23
R35
R40
R41
-D4.
5
11X X
C67
R44
R45
R46 R
47R
48
R49
R50
R51
R52
R53
R11
5
R55
R66
R67
R68
R69
R70
R71
R72
R73
R74
R75
R76
R77
R81
R82
R83
R78
R79
R80
RN
4
RN5
RN
6
R87
D6B
6D
6A
10,1
6,22
DG
D6B
17
D6A
R42
R43
X X
2 28
MIN
V
LIN
V
MIN
V
LIN
V
3Te
stTe
st
CLK
/8
CC
LK
3
2
78
5
1
6
4
100EL
11
XX
R56
R57
16
(-1.
00 V
)
+1/4(
AD
491)
-D2
C77
P1
FB8
J6AJ6B
J5AJ5B
R1
-D2
100E
L34
MR
10
9
/EN
15
VB
B(2,
4,8)
C70
C73
R16 R17
-D2
R11
0
-D2
-D4.
59 16 15 14
S0 S1
VIH
-D2
100
R11
1
D4
C71
R63
-D2
-D4.
5
XX
C72
R62
R64
R65
100E
L57
/D1
D2
/D2
D3
/D3
/D0
D1
D0
Sel
0
Sel
1
U15
(4:1
MU
X)
CK
XX
R58
R59
R84
R95
R96
R94
R93
R92
R91
DG
1D
G2
FB
3
-2-D
4.5
.1F
10F
+.1
F
10 F
+
- D
2-
D4.
5D
GN
DD
GN
D
C3
C4
C29
C30
-D2
C80
C82
C84
C85
C78
R88
R89
R11
2
R85
R86
33
RN3
-D2
FAN
S P
OW
ER
+5V
MIN
I FA
N
+-
C31
C21
C202 3
IN /IN
7-9,
20
Q14
12,1
5,16
1
-D2
X XR9
R8
J9
Hea
tS
ink
C34
C81
C83
C79
C33
C35
C36
C12
100E
196
D3
D2
D1
D0
LEN
-D2
AB
VIH
28 /QX13
A/B
SE
L
2726
2524
01
23
(Del
ayLi
ne)
R6
R7
18
FT
UN
E
C5
R31
A
B
-
SPT 9 1/12/01AN7610
Figure 9 Timing Diagram, Rev C
U12(S2 = 0)
U13 ( 4)
0.65
U8
0.5
0.3
U14
U15
U16
U9
U10
0.65
1.1
0.63
0.8
0.25
N-3N-11
N-3
N-11-4xn N-3
N+1N+2
N-1 N
N+3
N+4
DRA(REF ONLY)
CLK(1GSPS)
U11 *(Tap = 0)
OUTPUT B N-3
OUTPUT A
DRB 1.4
N-1 N+1
NN-2N-4
N-5
N-6
0.9
1.4
N-11-4xn , where n = selected second decimations factor
*U11 output has a delay of 1.4 ns. See table VIII for additional
delay times.
Table VIII U11 Output Delay Table
Typical TypicalAdditional Total
SW8 SW7 SW6 SW5 Delay (ps)* Delay (ps)*0 0 0 0 0 1,4000 0 0 1 18
1,4180 0 1 0 35 1,4350 0 1 1 53 1,4530 1 0 0 70 1,4700 1 0 1 88
1,4880 1 1 0 105 1,5050 1 1 1 123 1,523
Typical TypicalAdditional Total
SW8 SW7 SW6 SW5 Delay (ps)* Delay (ps)*1 0 0 0 140 1,5401 0 0 1
158 1,5581 0 1 0 175 1,5751 0 1 1 193 1,5931 1 0 0 210 1,6101 1 0 1
228 1,6281 1 1 0 245 1,6451 1 1 1 263 1,663
*FTune has a range from 0 to 80 ps, 0 to 4.0 V respectively.
-
SPT 10 1/12/01AN7610
Table IX EB7610 Bill of Materials
# Reference Part Number Description Qty Manufacturer1 C2-4
ECS-T1DC106R 10 F 20 V Tantalum Chip Cap 3 Panasonic/Any2
C5,12,50-59,61-73, 12062R103K9B20D .01F Chip Cap 30 Philips /
Any
75-77,90,913 C6-11,19,27 ECS-T0JY106R 10 F 6.3V Tantalum Chip
Cap 8 Panasonic/Any4 C1,13-18 ECS-T1CY225R 2.2 F Tantalum Chip Cap
7 Panasonic/Any5 C20-26,28-39,74,78-89 12062R104K9B20D .1 F Chip
Cap 32 Philips / Any6 C40-48 1206CG101J9B200 100 pF Chip Cap 9
Philips / Any7 D1 ICL8069CCZQ-2 1.2 Volt Reference 1 Maxim8 D2-4
1N4001 Axial Diode 3 Any9 FB1-10 EXC-ELSA35V Ferrite Bead 10
Panasonic
10 J1 745189-1 37-Pin Vert Fem D-Sub Conn. 1 Amp11 J2-11
PZC36SAAN Jumper Pins (trim from 36-Pin) 1 Sullins12 J12-14
142-0701-201 RF (SMA) Connector 3 Johnson13 J15-23 108-0740-001
Banana Jack 9 Johnson14 Q1 2N2907A PNP Transistor 1 Fairchild15
R1-4,7 3266W-1-102 1K Potentiometer 5 Bourns16 R5 3266W-1-200 200
Ohm Potentiometer 1 Bourns17 R6 MFR-25FBF 2000 200 Ohm Axial
Resistor [socketed] 1 Yageo / Any18 R8,9,16-18-22,24,31,35,
ERJ-8ENF49R9 50 Ohm Chip Resistor 67 Panasonic/Any
40-45,47-59,62-89,90-96,110,112
19 R10-15,23 ERJ-8ENF1001 1K Ohm Chip Resistor 7 Panasonic/Any20
R25 ERJ-8ENF2671 2.67K Chip Resistor 1 Panasonic/Any21 R26,46,111
ERJ-8ENF1210 121 Ohm Chip Resistor 3 Panasonic/Any22 R27-30
ERJ-8ENF22R1 22 Ohm Chip Resistor 4 Panasonic/Any23 R33,34
MFR-25FBF 51R1 51 Ohm Axial Resistor [socketed] 1 Yageo / Any24
RN3,5 EXB-H8E470J 47 Ohm SMD Res Network 2 Panasonic25 RN4,6
766-143-R33 33 Ohm SMD Res Array 2 CTS26 S0-2,SW5-8 EG1218 Slide
Switch 7 E-Switch
SW9-11 > Do Not Load27 TP1-20 40F6045 Solder Terminal 20
NEWARK28 U1 SPT7610 6-Bit, 1 GSPS ADC 1 SPT29 U2 LM337H Adj. Neg.
Volt Regulator 1 National30 U3 MC10EL16D Diff. Receiver 1 ON
Semi.31 U4 TLV2464CD R-R Op Amp 1 Tex. Instr.32 U5 SPT1019AIN 8-Bit
DAC 1 SPT33 U8 MC100E167FN 6-Bit, 2:1 Mux-Register 1 ON Semi.34 U9
MC100E151FN 6-Bit, D-Register 1 ON Semi.35 U10 SY100S350JC Hex
D-Latch 1 Synergy36 U11 MC100E196FN Prog. Delay Chip 1 ON Semi.37
U12 MC100EL07D XOR / XNOR Gate 1 ON Semi.38 U13 MC100EL33D Divider
/ 4 1 ON Semi.39 U14 MC100EL34D Clock Gen. Chip 1 ON Semi.40 U15
MC100EL57D 4:1 Diff. Mux 1 ON Semi.41 U16 MC10EL11D 1:2 Diff.
Fanout Buffer 1 ON Semi.42 N/A ED5044-ND Pin Receptacles [for
socketed parts] 6 DIGI-KEY43 N/A 929955-06 Shunt for Jumper 10
DIGI-KEY (3M)44 N/A 2206K-ND1 1.5" Spacer 4 DIGI-KEY45 N/A H143-ND1
4-40 Pan-head Screw 4 DIGI-KEY46 EB7610 Rev C Evaluation Board 1
SAS
1Mount in four corners as bottom side legs.
-
SPT 11 1/12/01AN7610
Figure 10 Top Layer Component
-
SPT 12 1/12/01AN7610
Figure 11 Layers 2, 4, 6 Ground
-
SPT 13 1/12/01AN7610
Figure 12 Layer 3 Inner Signal Layer 1
-
SPT 14 1/12/01AN7610
Figure 13 Layer 5 Inner Signal Layer 2
-
SPT 15 1/12/01AN7610
Figure 14 Layer 7 Power
-
SPT 16 1/12/01AN7610
Figure 15 Bottom Layer Solder