EE130 Lecture 41, Slide 1 Spring 2007 Lecture #41 QUIZ #6 (Friday, May 4) • Material of HW#12 & HW#13 (Lectures 33 through 38) – MOS non-idealities, V T adjustment; MOSFET I-V, effective mobility, body effect, and small-signal model • Closed book, no calculators; 6 pages of notes allowed • Review session today at 5PM in 521 Cory (Hogan Rm) OUTLINE Modern MOSFETs: • The short-channel effect • Source/drain structure • Drain-induced barrier lowering • Excess current effects Reading : Chapter 19.1, 19.2
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Spring 2007EE130 Lecture 41, Slide 1 Lecture #41 QUIZ #6 (Friday, May 4) Material of HW#12 & HW#13 (Lectures 33 through 38) –MOS non-idealities, V T adjustment;
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EE130 Lecture 41, Slide 1Spring 2007
Lecture #41
QUIZ #6 (Friday, May 4)• Material of HW#12 & HW#13 (Lectures 33 through 38)
– MOS non-idealities, VT adjustment; MOSFET I-V, effective mobility, body effect, and small-signal model
• Closed book, no calculators; 6 pages of notes allowed• Review session today at 5PM in 521 Cory (Hogan Rm)
OUTLINE Modern MOSFETs:
• The short-channel effect• Source/drain structure• Drain-induced barrier lowering• Excess current effects
Reading: Chapter 19.1, 19.2
EE130 Lecture 41, Slide 2Spring 2007
The Short Channel Effect (SCE)
• |VT| decreases with L– Effect is exacerbated by
high values of |VDS|
• This is undesirable (i.e. we want to minimize it!) because circuit designers would like VT to be invariant with transistor dimensions and biasing conditions
“VT roll-off”
EE130 Lecture 41, Slide 3Spring 2007
Qualitative Explanation of SCE
• Before an inversion layer forms beneath the gate, the surface of the Si underneath the gate must be depleted (to a depth WT)
• The source & drain pn junctions assist in depleting the Si underneath the gate – Portions of the depletion charge in the channel
region are balanced by charge in S/D regions, rather than by charge on the gate
less gate charge is required to reach inversion (i.e. |VT | decreases)
Drain Induced Barrier Lowering (DIBL)• As the source & drain get closer, they become
electrostatically coupled, so that the drain bias can affect the potential barrier to carrier flow at the source junction subthreshold current increases.
EE130 Lecture 41, Slide 13Spring 2007
Excess Current Effects
• Punchthrough
EE130 Lecture 41, Slide 14Spring 2007
Summary: MOSFET OFF State vs. ON State
• OFF state (VGS < VT):– IDS is limited by the rate at which carriers diffuse across the
source pn junction– Sub-threshold swing S, DIBL are issues
• ON state (VGS > VT):– IDS is limited by the rate at which carriers drift across the
channel– Punchthrough and parasitic BJT effects are of concern at