Spring 2006 1 EE 437 Lillevik 437s06-l8 University of Portland School of Engineering Advanced Computer Architecture Lecture 8 Project 3: memory agent Programmed.

Spring 2006

Lillevik 437s06-l8 1University of Portland School of Engineering

EE 437

Advanced ComputerArchitecture

Lecture 8

Project 3: memory agent

Programmed I/O

Direct memory access

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Project 3 system schematic

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Project 3 requirements

• Goal: memory bus agent

• Requirements– ROM: 0x00 – 0x1f– RAM: 0x20 – 0xff

• Fully decode: address and control buses

• Assume one master• Must generate ACK (tri-state)

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Project 3 traces

read ROM read ROM

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Project 3 traces, continued.

write RAM write RAM

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Project 3 traces, continued.

read RAM read RAM

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I/O design

• Separate I/O address space– Instructions for I/O operations: in, out– Address often referred to as a Port

• One address space– Known as “memory-mapped I/O”– All memory reference instructions may operate

on I/O data

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Memory mapped I/O example

• I/O device: USART

• Receiver– Control register: 0xffff 0000– Data register: 0xffff 0004

• Transmitter– Control register: 0xffff 0008– Data register: 0xffff 000c

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C8251 block diagram

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Assembly code

Definitions for memory-mapped devices

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Assembly code, continued.

Subroutines to read and write a byte

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Find flowchart for rcvbyte?

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Wait loop

• Programming technique– CPU continuously reads control register until

non-zero (ready bit set)– CPU reads/writes data to port

• Results in poor system utilization: both memory-mapped or separate I/O addresses

• Known as programmed I/O

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Disadvantages of programmed I/O?

1. Wasted cycles CPU

2. Not writing to bus if reading it

3. No work done on bus

4.

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Direct memory access

• Objective: avoid the disadvantages of programmed I/O (eliminate the busy loop)

• Technique– CPU writes to special controller (word count

and memory address)– CPU tells controller to start data transfers– CPU continues with other computing– CPU responds to interrupt from controller: ISR

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Role of DMA controller

• Accept initialization data from CPU

• Access I/O device and drive bus (master)– Input: read I/O device and write data to

memory– Output: read memory data and write to I/O

device

• Interrupt CPU when transfer complete

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Programmed I/O

Programmed I/O ties up CPU

Read I/O

Write memory

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DMA I/O

DMA requires little CPU overhead

Initialize

Multiple

transfers

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DMA time line

ISR ISR

Interrupt Interrupt

CPU and I/O concurrent in time

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DMA hardware view

n words n words

adr X

adr X+(n-1)

Memory

I/O device

buffer

System bus adr 0

adr n-1

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DMA initialization instructions?

1. Memory/destination address

2. How long, or how many

3. Tell it to start

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DMA controller architecture

Counts up from zero

Counts down to zero Preset counter

Word

Count

Data

Buffer

Memory

Address

Buffer

Address

Control

D

A

C

Xcvr

Xcvr

Xcvr

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Find flowchart for rcvbyte?Push $ra

Get rcv status

Char ready?

Read and echo char

Pop $ra

yes

no

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Disadvantages of programmed I/O?

1. CPU cycles result in little computing

2. Memory continuously accessed, possible contention with another CPU

3. One I/O access at a time

4. Bus heavily requested

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DMA initialization instructions?

1. Write start address

2. Write word count (or end address)

3. Write “go” command

Each write is to a specific DMA controller port address

Spring 2006 1 EE 437 Lillevik 437s06-l8 University of Portland School of Engineering Advanced Computer Architecture Lecture 8 Project 3: memory agent Programmed.

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