Spring 07, Apr 17, 19 Spring 07, Apr 17, 19 ELEC 7770: Advanced VLSI Design (Ag ELEC 7770: Advanced VLSI Design (Ag rawal) rawal) 1 ELEC 7770 ELEC 7770 Advanced VLSI Design Advanced VLSI Design Spring 2007 Spring 2007 Soft Errors and Fault-Tolerant Soft Errors and Fault-Tolerant Design Design Vishwani D. Agrawal Vishwani D. Agrawal James J. Danaher Professor James J. Danaher Professor ECE Department, Auburn University ECE Department, Auburn University Auburn, AL 36849 Auburn, AL 36849 [email protected][email protected]http://www.eng.auburn.edu/~vagrawal/COURSE/E77 http://www.eng.auburn.edu/~vagrawal/COURSE/E77 70_Spr07 70_Spr07
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Spring 07, Apr 17, 19 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2007 Soft Errors and Fault-Tolerant Design Vishwani.
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Soft ErrorsSoft Errors Soft errors are the errors caused by the Soft errors are the errors caused by the
operating environment.operating environment. They are not due to a permanent hardware fault.They are not due to a permanent hardware fault. Soft errors are intermittent or random, which Soft errors are intermittent or random, which
makes their testing unreliable.makes their testing unreliable. One way to deal with soft errors is to make One way to deal with soft errors is to make
hardware robust:hardware robust: Capable of detecting soft errorsCapable of detecting soft errors Capable of correcting soft errorsCapable of correcting soft errors Both measures are probabilisticBoth measures are probabilistic
Some Early ReferencesSome Early References J. von Neumann, “Probabilistic Logics and the Synthesis J. von Neumann, “Probabilistic Logics and the Synthesis
of Reliable Organisms from Unreliable Components,” pp. of Reliable Organisms from Unreliable Components,” pp. 329-378, 1959, in A. H. Taub, editor, 329-378, 1959, in A. H. Taub, editor, John von Neumann: John von Neumann: Collected WorksCollected Works, , Volume V: Design of Computers, Theory Volume V: Design of Computers, Theory of Automata and Numerical Analysisof Automata and Numerical Analysis, , Oxford University Press, 1963. Oxford University Press, 1963.
M. A. Breuer, “Testing for Intermittent Faults in Digital M. A. Breuer, “Testing for Intermittent Faults in Digital Circuits,” Circuits,” IEEE Trans. ComputersIEEE Trans. Computers, vol. C-22, no. 3, pp. , vol. C-22, no. 3, pp. 241-246, March 1973.241-246, March 1973.
T. C. May and M. H. Woods, “Alpha-Particle-Induces Soft T. C. May and M. H. Woods, “Alpha-Particle-Induces Soft Errors in Dynamic Memories,” Errors in Dynamic Memories,” IEEE Trans. Electron IEEE Trans. Electron DevicesDevices, vol. ED-26, no. 1, pp. 2-9, 1979., vol. ED-26, no. 1, pp. 2-9, 1979.
Interconnect coupling (crosstalk).Interconnect coupling (crosstalk). Power supply noise: IR-drop, delta-I.Power supply noise: IR-drop, delta-I. Effects generally attributed to alpha-particles:Effects generally attributed to alpha-particles:
Sources of Alpha-ParticlesSources of Alpha-Particles
Radioactive contamination in VLSI packaging Radioactive contamination in VLSI packaging material.material.
Ionosphere, magnetosphere and solar radiation.Ionosphere, magnetosphere and solar radiation. Other electromagnetic radiation.Other electromagnetic radiation.
Helium nucleus: two protons and two Helium nucleus: two protons and two neutrons, mass = 6.65 neutrons, mass = 6.65 ×10×10-27-27kgkg, charge = , charge = +2e (e = 1.6 +2e (e = 1.6 ×10×10-19-19C).C).
Error correcting effectsError correcting effects Transient pulse is filtered by gate inertiaTransient pulse is filtered by gate inertia Transient is blocked by an unsensitized pathTransient is blocked by an unsensitized path Transient is blocked by an inactive clockTransient is blocked by an inactive clock
Error enhancing effectsError enhancing effects Large number of gates can produce multiple Large number of gates can produce multiple
pulsespulses Fanouts can multiply error pulsesFanouts can multiply error pulses
Parts that can be affectedParts that can be affected Look-up table (LUT)Look-up table (LUT) Configuration memory cellConfiguration memory cell Flip-flopFlip-flop Block RAMBlock RAM
F. L. Kastensmidt, L. Carro and R. Reis, F. L. Kastensmidt, L. Carro and R. Reis, Fault-Fault-Tolerant Techniques for SRAM-Based FPGAsTolerant Techniques for SRAM-Based FPGAs, , Springer, 2006.Springer, 2006.
S. Mitra, N. Seifert, M. Zhang, Q. Shi, and K. S. S. Mitra, N. Seifert, M. Zhang, Q. Shi, and K. S. Kim, “Robust System Design with Built-In Soft-Kim, “Robust System Design with Built-In Soft-Error Resilience,” Error Resilience,” ComputerComputer, vol. 38, no. 2, pp. , vol. 38, no. 2, pp. 43-52, February 2005.43-52, February 2005.
Summary of Topics Covered (1)Summary of Topics Covered (1) Nanotechnology devicesNanotechnology devices Moore’s lawMoore’s law System level design for testability and test scheduling System level design for testability and test scheduling
Power consumption and low-power conceptsPower consumption and low-power concepts Multi-core parallelismMulti-core parallelism MicroprocessorsMicroprocessors MemoriesMemories
Timing optimizationTiming optimization Linear programming and clock constraintsLinear programming and clock constraints Clock skew problemClock skew problem Zero skew designZero skew design
Retiming, constraint graph and performance Retiming, constraint graph and performance optimizationoptimization
Soft errors and fault-tolerant designSoft errors and fault-tolerant design