SPICE MODEL

7/29/2019 SPICE MODEL

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C. Hutchens Chap 4 ECEN 4303 Handouts 1

CHAP 4 SPICE MOS MODELS

Q DIODES

Q NMOS and PMOS Transistors

Q ApproachQ Select a process i.e channel length driven acquire

.MODEL card for NMOS and PMOS devices

Q Enter the Schematic post designQ SPICE the VTC (.DC) and then Transient (.TRAN)

Q accurate results demand we enter AD,AS, PD,

and PSQ Layout the Design- DRC, extract and resimulate

Q LVS to verify schematic against extracted layout


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Key SPICE MODEL Parameters

Q DIODES

IS Is saturation current

RS R Series contact resistance NOT dynamic resistanceTT T Transit time forwardCJ Cj0 zero bias CapMJ mj Grading coiefficent exponent

PB built in potential


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SPICE MODEL Parameters

Q MOS TRAN

VT0 VTX threshold where X = N or P

U0 X mobility where X = n or pTOX tox gate oxide thicknessLD LD gate drain (source) overlap

GAMMA body threshold modulation parameterNSUB NX substate doping X = A or D for N or P MOS

PHI |2F| surface strong inversion potentialPB 0 built in contact potential junction to bulkCJ Cj0 zero bias bottom cap. for D-Bdy and S- BdyCJSW Cj-sw0 zero bias side wall cap. for D-Bdy and S- Bdy

LAMBDA 1/ recipocal forward early voltage 1/= VARX RE Series S and D contact resistance X = S o DMJ mj Grading coiefficent exponent junction bot.MJSW mj-swGrading coiefficent exponent junction

sidewall

CGD0 C d/W per unit width G-D and G-S overlap cap.


4/13C. Hutchens Chap 4 ECEN 4303 Handouts 4

SPICE LEVEL MODELS

Q Level 1 is primarily for academic discussion & HandCalculations.

Q Use Level 49 or BSIM3 or proprietary models

Q This is required to handle short channel effectsQ What are we using for hand analysis?

Q VTO, kn (kn), to determine effect Ron (or desired W

given L)Q CJ and CJSW along with AD, AS, PD and PS to

calculate the added cap due to the depletion capcontributions.

Q TOX along with the effective dielectric constant todetermine Cgs. Note we will limp Cgs = WLCox.

Q We need RS, RD and the poly sheet Res.in high

speed design



MODEL CARD EX 1



MODEL CARD EX 2



SPICE GUIDELINES

Calculate Rise and Fall times in advance.

Know the order of magnitude of the answer.

DIVIDE and Conquer approach.

KISS Principle.(keep it simple,stupid)

Use SPICE-spectre like a Bench Scope

Dont forget Body Ties when extracting.



LAYOUT EX

AD = AS = 7 X 4 = 28 2

PD = PS = 2 X 7 + 4 = 22

EX resistance of ploy looking into the ploy gate

Rg = Rpolysheet [(2/4) + (1 + 4 + 2 )/( 2 )]

Rg = Rpolysheet( 1/2 + 7/2)

Note this diagram does NOT show a body tie!!


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Diffusion verse Active Pullup EX

L

W

Figure 1

Rsegment /2 = R/2n Csegment =C/n

pp 237

Time Delay Equations

Diffusion

22

2 RCnDiffusion = (1)

=Rsegment Csegment and the effective trise is 1/2.

Lumped -Active or Passive RC

=

2

2

2.22.2

DD

DDLumped

VkpL

WV

RCt (2)

EXLumped ploy line

RCtLumped 2.22.2 = or

R = Rsheet-ployl/w, C = Csheet l w

R = 30sq.(1000m/4um) = 7.5k

C = 0.7fFd/um2

(1000um X 4um) = 280fF

COMPARE to Equation (1) to lumped wenote a factor of 2, 2.1 vs. 1.05nS.


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SPICE EXAMPLE

Beta matched invvdd 1 0 3.3.PROBE

.op

.include TSOS.libm1 2 5 1 1 pFET w=30u l=2u pd=30u ps=30u+ ad = 90p as= 90pm4 2 5 6 6 nFET w=15u l=2u pd=15u ps=15u

+ ad = 450p as= 45pVin 5 0 dc -0.dc vin 0 3.3 .05.tran 0 3.3 0.1nS 1nS 1nS 20nS 50nS.end

*NEURAL SOS LOT 911**TYPICAL CASE PARAMETERS, 1.25-10 MICRON, T=25 DEGREES C*********.MODEL NSS1_25U NMOS (LD=0.0E-7 XJ=1.0E-7 TOX=2.5E-8+ VTO=0.74 UO=376 NSUB=4.7E16+ UEXP=0.5 UCRIT=3.0E5 UTRA=0.5

+ GAMMA=1.0 LAMBDA=0.05 NFS=1.0E11+ LEVEL=2 PHI=.6 CJ=0.0 MJSW=3.33E-1+ CJSW=6.0E-11 MJ=5.0E-1+ CGSO=2.80E-10 CGDO=2.80E-10 RSH=200 )*********.MODEL PSS1_25U PMOS (LD=0.0E-7 XJ=1.0E-7 TOX=2.5E-8+ VTO=-0.9 UO=204 NSUB=1.0E15+ GAMMA=1.1 UEXP=0.2 UCRIT=8.0E4 UTRA=0.5

+ LAMBDA=0.035 NFS=1.0E11+ LEVEL=2 CJ=0.0E-4 MJSW=3.33E-1+ CJSW=3.0E-12 MJ=5.0E-1+ CGSO=2.8E-10 CGDO=2.8E-10 RSH=200 )


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SPICE as a Design Support Tool EXAMPLE

Approach

1. Synthesize logic

2. Determine transistor geomerties3. Validate DC VTC curves with SPICE

Noise margin logic

4. Estimate from geometries expected rise

and fall times5. Add appropriate loading and AD, AS,

PD AND PS to transistors as required.6. Using estimated raise and fall times

select .TRAN values (one must use afaster pulse 5-10X, to test the gate thanthe gates expected performance.

7. Execute SPICE and use waveformviewer to measure tr and tf.

8. Modify Ws as required and repeat ifnecessary.


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Tapered Buffer EX


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Tappered Buffer

SPICE MODEL

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