Desconectar alimentación de la tarjeta. Conectar cable USB entre board y PC Ubique Jumper J1 en la esquina superior derecha de la board, bien sea para programar la PROM de STMicro o la PROM de Atmel. Asimismo ubique los J23 y J25 para conectar el puerto JTAG a la memoria. Configurar los J26 y J46 de la siguiente forma para ir al modo Master SPI PLATFORM FLASH PROM Conectar cable USB tipo A-B a la FPGA y al PC. Se reconocerá e instalará en el PC tras lo cual se encenderá un LED verde en la tarjeta (El rojo indica la instalación de Firmware).
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Desconectar alimentación de la tarjeta.
Conectar cable USB entre board y PC
Ubique Jumper J1 en la esquina superior derecha de la board, bien sea para programar la PROM de STMicro o la PROM de Atmel. Asimismo ubique los J23 y J25 para conectar el puerto JTAG a la memoria.
Configurar los J26 y J46 de la siguiente forma para ir al modo Master SPI
PLATFORM FLASH PROM
Conectar cable USB tipo A-B a la FPGA y al PC. Se reconocerá e instalará en el PC tras lo cual se encenderá un LED verde en la tarjeta (El rojo indica la instalación de Firmware).
APENDICE
“Let's face it, in some applications, the easiest solution is the best solution. The best solutionfor these applications is either Internal Master SPI mode supported only by Spartan-3ANFPGAs or Master Serial mode using a Xilinx Platform Flash PROM, which is available forany Spartan-3 generation FPGA. These solutions use the fewest FPGA pins, have flexibleI/O voltage support, and is fully supported by iMPACT, the Xilinx JTAG-basedprogramming software.”ug332
The Xilinx Platform Flash PROM provides easy, JTAG-programmable configurationstorage for the FPGA. The FPGA configures from the Platform Flash using Master Serialmode.
The PROG push-button switch, labeled in Figure 4-1, forces the FPGA to reconfigure fromthe configuration memory source selected by the “Configuration Mode Jumpers,” page 39.Press and release this button to restart the FPGA configuration process at any time.
The DONE pin LED, labeled in Figure 4-1, lights whenever the FPGA is successfullyconfigured. If this LED is not lit, then the FPGA is not configured.
RESTRICCIONES UCF
# some connections shared with SPI Flash, DAC, ADC, and AMPNET "SPI_MISO" LOC = "AB20" | IOSTANDARD = LVCMOS33 ;