alessandro.bogliolo@uniurb. SPI-07 – May 14, 2007 Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication Channels Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication Channels Alessandro Bogliolo University of Urbino Nicola Terrassan and Davide Bertozzi University of Ferrara
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SPI-07 – May 14, 2007 Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication Channels Alessandro Bogliolo University.
SPI-07 – May 14, 2007 Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication Channels Motivation SPICE-based design space explorations are not viable due to system complexity Physical gap Hell of nano-scale physics 500M Transistor Platform Design-Productivity Gap Degradation of RC propagation delay across on-chip interconnects Low-swing signaling and coding for low-power Increased sensitivity to on-chip noise sources Development of accurate physical models and their abstraction into accurate compact models are mandatory for designing complex circuits
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Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication Channels
MotivationSPICE-based design space explorations are not viable due to system complexity
Physical gap
Hell of nano-scale physics
500M Transistor Platform
Design-Productivity GapIP coremasterIF
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Network on Chip
IP coremasterIF IP coremasterIF
IFIP coreslave IFIP coreslave
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Network on Chip
• Degradation of RC propagation delay across on-chip interconnects• Low-swing signaling and coding for low-power• Increased sensitivity to on-chip noise sources
Development of accurate physical models
and their abstraction into accurate compact models are mandatory for designing
Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication Channels
Power breakdown130nm 90nm
Total Power: 98,968 µW 38,532 µW
Scaling factor of power ranges from 0.24x (SAFF) to 0.52x (NOR Latch) Interconnect power increases by 1.1x FF, driver and receiver are the most power-hungry components Interconnect power relevant only in 90nm Overall channel power reduces by 60%
Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication Channels
Parametric NSA modelMeasured parameters are manipulated in order to use linear regressions to fit experimental data with a minimum number of fitting coefficients
Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication Channels
Delay model
0ww1dd
2 cCRcGnd)(V1cd
Inversely proportional to Vdd - Gnd
Directly proportional to Resistance and Capacitance per unit length
We did not derive fitting models of the delay measured from HSPICE simulations, but of those delay values that minimize the MSE of the fitting exponential
transients
We therefore aim at achieving maximum accuracyin predicting the far-end voltage Vin at sampling time
Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication ChannelsMacromodel integration in
SystemCNeed: expose the analytical models to a
high-level modelling and simulation environment Interconnect analysis with SPICE accuracy in complex systems Traditional macromodels integrated in VHDL/Verilog SystemC is emerging as the ref. backbone for system-level design C-language programming facilitates HW-SW codesign
Analytical macromodel integration in SystemC
We exploited theAdvanced and Flexible Communication Abstractions in SystemC Ports: gateways to communication functions Interfaces: declaration of communication functions Channels: actual implementation of communication functions
Accuracy results for 30 different mixes of noise sources
Average error at sampling time never worse than 2%, max. error less than 7% Risk of logic value misprediction if sampled voltage close to decision threshold
a warning is generated by the SystemC channel Accounting for Inter-Symbol Interference Simulation time improvements with SystemC by 10x
Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication Channels
Conclusions Design of a communication channel for high-performance on-chip links
targeting 1 GHz operating frequency at 130nm and 90nm techn. nodes low power, low swing signaling
Analytical modelling of channel behavior in presence of noise Noise sensitive area concept, delay and signal slope models
Macromodel integration into SystemC Powerful communication abstractions Plug-and-play backannotated channel Very high accuracy in predicting far-end voltage at sampling time
Average error below 2%, max error below 7% Improvement of simulation time by 10x Accounting for Inter-Symbol Interference
Macromodels at work for fast assessment of channel robustness against noise sources physical channel design space exploration