A. A. Jerraya Specification and Validation for Heterogeneous Multiprocessor SoC Specification and Validation for Heterogeneous Multiprocessor SoC Ahmed A. Jerraya, System-Level Synthesis Group TIMA Laboratory 46 Avenue Felix Viallet 38031 Grenoble Cedex France Tel: +33 476 57 47 59 Fax: +33 476 47 38 14 Email: [email protected]
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Specification and Validation for Heterogeneous .... A. Jerraya Specification and Validation for Heterogeneous Multiprocessor SoC Ahmed A. Jerraya, System-Level Synthesis Group TIMA
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A. A. Jerraya
Specification and Validationfor HeterogeneousMultiprocessor SoC
Specification and Validationfor HeterogeneousMultiprocessor SoC
MP-SoC Summer School, July 2001, Aix-les-Bains, France - 6Ahmed A. Jerraya
System-on-Chip Architectures
Application SW
CPUs, IP, Memory(DSP, MCU) (ASICs, COTs)
On-chip HW Communication Network
Resources management
SW Communication(drivers, I/O, interrupts)
HW
/SW
tra
de-
off
s
SW
HW
OS
■ SoC Architecture:g HW Componentsg Application Softwareg HW-SW Communication
■ On Chip network (HW)■ support Package (SW)
■ Programming Layer (SW)
■ Multilevel APIs required
■ Design Automationg HW component design: OK
g SW Application design: OK
g Architecture design: Stillneed to be invented
MP-SoC Summer School, July 2001, Aix-les-Bains, France - 7Ahmed A. Jerraya
Outline1. Multiprocessors SoC (MP SoC)
1.1. Multiprocessor SoC1.2. Multiprocessor SoC design1.3. This Course
2. Specification and validation of electronic systems2.1. Basic concepts2.2. Specification languages2.3. Heterogeneous systems modeling and validation
3. COLIF: A Design Model for MP SoCs3.1. COLIF: the Meta-model and the external syntax3.2. Mixed and multilevel model execution
4. A VDSL design example4.1. The application4.2. The design process
5. Summary
MP-SoC Summer School, July 2001, Aix-les-Bains, France - 8Ahmed A. Jerraya
Multi-Processor SoC Design
■ Design: produce an RTL multi-processorarchitecture and the corresponding supportsoftware from system specification
■ Key decisions:g Multiple vs. single OSg Static vs. dynamic allocation of tasksg Existing OS vs. Generated OSg Architecture platform vs. IP assembling
Platform baseddesign of embeddedsystems-on-chipW. Rosenstiel, U.Tuebingen & FZI
SESSION 2:
Multi-processorSOC
SESSION 3:
RTOS forEmbeddedSystems
Building Systems on aChip with Trimediatechnology K. Vissers,TriMedia Technologies
From Applications toMulti-Processor DSPArchitecturesP. Pirsch, U. Hannover
Energy-efficient designand manage-ment ofSoCsG. De Micheli,Stanford UReal-Time OperatingSystems: Principlesand a Case StudyK. Shin, U. Michigan
RTOS for EmbeddedSystems and SoCM. Potkonjak, UCLA
Real-Time Inter-Pro-cessor SynchronizationAlgorithmsH. Takada, Toyohashi UT
SESSION 4:
RTOS forEmbeddedSystems
From a distributedembedded RTOS to apragmatic frameworkfor multi-core SoC E. Verhulst, Eonic SolutionsTask-level run-timescheduling approachfor dynamic multi-media systems. F. Catthoor, IMECModeling real-timesystemsJ. Sifakis, Verimag
SESSION 5:
System-LevelArchitecture
SESSION 8:
System-LevelArchitecture
The Architecture ofMultiprocessor Systemson a ChipT. Mudge, U. MichiganSOC MultiprocessorArchitecture andModelingR. Ernst, TU BraunschweigArchitectural challengesand opportunities forsystems on a chipB. Rau, Hewlett-Packard
SESSION 6:
EmbeddedRT-SW
Challenges in NetworkProcessor Architecturesand Embedded S/WToolsP. Paulin, STMicroelectronicsF. Karim, STMicroelectronics
Multiprocessor SoCs for Video ProcessingW. Wolf, Princeton U.
Configuring the JazzVLIW-DSP Core forApplication SpecificRequirementsO. Levia, Improv Systems
Static scheduling forembedded systemsL. Lavagno, U. Udine
SESSION 9:
SoCValidationand Test
Communicationarchitectures for deep-submicron VLSISystemsJ. van Meerbergen, Philips
System Architectures:Hardware or Softwaredominant ? A CaseStudy: xDSL modemsM. Genoe, Alcatel
System on Chip:Embedded Test StrategiesY. Zorian, LogicVisionArchitecture and Imple-mentation of Application-Specific Multi-processorSOCs for Digital TV (DTV)and Media-ProcessingApplications, S. Dutta, Philips
Testing Future System-on-Chips: Challenges andEmerging TechniquesS. Dey, U. California, San Diego
MP-SoC Summer School, July 2001, Aix-les-Bains, France - 12Ahmed A. Jerraya
Outline1. Multiprocessors SoC (MP SoC)
1.1. Multiprocessor SoC1.2. Multiprocessor SoC design1.3. This Course
2. Specification and validation of electronic systems2.1. Basic concepts2.2. Specification languages2.3. Heterogeneous systems modeling and validation
3. COLIF: A Design Model for MP SoCs3.1. COLIF: the Meta-model and the external syntax3.2. Mixed and multilevel model execution
4. A VDSL design example4.1. The application4.2. The design process
5. Summary
MP-SoC Summer School, July 2001, Aix-les-Bains, France - 13Ahmed A. Jerraya
Electronic System Specification■ Basic Model: a set of hierarchically
interconnected modules representing an abstractarchitecture
■ Basic concepts:Module Interface Port
Operation on ports
Content Behavior
Instances
Communication channels
Module A Module B
SystemMedia
Behavior
Data unit
Different abstraction levels forbehavior and communication
MP-SoC Summer School, July 2001, Aix-les-Bains, France - 14Ahmed A. Jerraya
Abstraction levels in behavior
Untimed
SuperstateComputation/control step
Partial order
VHDL, SystemC,
Esterel
CSP, SDL
Typical model
InterconnectedFSMs
Gates
Synchronousscheduling
Communicating
processes
Typical language
RTL
Physical levelPhysical Time
(Delays)
C/K cycleVHDL, SystemC,
Verilog
VHDL/Verilog
Timing UnitAbstraction level
Behavioral model
MP-SoC Summer School, July 2001, Aix-les-Bains, France - 15Ahmed A. Jerraya
Abstraction levels in communication
Client server
Functional
Macro
architectureLogical
connection
Active Channel
Abstract
Network
VHDL, SystemC
SDL
CORBA / UML
Typicalcommunication
primitive
Set (Value, Port)
Wait (clock)
Write (Data, Port)Wait until x = y
Send(file, disk)
Print(file, network)
Typical Model
RTL (Micro
arcitecture
Physical
connection
VHDL, SystemC,
Verilog
Media
Communication Model
Abstraction level
MP-SoC Summer School, July 2001, Aix-les-Bains, France - 16Ahmed A. Jerraya
Modeling Concepts through the AbstractionLevel
Abstraction level
Object C-S level Functional
Macro-Architecture
RTL
Module Module Module Module Module
Port Network Access (SAP) Channel access Logical port Physical port
Operation Service request
Send/Receive to identified process Read/Write Data Set/Reset bits
BehaviorConcurrent
Objects Partially Ordered
TransactionsComputation/ control steps
Cycle-truecomputation
Instance Instance Instance Instance Instance
Communication Channel
Inte
rface
Co
nte
nt
- Media - Abstract Network - Active Channel - Abstract wires - Physical wires
■ Execution model through automatic wrapper generation
■ External Syntax: VADeL, a SystemC extension
■ Internal Syntax: XML
MP-SoC Summer School, July 2001, Aix-les-Bains, France - 33Ahmed A. Jerraya
COLIF: An Internal Model for Mixed &Multi-level Refinement
External syntaxe.g. SystemC, VADeL, ...
COLIF- Hierarchical
interconnect model- Design parameters
Implementation RTL:Synthesizable HW/Executable SW
SimulationModel
Communication refinement
Automaticcode generation
Simulation
MP-SoC Summer School, July 2001, Aix-les-Bains, France - 34Ahmed A. Jerraya
Target Architectureg Dissociate Components and communication network
g HW: Requires communication co-processors (wrapper, bridge)g SW: Multiple Application specific RTOS
IP(ASIC,
Memory)DSPMCU
Adaptor
Communication Networks
Adaptor Adaptor
CPU
AD
Mem
Adaptor
ProtocolCtrl #1
ProtocolCtrl #4
ProtocolCtrl #3
ProtocolCtrl #2
Internal Bus
CPU(IP)-Bus AdaptorOSDriver
R.M.
Application
g Enable both Automatic Design and Co-simulationg Cover both Hardware and Softwareg Systematic Assembling of heterogeneous existing blocs
MP-SoC Summer School, July 2001, Aix-les-Bains, France - 35Ahmed A. Jerraya
Heterogeneous System Specification■ Basic model: a set of hierarchically interconnected modules
■ Basic concepts:g Virtual Module
■ Interface, set of ports (internal, external)■ Content (Tasks / Instances + Communication channels)
System Specification
Not executable due to the difference btw. internal and external ports
External port
Internal port
Abs. level ProtocolMacro AL FIFO
RT level AMBA
B
C
A
MP-SoC Summer School, July 2001, Aix-les-Bains, France - 36Ahmed A. Jerraya
Heterogeneous System Specification■ Basic model: a set of hierarchically interconnected modules
■ Basic concepts:g Virtual Module
■ Interface, set of ports (internal, external)■ Content (Tasks / Instances + Communication channels)
System Specification
B
C
A
Wrapper
Communication Network
A
Wrapper Wrapper
B C
System Architecture
Executable/implementable by the generated wrappers
MP-SoC Summer School, July 2001, Aix-les-Bains, France - 37Ahmed A. Jerraya
Heterogeneous System Specification■ Basic model: a set of hierarchically interconnected modules
■ Basic concepts:g Virtual Module
■ Interface, set of ports (internal, external)■ Content (Tasks / Instances + Communication channels)
System Specification
Abstraction levels of communication- Service: client-server, e.g. CORBA - System: e.g. send/receive in SDL- Macro Architecture: e.g. FIFO- Micro Architecture (RT level): e.g. AMBA
B
C
A
MP-SoC Summer School, July 2001, Aix-les-Bains, France - 38Ahmed A. Jerraya
Virtual module
Wrapped module
VADel: a SystemC extensionfor COLIF execution
■ Embedded processor in
VADeLg Virtual Module annotated
with implementationparameters
g SystemC modules for eachtask or IP
g Virtual Ports forAbstraction-level/Language/Protocoladaptation
g Virtual nets to grouprelated SystemC signals
Task 1
■ VADeL
■ SystemC
Task 3Task 2
■ VADeL: Virtual Architecture Description Language
MP-SoC Summer School, July 2001, Aix-les-Bains, France - 39Ahmed A. Jerraya
VADeL - Mixed level specification
NiveauNiveauM. Arch.M. Arch.
NiveauNiveauSystèmeSystème
NiveauNiveauSystèmeSystème
............
VCVCT5T5
CounterCounter
ARM7ARM7
token3token3 ............
... ... ...... ... ...
#include <systemc.h>##include include <<vadelvadel.h>.h>
MP-SoC Summer School, July 2001, Aix-les-Bains, France - 52Ahmed A. Jerraya
Conclusions
■ Multiprocessor SoC: already a reality and main future driver
■ System Specifications: Few Concepts, Too many languages
■ Key issues for MP SoC specification/validation:
g On chip communication network abstraction,
g Execution and refinement for multi and mixed level model
■ COLIF: A Design Model for MP SoCs Specification
g Abstract wrappers to connect heterogeneous components
g Architecture generation through systematic HW-SW assembly
MP-SoC Summer School, July 2001, Aix-les-Bains, France - 53Ahmed A. Jerraya
Reading about system specification1. A. Lee and A. Sangiovanni-vicentelli, A Denotational Framework
for Comparing Models of Computation, ERL MemorandumUCB/ERL-M97/11, University of California, Berkley, CA 94720,January 1997.
2. A. Jantsch, S. Kumar, A. Hemani, « The Rugby Model: AMetamodel for Studying Concepts in Electronic System Design »,IEEE Design & Test of Computers, 2000, p. 78-85.
3. D. D. Gajski, J. Zhu, R. Zömer, A. Gerstlauer, S. Zhao, SpecCSpecification Language and Methodology, Kluwer AcademicPublishers, Boston, MA, ISBN 0-7923-7822-9, March 2000.
4. M. Sgroi, L. Lavagno, A.S. Vicentelli, « Formal Models for EmbededSystem Design », IEEE Design & Test of Computers, vol. 17, no.12, April-June 2000.
5. SystemC, available at http://www.systemc.org
6. R. Ernst, D. Ziegenbein, K. Richter, L. Teich, "Hardware/SoftwareCo-Design of Embedded Systems - The SPI Workbench," Proc.IEEE Workshop on VLSI'99, pp. 9-17, Orlando, 1999.
MP-SoC Summer School, July 2001, Aix-les-Bains, France - 54Ahmed A. Jerraya
Reading about system co-simulation
1. J.A. Rowson « Hardware/Software Co-simulation », proceeding Design
Automation Conference, 1994.
2. C.A. Valderrama, A. Changuel, P.V. Vijaya-Raghavan, M. Abid, T. Ben Ismail,
A.A. Jerraya, "A unified model for co-simulation and co-synthesis of mixed
hardware/software systems", European Design and Test Conference (EDAC-
ETC-EUROASIC'95), Paris, France, March 1995.
3. L. Séméria and A. Ghosh, “Methodology for Hardware/Software Co-
verification in C/ C++” , Proceeding of ASPDAC, 2001.
4. Seamless CVE, available at http://www.mentorg.com
5. C. Passerone, L. Lavagno, M. Chiodo, A. Sangiovanni-Vincentelli “Fast
hardware/software co-simulation for virtual prototyping and trade-off
analysis”, in Proceedings of Design Automation Conference, June, 1997
6. Coware, Inc. “N2C” , available at http : // coware.com/cowareN2C.html
MP-SoC Summer School, July 2001, Aix-les-Bains, France - 55Ahmed A. Jerraya
Reading about COLIF and theArchitecture design environment
1. S. Yoo, al. « A Generic Wrapper Architecture for Multi-Processor SoC Cosimulation and
Design », CODES, 2001.
3. W.O. Cesario, al. "Colif: a Multilevel Design Representation for Application-Specific