Special-Purpose Digital Circuits - RNBS Web page トッ … CMOS Design, H20/5/2 2 Necessary Functions other than Logic Operations CMOS logic circuits do contain more than only logic
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CMOS logic circuits do contain more than only logic gates.
1) Transmission of signals over long interconnection lines or to many receivers
- Buffer (inverting, non-inverting, tri-state)2) Selection of an interconnection for a Signal according to a condition
- Selector (multiplexer, demultiplexer)3) Storing an information for some time
- Flip-flop, latch4) Removing Noise from a Signal
- Trigger circuits5) Generation of Synchronous or Asynchronous Control Signal
- Multi-vibrator circuits (a-stable, bi-stable, mono-stable)6) Generation of other Voltages than VDD or VSS
- Voltage generator circuits
Mattausch, CMOS Design, H20/5/2 3
Buffer Circuits- Increasing the driving capability of a logic
signal for large load capacities- Conventional non-inverting buffers- Inverting buffers- Tri-state buffers
Mattausch, CMOS Design, H20/5/2 4
Reduction of Logic-Gate Fan-Out with a Buffer
The delay of a circuit with large fan-out (i. e. large output load) can be reduced with a buffer, if (k-1)·trex > tbuffer is valid.
NAND-gate withfan-out = k, fan-in = m
m
31
2
m-12
1
3
k
NAND-gate withfan-out = 1, fan-in = m
m
31
2
m-12
1
3
k
Non-inverting Buffer
)k(mm, fexfinNANDdf ttt ⋅+⋅⋅=rexrinNANDdr ttt ⋅+⋅= km,
Delay without buffer
bufferfexfinNANDdf tttt ++⋅⋅= )(mm,
bufferrexrinNANDdr tttt ++⋅= m,
Delay with buffer
Mattausch, CMOS Design, H20/5/2 5
Construction of Non-Inverting CMOS Buffers
Non-inverting buffers have even number of inverters. Each stage has a factor Ani-buffer (Cload,Cin) larger driving capability.
VSS
Cload
VoutVin
Vin
VSS
Cload
Vout
I1 I2 I2N-1 I2N
A 0 Wp
Wn
A1 Wp
Wn
A 2N −2 Wp
Wn
A 2N −1 Wp
Wn
Optimum choice of A and N
N21
1in
loadbufferni C
CA
=−
=−
1in
load21
bufferni C
ClnintN
(Cin1 is the input capacity of the 1st inverter)
Mattausch, CMOS Design, H20/5/2 6
Construction of Inverting CMOS Buffers
Inverting buffers use an odd number of cascaded inverters. Each stage has again Ai-buffer(Cload,Cin) larger driving capability.
VSS
Cload
VoutVin Optimum Choice of A and N
1N21
1in
loadbufferi C
CA
+
−
=
−
=− 2
1
1in
load21
bufferi C
ClnintN
Vin
VSS
Cload
Vout
I1 I2 I2N I2N+1
A 0 Wp
Wn
A1 Wp
Wn
A 2N −1 Wp
Wn
A 2N Wp
Wn
I3
A 2 Wp
Wn
(Cin1 is the input capacity of the 1st inverter)
Mattausch, CMOS Design, H20/5/2 7
Tri-State Inverter
A tri-state inverter has an additional high-impedance or floating output state selected with an enable signal. It can be
built with a conventional inverter and a transmission gate.
OutIn
Symbol
VDD
En
VSS En
In Out
En In Out
0 0 floating
0 1 floating
1 0 1
1 1 0
Truth Table
CMOS-Circuit Implementation
Mattausch, CMOS Design, H20/5/2 8
Tri-State Buffers
A tri-state buffer combines high driving capability for a large load capacity Cload and the possibility of a floating output.
non-inverting tri-state buffer
OutIn
En
CMOS-Circuit Implementation
OutIn
En
inverting tri-state buffer
VDD
VSS
En
In OutI1 I2 IN-1 IN
Mattausch, CMOS Design, H20/5/2 9
Path-Selector Circuits - Multiplexer- and Demultiplexer Principles- Implementation with Transmission Gates- Series Connection of Transmission Gates- Implementation with Tri-State Inverters or
Tri-State Buffers
Mattausch, CMOS Design, H20/5/2 10
Multiplexer and Demultiplexer Principles
Conditional signal-path selection is performed with multiplexer- or demultiplexer circuits.
123
N
NDataInputLines
OneSelected
DataOutput
NPossible0utputLines
123
N
OneDataInput
between ln(N) and NControl/Selector Lines
between ln(N) and NControl/Selector Lines
Multiplexer(MUX)
Demultiplexer(DEMUX)
Mattausch, CMOS Design, H20/5/2 11
Circuits
Multiplexer Realization with Transmission Gates
Path-selector realization is easiest by transmission gates.
En
In Out
In Out
En
Transmission Gates 4-Input Multiplexer
En
In Out
In Out
EnEn1 En2 En3 En4
In1
In2
In3
In4
Out
Symbols Minimum Transmission Gates
Minimum Select SignalsEn1 En2
In1
In2
In3
In4
Out
Mattausch, CMOS Design, H20/5/2 12
Series Connection of Transmission Gates
A series connection of N transmission gates represents an RC-chain. Therefore, its delay time increases with N2.