What’s VHDL? Basic What’s VHDL? Basic Concept Concept VHDL Very Hard Difficult Language Very High Speed Integrated Circuit Hardware Description Language Front end/Back end Design
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What’s VHDL? Basic What’s VHDL? Basic ConceptConcept VHDL
Very Hard Difficult Language
Very High Speed Integrated Circuit Hardware
Description Language
Front end/Back end Design
Why VHDL? (Using an HDL)Can be used to
Describing,
Modeling, and
Designing digital systems
For the goals of
Requirement specification
Documentation
Testing using simulation
Verification
Synthesizing digital circuits
VHDL DevelopmentVHDL Development
US DoD initiated in 80’sVery High Speed ASIC Description
LanguageInitial objective was modeling only and
thus only a simulator was envisagedSubsequently tools for VHDL synthesis
were developed
History of VHDL
•Launched in 1980 by Defense Advanced
Research Projects Agency (DARPA)
•July 1983Intermetrics, IBM and Texas
Instruments were awarded a contract to
develop VHDL
•August 1985 release of final version of the
language under government contract, VHDL
Version 7.2
December 1987IEEE Standard 1076-1987
1988VHDL became an American National Standards Institute (ANSI ) standard
In 1990 Cadence opened the language to the public
For RTL design VITAL added– VITAL(VHDL Initiative Towards ASIC
Library)– IEEE revised VHDL & VITAL in 1993
SeptemberFinal review of standard in 2001
VHDL vs. VerilogVHDL vs. Verilog
Complex grammar– Complicated
compiler– Large memory for
simulation– Hard to learn
A lot of data types High level data types,
– Pointers– Alias
Easy language– Simple & fast
compiler– Efficient memory
usage and faster– Easy to learn for
beginner A few data types Hardware related
– Wires– Registers
VHDL vs. VerilogVHDL vs. Verilog
User defined types Strong type checking
– (ie it checks the typing more rigorously)
User defined Library & package
Open Language
All primitive types Some castings are
allowed
No user defined packages
Cadence’s language at first
Verilog modeled after C, VHDL is modeled after Ada
Verilog is case sensitive while VHDL is not
VHDL is more flexible
Verilog used extensively in the US while VHDL is used internationally
Data TypesData Types bit values: '0', '1' boolean values: TRUE, FALSE integer values: -(231) to +(231 - 1)
std_logic values: 'U','X','1','0','Z','W','H','L','-' U' = uninitialized'X' = unknown'W' = weak 'X‘'Z' = floating'H'/'L' = weak '1'/'0‘'-' = don't care
Std_logic_vector (n downto 0); Std_logic_vector (0 upto n);
Additional standardized packages
provide definitions
of data types and expressions of
timing data
– IEEE 1164 (data types)
– IEEE 1076.3 (numeric)
– IEEE 1076.4 (timing)
Hardware description languages describe a system– Systems can be described from many different points of view• Behavior: what does it do?• Structure: what is it composed of?• Functional properties: how do I interface to it?• Physical properties: how fast is it?
Usage (Using an HDL)
Descriptions can used for– Simulation• Verification, performance evaluation– Synthesis• First step in hardware design
SynthesisSynthesis
Synthesis:
Conversion of behavioral level description to
structural level netlist
Structural level netlist
– Implementation of behavioral description
– Describes interconnection of gates
Synthesis tool we shall use:
Leonardo Spectrum/ISE inbuilt synthesizer
SimulationSimulation Simulation is modeling the output
response of a circuit to given input stimuli
For our example circuit:– Given the values of A, B and S– Determine the values of X and
Y
Many types of simulators used– Event driven simulator is used
popularly– Simulation tool we shall use:
ModelSim/inbuilt simulator ISE
my_ckt
A
B
S
X
Y
Module/UnitModule/Unit
Logic module
A
B
C
Out put
In puts
FullAdder
Defining Modules in VHDLDefining Modules in VHDL
1.Define block by giving name
2.Specify i/p ,o/p lines (ports).
VHDL language elementsVHDL language elements
VHDL is composed of language VHDL is composed of language building building blocks blocks that consist of more than that consist of more than 75 75 reserved reserved words words and about 200 and about 200 descriptive wordsdescriptive words or or
wordword combinationscombinations
Reserved VHDL keywordsReserved VHDL keywordsVARIABLE
WAITWHENWHILEWITH
XNORXOR
RETURN
SELECTSEVERITYSIGNALSHAREDSLASLLSRASRLSUBTYPE
THENTOTRANSPORTTYPE
UNAFFECTEDUNITSUNTILUSE
OFONOPENOROTHERSOUT
PACKAGEPORTPOSTPONEDPROCEDUREPROCESSPURE
RANGERECORDREGISTERREMREPORTROLROR
ININERTIALINOUTIS
LABELLIBRARYLINKAGELITERALLOOP
MAPMOD NANDNEWNEXTNORNOTNULL
DISCONNECTDOWNTO
ELSEELSIFENDENTITYEXIT
FILEFORFUNCTION
GENERATEGENERICGROUPGUARDED
IFIMPURE
ABSACCESSAFTERALIASALLANDARCHITECTUREARRAYASSERTATTRIBUTE
BEGINBLOCKBODYBUFFERBUS
CASECOMPONENTCONFIGURATION CONSTANT
Levels of AbstractionLevels of AbstractionDigital system can be represented at different
levels of abstraction
– Behavioral—relationship between input and output signals, usually boolean expressions
– Structural—description of the collection of gates and connections, more like a schematic
– Physical (Layout)
VHDL Programming
Dataflow
Behavioral
Structural
Mixed Structural and Behavioral
VHDL structureVHDL structure
Library– Definitions, constants
Entity– Interface
Architecture– Implementation, function
LibrariesLibraries
Library ieee;
Use ieee.std_logic_1164.all;Use ieee.std_logic_arith.all;Use ieee.std_logic_signed.all;Use ieee.std_logic_unsigned.all;
EntityEntity
Define inputs and outputs Example:
Entity test is
Port( A,B,C,D: in std_logic;
E: out std_logic);
End test;
Inputs and Outputs
Chip
A
B
C
D
E
EntityEntity
Describes the interface of a module
entity Reg4 isport ( d0, d1, d2, d3, en, clk : in
std_logic;q0, q1, q2, q3 : out std_logic);
end Reg4;
entity name port names port mode (direction)
port type
Basic Identifiers– Can Only Use
alphabetic letters ( A-Z, a-z ), orDecimal digits ( 0-9 ), orUnderline character ( _ )
– Must Start With Alphabetic Letter – May NOT end with underline ( MyVal_ )– May NOT contain sequential underlines (My__Val)
Not case sensitive, but recommended to use always the same way.
It is also recommended to use capitals for language components– Examples– B3,b3,ram1,ram_1,ram_1_c, MyVal.The followings are not used_Basic_gateRam_2_Ram__2
The mode of the portThe mode of the port<mode> = in, out, inout, buffer, linkage
in: Component only read the signal
out: Component only write to the signal
inout: Component read or write to the signal (bidirectional signals)
buffer: Component write and read back the signal (no bidirectional signals, the signal is going out from the component)
linkage: Used only in the documentation
Concurrent operation Concurrent operation
Q=a+ b .c
<=a or (b and c)
=/ a or b and c=(a+ b) .cH= a + b . c’ + d
(not (a or (b and not c) or d))g<=(x or y) and (z or not (w and v))
ArchitectureArchitecture
Define functionality of the chip
X <= A AND B;Y <= C AND D;E <= X OR Y;
ChipA
B
C
D
E
X
Y
Dataflow ModelDataflow ModelThe flow of data through the entity is
modeled primarily using concurrent signal assignment statements. (uses statements that defines the actual flow of data.....)
The structure of the entity is not explicitly specified but it can be implicitly deduced.
Architecture MYARCH of MYENT is begin SUM <= A xor B after 8ns end MYARCH;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity half_adder is Port ( a : in STD_LOGIC; b : in STD_LOGIC; carry : out STD_LOGIC; sum : out STD_LOGIC);end half_adder;
architecture Behavioral of half_adder is
beginsum<= a xor b;carry<= a and b;
end Behavioral;
XOR
&
a
bsum
carry
Logical operators defined in Logical operators defined in VHDL VHDL
NOTANDNANDORNORXORXNOR
Delay in Signal AssignmentDelay in Signal Assignment
There are two types of delay that can be applied when assigning a time/value pair into the driver of a signal– Inertial Delay– Transport Delay
Inertial DelayInertial DelayInertial delay models the delays often found
in switching circuits. An input value must remain stable for a specified time (pulse rejection limit) before the value is allowed to propagate to the output.
This is the delay due to the fact that electronic gates require a short amount of time to respond to the movement of energy within the circuit.
The value appears at the output after the specified inertial-delay.
Transport DelayTransport Delay This delay models pure propagation delay; ie, any
change in the input (no matter how small) is transported to the output after the specified delay time period
To use a transport delay model, the keyword transport transport must be used in a signal assignment statement
Ideal delay modeling can be obtained by using this delay model, where spikes would be propagated through instead of being ignored
Output<=transport (x) after 10ps;
Example: 1-bit Full Adder Example: 1-bit Full Adder (with delay)(with delay)
entity FullAdder is
port (X, Y, Cin: in bit; -- Inputs
Cout, Sum: out bit); -- Outputs
end FullAdder;
X
YCin
Sum
CoutFull Adder
Example: 1-bit Full Adder Example: 1-bit Full Adder (contd.)(contd.)
Architecture Equations of FullAdder is
begin -- Concurrent Assignment
Sum <= X xor Y xor Cin after 10 ns;
Cout <= (X and Y) or (X and Cin) or (Y and Cin) after 15 ns;
end Equations;
Example of Communicating Processes - the full adder.
In1
In2
s1
c_in
sum
c_out
HA HA
ORs2
s3
This example shows a model of a full adder constructed from2 half-adders and a 2 input OR gate.
The behavior of the 3 components is described using processesthat communicate through signals.
When there is an event on either of the input signals, process HA1executes (see code in next slide), which creates events on internalsignals s1 and s2.
library IEEE;use IEEE.std_logic_1164.all;entity full_adder isport(in1, in2, c_in: in std_ulogic; sum, c_out: out std_ulogic);end full_adder;
architecture dataflow of full_adder issignal s1, s2, s3 : std_ulogic;constant gate_delay: Time:=5 ns;beginL1: s1<=(in1 xor in2) after gate_delay;L2: s2<=(c_in and s1) after gate_delay;L3: s3<=(in1 and in2) after gate_delay;L4: sum<=(s1 xor c_in) after gate_delay;L5: c_out<=(s2 or s3) after gate_delay;end dataflow;
Architecture Body
ArchitectureDeclarative Statement
Structural ModelStructural Model Digital circuits consist of components and
interconnection between them A component can in turn be composed of sub-
components and their interconnections A component interacts with other components
through pins Component is modeled as entity Component pins are modeled as ports Interconnections between components are
modeled as signals
VHDL Structural ElementsVHDL Structural Elements
Entity: InterfaceArchitecture: Implementation, behavior,
functionProcess: Concurrency, event controlledConfiguration: Model chaining, structure,
hierarchyPackage: Modular design, standard
solution, data types, constantsLibrary: Compilation, object code
--Structural Descriptionentity AOI_Network is
port(A,B.C,D:in std_logic;
E:out std_logic);
end AOI_Network
architecture structural of AOI_Network is
component AND2
port(x,y:in std_logic;
z:out std_logic);
end component;
ChipA
B
C
D
EX
Y
component or2
port(x,y:in std_logic;
z:out std_logic);
end component;
signal X,Y:std_logic;
Begin
G1:AND2 port map (A,B,X);
G2:AND2 port map (C,D,Y);
G3:OR2 port map (X,Y,E);
End structural;
Before this the module should be previously defined
use library….
entity AND2 is
port (u,v:in std_logic;
q:out std_logic);
end AND2;
architecture of AND2 is
begin
q<=u and v;
end AND2;
Similarly for OR2, module should be defined.
Example: 4-bit AdderExample: 4-bit Adder
entity Adder4 is
port (A, B: in bit_vector(3 downto 0);
Ci: in bit; -- Inputs
S: out bit_vector(3 downto 0);
Co: out bit); -- Outputs
end Adder4;
Example: 4-bit Adder (contd.)Example: 4-bit Adder (contd.)
Architecture Structure of Adder4 is
Component FullAdder
port (X, Y, Cin: in bit; Cout, Sum: out bit);
signal C: bit_vector (3 downto 1);
begin -- Instantiations
FA0: FullAdder port map (A(0), B(0), Ci, C(1), S(0));
FA1: FullAdder port map (A(1), B(1), C(1), C(2), S(1));
FA2: FullAdder port map (A(2), B(2), C(2), C(3), S(2));
FA3: FullAdder port map (A(3), B(3), C(3), Co, S(3));
end Structure;
The concept of component can be understood using the concept of a design library, which is a collection of different modules, each defined by entity and architecture statement.
Once cells are used in library we can use copies by component command
This is called instancing the cell, and component itself is called an instance of the original.
Modeling the Behavior wayModeling the Behavior way Architecture body
– describes an implementation of an entity– may be several per entity
Behavioral architecture– describes the algorithm performed by the module– contains
process statements, each containing– sequential statements, including
• signal assignment statements and• wait statements
Full Adder – using ProcessesFull Adder – using Processes
library ieee;use ieee.std_logic_1164.all;entity FULL_ADDER is
port (A, B, Cin : in std_logic;Sum, Cout : out std_logic);
end FULL_ADDER;
architecture BEHAV_FA of FULL_ADDER issignal int1, int2, int3: std_logic;begin
-- Process P1 that defines the first half adderP1: process (A, B)
beginint1<= A xor
B;int2<= A and
B;end process;
-- Process P2 that defines the second half adder and the OR -- gateP2: process (int1, int2, Cin)
beginSum <= int1 xor Cin;
int3 <= int1 and Cin;
Cout <= int2 or int3;
end process;end BEHAV_FA;
MultiplexersMultiplexers
A B
4-to-1MUX
I0
I1
I2
I3
Z
ABI3
AB’I2
A’BI1
A’B’I0
Z
Data inputs versus control
inputs
Use of muxes in
control and data path
A B Z 0 0 I0 0 1 I1 1 0 I2 1 1 I3
+
Concurrent Conditional Concurrent Conditional Assignment: 4 to 1 MultiplexerAssignment: 4 to 1 Multiplexer
y <= x0 when sel = 0
else x1 when sel = 1
else x2 when sel = 2
else x3 when sel = 3
x0x1x2x3
sel
y
CASE Statement: CASE Statement: 4 to 1 Multiplexer4 to 1 Multiplexer
Case sel is
when 0 => y <= x0
when 1 => y <= x1
when 2 => y <= x2
when 3 => y <= x3
end case
x0x1x2x3
y
2-to-4-decoder with enable,2-to-4-decoder with enable,DeMUXDeMUX
Example: DFF (contd.)Example: DFF (contd.)Architecture Beh of DFF is
begin process (CLK)
begin if (CLK = ‘1’ then
Q <= D after 10 ns;
QN <= not D after 10 ns;
endif;
endprocess;
end Beh;
Internal Structure of a Internal Structure of a PLAPLA
Inputs
A
A’
B
B’
C
C’
AND ARRAY
OR ARRAY
F0 F1 F2 F3
Outputs
A’B’
AC’
B
BC’
AC
THANK YOU ALL
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