Solving the ESD challenges for Internet of Things

BART KEPPENS

SEPTEMBER 2015

On-chip ESD solutions for

Internet of Things

Intellectual Property

SOFICS © 2015 Proprietary & Confidential 2

As is the case with many published ESD design solutions, the techniques and protection solutions described in this presentation are protected by patents

and patents pending and cannot be copied freely.

Contact Sofics to discuss about a license for the Sofics technology.

[email protected]

PowerQubic, TakeCharge, and Sofics are trademarks of Sofics BVBA.

mailto:[email protected]


Outline

• Introduction

– Internet of Things (IoT)

• Challenges, solutions for ESD/EOS protection

• Conclusion

Internet of Things


• By 2020 Cisco expects 50 billion connected devices

– More than 6 devices per person

IoT: According to Synapse


• To achieve 50 Billion devices in 5 year

– Must be cheap

Below $5

– Must be able to run multiple years on 1 or 2 coin batteries

100uA limit

Always ON block to wake up rest of the functions: max. 10uA standby current

– Reasonable high MIPS CPU in active mode

300 MHz

– Must be small form factor

Can be inserted everywhere: keys, shoes, ...

– Must have worldwide connectivity options

Synapse selected LTE

IoT: according to SMIC


• IoT Process, IP platform, subsystems

– Adequate performance

200MHz CPU

– Ultra low power

<1uW

– Wireless connectivity

Bluetooth, Zigbee, NFC, GPS, LTE,

– Embedded NVM

Up to 2MB memory

– Sensor integration

SiP

– Security

• Select right technology node by market size and computing complexity


Outline

• Introduction



– Ultra Low power


– Reliability

• Conclusion

Intro: Explosive growth of wireless interfaces

• Wireless interfaces: very diverse and growing

– Broad set of standards and versions

– Increasing bandwidth


Intro: ESD protection influences RF performance

• Example: RF ESD protection

– Lower gain (S21)

– Higher noise figure (NF)

– Degraded input reflection coefficient (S11)

• Unique ESD solutions required

– Low parasitic capacitance

– Low pad resistance

– High Q factor

– Low leakage


[12]

Approach 1: Plug-n-play

• Minimize parasitic capacitance of ESD devices

– Parasitic capacitance chosen not to degrade RF performance

– Most used approach:

dual diode and efficient power clamp

– Alternative:

Local protection clamps

Select optimal protection device [15-21]


0

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ggnMOS

LVTSCR

Cj(0

) [p

F]

It2 [A]

20m

50m

75m

100m

150m

200m

Approach 2: LC cancellation

• ESD protection using filters and cancellation

– LC resonator isolates the ESD protection device from the RF input

– Resonator is tuned to the operation frequency of the RF circuit

– Does not require high-Q ESD protection device

• References [10, 13, 22]


Approach 3: ESD – RF co-design

• Full (or partial) circuit ESD co-design

– ESD protection is integrated in RF design

– More designer freedom

– Designer has to know both RF and ESD!

• References [23, 24]


90nm product: 8.5 GHz LNA

• Application: RF - tagging

– 8.5GHz wireless interface

– Location aware

– 10 year lifetime from 1 coin battery

– 802.15.4a standard: Alternate PHY for Zigbee devices

• Protection concept

– Design window failure voltage: 11.4V

– Dual diode approach not possible

Only narrow Vdd connection available

– Local clamp

SCR triggered by dynamically biased MOS


90nm product: Capacitive loading

• Parasitic capacitance: calculation based on foundry data

– Maximum 100fF allowed


90nm product: Results

• ESD protection for LNA IO

– ESD: >2kV HBM

– Latch-up immune

– Low capacitive: <100fF

– Low leakage: <0.1nA

– Small area: <3000um2

– CUP: ESD under bond pad


Example NFC


• Simplify everyday tasks

– Payment

– Transportation

– Networking

– Promotions/coupons

NFC – Near Field Communication


• Simplified circuit

NFC – Near Field Communication


• Protection required for antenna pads

– ESD protection

During production and assembly

– EOS protection

Amplitude of coil voltage depends on proximity

Differential voltage on antenna pads can run high


• Simulation of voltage difference between antenna pads

9V

High voltage on antenna pads


• Solution 1:

– Use high voltage transistors for RF front-end

• Solution 2:

– Limit the voltage

– Typical solution: diode based limiting circuit

– Sofics solution: clipping circuit

Voltage at antenna pads needs to be ’clipped’


• Basic clipping circuit // Over voltage protection // limiting circuits

Diode based limiting circuits


• Disadvantages for the diode-based solutions

– Large diodes required determined by the maximum current

– Large leakage current during normal non-clipped operation

– Large Silicon footprint

– Fixed clipping level determined by number of diodes

– Multiple diodes: creation of many parasitic bipolars: Darlington, latch-up...

Sofics clipping circuit


• Silicon/product proof TSMC 55nm

– Area: 5488 µm² (63.52µm x 86.40µm)

– Max. current: 100 mA

– Different options

Clips @ 3.6V (ENABLE_CLAMP is ON)

Clips @ 2.2V (ENABLE_2V2 is ON)

GPIO use (ENABLE_CLAMP is OFF)

– Leakage below 780nA in GPIO mode

– Temperature range: -40°C up to 100 °C

Sofics: Over voltage and ESD protection circuit


• Reduce maximum voltage

– Clip at 3.6V

– Option to clip at 2.2V

– Protect sensitive circuit

• Included

– Different clipping levels

– Enable/Disable circuit

55nm clipping circuit

Without clipping circuit

Sofics clipping circuit


Outline

• Introduction



– Ultra Low power


– Reliability

• Conclusion

Ultra low power


• Internet of Things devices need ultra low power

– Conserve battery power

– Rely on energy harvesting

• Foundries develop new platforms

– Reduced leakage

– Improved efficiency

– 55nm ULP

– 90nm ULP

– 40nm ULP

– 28nm FD SOI

Ultra low power


• But how can ESD protection help to achieve lower power?

– Standby power: Select low leakage concepts

– Dynamic power: Select ESD with low parasitic capacitance for interfaces

Examples: ESD protection with ultra low leakage

• Reduce ESD related leakage with Sofics ESD IP

– Example: 1.2V TSMC 40nm

ESD protection for RF LNA circuit

Leakage ~20pA at 1.2V at high temperature

– Example: 5V TSMC 180nm

ESD protection for overvoltage tolerant IO

Leakage ~10nA at 5V at high temperature

– Example: 65nm ESD cells

All kinds of voltage domains

All kinds of interface types

Leakage ~20nA at high temperature

28 SOFICS © 2015 Proprietary & Confidential


Outline

• Introduction



– Ultra Low power


– Reliability

• Conclusion

IC technology trends – VDD levels reducing

• Technology scaling

– Reduction of core supply voltage continues

1.5V at 130nm

1.0V at 32nm

0.85V at 28nm

– Pace defined by ITRS

• Foundries further reduce Vdd levels for IoT platforms

• What about sensor connections?


Ref: IEW 2010 – Christian Russ, Infineon

Sensor connections

• Sensor interfaces

– Need different voltage levels

E.g. Several mV to 20V or higher

Cannot be handled by General Purpose I/O interface circuits

Need analog expertise, level shifters, sensitive current/sense amplifiers

– Examples:

Small signals (order of a few mV or mA) captured by sensors

– Motion detection

– Touch detection

– …

Driving voltage for implanted chip to restore hearing in the order of 20V

Sarnoff Europe © 2008 Proprietary & Confidential

31

GPIO ESD concept not suitable for Analog I/O


• Typical GPIO ESD protection concept

– ESD robust output drivers

Large NMOS/PMOS transistors

Silicide blocked drains

Integrated diodes

– Poly resistance between ESD and circuit

• Issues

– Prevent high speed circuits

– Prevent accurate current/voltage sensing

– High leakage current

– Large silicon area

– High parasitic capacitance

Solution: Typical Analog I/O – diode based approach


• Traditional Analog I/O

– Simple concept

Diode from Vss to Pad

Diode from Pad to Vdd

– Needs efficient power clamp

– Good characteristics

Low leakage

Low parasitic capacitance

Small area

– BUT: room for improvement

Lowest capacitance???

Overvoltage tolerant???

Protection of sensitive nodes???

Solution: Local I/O clamp reduces total voltage drop


• Local I/O clamp

– Strongly reduce voltage drop during ESD

– Many different device options

– Place power clamp in the I/O !?

• Concerns?

– Leakage current at I/O?

– Parasitic capacitance at I/O?

– Silicon footprint?

– Latch-up immunity?

Vdd

Vss

IN +

Analog front end

Example: high voltage interfaces in 28nm CMOS


• Customer required different high voltage ranges in TSMC 28nm

0

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10-12

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3.9V 5.5V 6.05V no DNW

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10-12

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3.9V with DNW

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10-12

10-10

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Leakage current [A]

5.5V 6.05V with DNW

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10-12

10-10

10-8

10-6

10-4

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I [A]

V [V]

Leakage current [A]

13.2V with DNW

Other issues with supplies


• To reduce power consumption

– Small circuit stays awake all the time

– Other circuits (sensing, control, communication) are switched off

Special consideration for ESD conditions between the powerlines


Outline

• Introduction



– Ultra Low power


– Reliability

• Conclusion

Reliability required?


• Do innovative IoT devices need lower or higher ESD performance?

– Harsh environments

Industrial IoT

Automotive IoT

Wearables, semiconductor integrated into clothes

Implanted electronics

– New materials, approaches

– What about latch-up?

Battery powered devices – not possible to replace the battery

Implanted devices

The automotive market


• Trend: more electronics in harsh EMI/EOS automotive environments

– Electrification of systems

– New regulations

– New applications

• Trend: more semiconductors in light cars

– $300 [2013]

– $400 [2017]

• TAM:

– $30B i.e. 10% semi market

• Reliability challenges:

– Zero defect requirements

– Very long system lifetime

Automotive electronics: not an “easy ride”


• Operation conditions different than consumer and industrial

• System (reliability) requirements are equally more stringent

– DC: 12V, 24V, 40V…

– Transient currents: several Amperes

Consumer Industrial Automotive

Temperature 0 to 40⁰C -10 to 70⁰C -40 to 160⁰C

Operation time 2 to 5 years 5 to 10 years up to 15 years

Humidity low environment 0% to 100%

Field failure rate <10% <<1% 0 failure

Supply ~ 1 year ~ 2 to 5 years up to 30 years



• Zero defect requirements

– Severe reliability tests and qualification

– Cost of errors over product(ion) life time

Early-built-in reliability

• Trend:

– OEM push reliability specifications on the IC

Adds complexity and cost to the IC

Source: Freescale, David Lopez

Source: Audi, Christian Lippert



• Severe reliability requirements passed on component and system level

– Above standard HBM, MM requirements

– Transient latch-up immune

-27V..+40V

– ESD under powered conditions

0V..+18V

– IEC 61000-4-2 system ESD

– ISO 7637-2 load dump pulse

– EMC IEC 62132 DPI

• Requirements strongly depend on application

– Automotive, industrial applications: IEC 61000-4-2, ISO 7637, IEC 62132 …

– Battery, power management: IEC 61000-4-2

Source: STMicroelectronics, Philippe Merceron


Outline

• Introduction


• Conclusion

Conclusion


• Many challenges for ESD protection in IoT devices

– Wireless connectivity requires low parasitic capacitance ESD

– Wireless interfaces like NFC require voltage limiting circuits

– Low power devices need low leakage ESD

– Sensor integration and embedded memory needs multi voltage support

• Sofics on-chip ESD protection solutions

– Verified on 10 foundries, broad set of applications

– Leakage in order of nA versus uA

– Parasitic capacitance: 200fF versus 1pF

– Flexible trigger condition: support for multiple voltage options

Typical key aspects mentioned for IoT


• Adequate performance

– Efficient DSP/MCU/CPU cores

• Wireless connectivity

– All kind of radio’s: Bluetooth, Zigbee, NFC, Wifi, LTE

• Ultra Low Power

– Battery powered / energy harvesting / Latch-up immune

• Sensor integration

– Beyond any imagination...

• Embedded non volatile memory

– Code, data and security key storage

• Security

– Privacy protection, not possible to hack

• Reliability

• Cost

References


Contact us for more information?


Sofics website

IoT cases

Solving the ESD challenges for Internet of Things

Engineering