SOI Detector (1) Mateusz Baszczyk, Piotr Dorosz, Sebastian Głąb, Wojciech Kucewicz, Łukasz Mik, Maria Sapor (2) Imran Ahmed, Tomasz Fiutowski, Marek Idzik, Jakub Moroń (3) Piotr Kapusta (1) Department of Electronics, (2) Department of Particle Interaction and Detection Techniques AGH – University of Science and Technology, Al. Mickiewicza 30, 30-059 Krakow, Poland (3) Institute of Nuclear Physics Polish Academy of Science
SOI Detector. (1) Mateusz Baszczyk, Piotr Dorosz, Sebastian Głąb , Wojciech Kucewicz, Łukasz Mik, Maria Sapor (2) Imran Ahmed, Tomasz Fiutowski, Marek Idzik, Jakub Moroń (3) Piotr Kapusta. (1) Department of Electronics, (2) Department of Particle Interaction and Detection Techniques - PowerPoint PPT Presentation
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SOI Detector
(1) Mateusz Baszczyk, Piotr Dorosz, Sebastian Głąb,Wojciech Kucewicz, Łukasz Mik, Maria Sapor
(2) Imran Ahmed, Tomasz Fiutowski, Marek Idzik, Jakub Moroń
(3) Piotr Kapusta
(1) Department of Electronics,(2) Department of Particle Interaction and Detection TechniquesAGH – University of Science and Technology,Al. Mickiewicza 30, 30-059 Krakow, Poland(3) Institute of Nuclear Physics Polish Academy of ScienceRadzikowskiego 152, 31-342 Krakow, Poland
Agenda
• Chip topology• Pixel circuit;• Band Gap voltage source;• Analogue to digital converter;• Digital library;• Summary;• Future work.
2
Assumptions
• Detector has to work but it’s parameters are not so important.
• Pixels with CDS and rolling shutter readout scheme.
• Possibility to measure wafer temperature.
• Functional 10 bit ADC with parallel data output (LVDS).
• We will take part in July submission.
3
Chip layout
4
• Detector has 32 pix x 32 pix;• Two slightly different layouts of
pixel;• Two Band Gaps;• Two 10 bit SAR ADCs;• Differential voltage signal.
Chip
5
Pixel
6
Designed by Piotr Kapusta
Pixel layout (30 um x 30 um)
7Designed by Piotr Kapusta
Negative temperature coefficient
8
Forward voltage of p-n junction VBE has negative TC.
T
qEVmV
T
V gTBEBE/4
2
3m
eVEg 12.1
q
kTVT
With VBE = 750 mV, T = 300 K:
K
mV
T
VBE 5.1
Temperature exponent of mobility:
Thermal voltage:
Bandgap energy of silicon:
Positive temperature coefficient
9
It was recognized in 1964 that if two bipolar transistors operate at unequal current densities, then the difference between their base-emitter voltages is directly proportional to the absolute temperature.
18M. Dessouky, A. Kaiser, Input switch configuration suitable for rail-to-rail operation of switched opamp circuits;Elect. Lett., vol. 35, no. 1, pp. 8-10, Jan. 1999.
Sampling circuit with bootstrap
19M. Dessouky, A. Kaiser, Input switch configuration suitable for rail-to-rail operation of switched opamp circuits;Elect. Lett., vol. 35, no. 1, pp. 8-10, Jan. 1999.
Sampling circuit with bootstrap
20
Designed by Marek Idzik and Tomasz Fiutowski
9 bit DAC (segmented)
21
Designed by Marek Idzik and Tomasz Fiutowski
Dynamic comparator
22
Designed by Marek Idzik and Tomasz Fiutowski
Dynamic comparator
23
Designed by Marek Idzik and Tomasz Fiutowski
Delay based on thyristor
24
Designed by Marek Idzik and Tomasz Fiutowski
Delay based on thyristor
25
Designed by Marek Idzik and Tomasz Fiutowski
Digital library
26
94 Cells (81 completed, 13 missing layout).
Adders, AND, AndOrInvert, Buffer, Buffer with Enable, Tristate Buffer, D Flip-Flops,D Latches, INV, JK Flip-Flops, Multiplexers, NAND, NOR, OR, T Flip-Flops, XNOR, XOR.
DigitalLib
• Two libraries: Gates and DigitalLib.Gates contains parameterized symbols and is used to draw schematics of DigitalLib.
• HDF_DYNAMIC and DF_DYNAMIC were drawn by Tomasz Fiutowski. These cells have different layout constraints.MESH is a template for layout drawing.
• These cells do not have layout: D Flip-Flops with Enable,all JK Flip-Flops, most of T Flip-Flops.
• All cells have passed simulation, DRC and LVS test. But I do not give any guarantee for correct operation of digital circuit – you must test it by yourself!!!
27
Conclusions
• We have designed first SOI detector in Lapis technology. It is starting point for further improvements;
• Simulation results have shown correct operation of ADC and Band gap voltage source;
• Digital library containing low height cells was made;(not tested yet)
28
Future work
• IC will be measured immediately after shipment.It is possible to use SeaBoard as acquisition system.
• We plan to use column ADC to increase readout speed. Due to large amount of digital data we will design serializer and phased locked loop.