Software Notes SHW · 2020. 11. 17. · PANEL1_VDDEN TB20 External Bottom 1V8 Panel Power Enable 1 for eDP/MDSI Table 1. Display Interfaces 3.2.2 CSI Interface Signal name Pin Connecto

gigaSOM gS01 HW Manual March 2020

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©2020 EXOR Embedded S.r.l. - Subject to change without notice

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gigaSOM gS01

History

Rev Date Description By

0.1 29/Mar/2019 Created (Draft) T. Smrtić 0.2 30/July/2019 GPIO for use with reconfiguration K. Zoric

0.3 03/Sep/2019 Removed “preliminary”, minor changes DJ

0.4 01/Jan/2020 Revision 0.3 T. Smrtić

0.5 23/Mar/2020 Updated pictures T. Smrtić

Reference

Cross Reference Filename Description

[1]

Document contains

Author(s)

Functional Specs

Usability Specs

Techical Specs

Test Procedures

Technical Documentation

ѵ User Documentation

The reproduction, transmission or use of this document or its contents is not permitted without express written authority. Offenders will be liable for damages. All rights, including rights created by patent grant or registration of a utility model or design, are reserved. Technical data subject to change. Copyright © 2020 EXOR International S.p.A. - All Rights Reserved.

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TABLE OF CONTENTS

1 Introduction ................................................................................................................................. 6

2 Specifications ............................................................................................................................. 7

2.1 Features .............................................................................................................................. 7 2.2 Temperature range ........................................................................................................... 8 2.3 Power Supply ..................................................................................................................... 8 2.4 Mechanical Dimensions .................................................................................................. 9 2.5 Block Diagram ................................................................................................................ 11

3 gigaSOM Edge Pads ............................................................................................................... 12

3.1 Pin Layout ........................................................................................................................ 12 3.2 Pin Description ............................................................................................................... 13

3.2.1 Display Interfaces ............................................................................................. 13 3.2.2 CSI Interface ...................................................................................................... 14 3.2.3 SD Card, SDIO Interface................................................................................... 15 3.2.4 SMBus Interface ............................................................................................... 16 3.2.5 USB Interfaces .................................................................................................. 16 3.2.6 PCIe Interfaces .................................................................................................. 17 3.2.7 SATA Interfaces ................................................................................................ 18 3.2.8 Audio Interfaces ................................................................................................ 19 3.2.9 Gigabit Ethernet ................................................................................................ 19 3.2.10 LPC Bus .............................................................................................................. 20 3.2.11 PWM Signals ..................................................................................................... 20 3.2.12 SPI Interfaces .................................................................................................... 21 3.2.13 UART Interfaces ................................................................................................ 21 3.2.14 I2C Interfaces .................................................................................................... 22 3.2.15 SoC GPIO Signals ............................................................................................. 22 3.2.16 FPGA Transceiver Interfaces.......................................................................... 23 3.2.17 FPGA LVDS Interface ....................................................................................... 24 3.2.18 FPGA GPIO Signals........................................................................................... 27 3.2.19 FPGA JTAG Interface ....................................................................................... 29 3.2.20 Power Signals .................................................................................................... 29

4 SoC Ambient ............................................................................................................................ 31

4.1 Display Interfaces .......................................................................................................... 31 4.2 CSI Interface ................................................................................................................... 31 4.3 SD Card, SDIO Interface ................................................................................................ 31 4.4 USB Interfaces ................................................................................................................ 31 4.5 PCIe Interfaces ............................................................................................................... 32 4.6 SATA Interfaces ............................................................................................................. 32 4.7 Audio Interfaces ............................................................................................................. 32 4.8 Gigabit Ethernet .............................................................................................................. 33 4.9 I2C Interfaces ................................................................................................................. 33 4.10 SPI Interfaces ................................................................................................................ 33 4.11 UART Interfaces ........................................................................................................... 34 4.12 Soc GPIO Signals ......................................................................................................... 34 4.13 LPC Bus .......................................................................................................................... 35 4.14 Onboard Interfaces ...................................................................................................... 35

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5 FPGA Ambient ......................................................................................................................... 36

5.1 Transceiver Interfaces .................................................................................................. 36 5.2 LVDS ................................................................................................................................. 36 5.3 FPGA GPIO Signals ........................................................................................................ 36 5.4 Memory ............................................................................................................................ 36 5.5 LEDs.................................................................................................................................. 37 5.6 JTAG ................................................................................................................................. 37 5.7 FPGA reconfiguration from CPU ................................................................................. 37

6 Additional Features ................................................................................................................. 38

6.1 Power Control ................................................................................................................. 38 6.2 Temperature Sensor ...................................................................................................... 38 6.3 Booting ............................................................................................................................. 39 6.4 Flexible I/O Adapter ....................................................................................................... 39

7 Soldering profile ...................................................................................................................... 40

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List of Figures Figure 1. gigaSOM .................................................................................................................................................. 6 Figure 2. Physical Dimensions............................................................................................................................. 9 Figure 3. Recommended PCB Land Patter ..................................................................................................... 10 Figure 4. Block Diagram ...................................................................................................................................... 11 Figure 5. Pin Layout ............................................................................................................................................. 12 Figure 6. PCIe Diagram ....................................................................................................................................... 32 Figure 7. SPI Diagram .......................................................................................................................................... 33 Figure 8. Fast SPI Diagram ................................................................................................................................. 34 Figure 9. High-speed I/O Lane Multiplexing .................................................................................................... 39 Figure 10. Soldering Thermal Profile ................................................................................................................ 40 List of Tables Table 1. Display Interfaces ................................................................................................................................. 14 Table 2. CSI Interface .......................................................................................................................................... 15 Table 3. SD Card, SDIO Interface ....................................................................................................................... 16 Table 4. SMBus Interface ................................................................................................................................... 16 Table 5. USB Interfaces....................................................................................................................................... 17 Table 6. PCIe Interfaces ...................................................................................................................................... 18 Table 7. SATA Interfaces .................................................................................................................................... 18 Table 8. AUDIO Interfaces .................................................................................................................................. 19 Table 9. Gigabit Ethernet .................................................................................................................................... 20 Table 10. LPC Bus ................................................................................................................................................ 20 Table 11. PWM Signals ....................................................................................................................................... 20 Table 12. SPI Interfaces ...................................................................................................................................... 21 Table 13. UART Interfaces.................................................................................................................................. 22 Table 14. I2C Interfaces ...................................................................................................................................... 22 Table 15. SoC GPIO Signals ............................................................................................................................... 23 Table 16. Transceiver Interfaces ....................................................................................................................... 24 Table 17. LVDS Interface .................................................................................................................................... 27 Table 18. FPGA Bank 2L GPIO Signals ............................................................................................................. 27 Table 19. FPGA Bank 2J GPIO Signals ............................................................................................................. 28 Table 20. FPGA Bank 2A GPIO Signals ............................................................................................................ 28 Table 21. FPGA JTAG Intreface......................................................................................................................... 29 Table 22. Power Signals ..................................................................................................................................... 29 Table 23. Power Management Signals ............................................................................................................ 30 Table 24. Ground Signal ...................................................................................................................................... 30 Table 25. Mux Selector Description .................................................................................................................. 36 Table 26. LED Description .................................................................................................................................. 37 Table 27. Power Control Description ................................................................................................................ 38 Table 28. Booting Header Description ............................................................................................................. 39

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1 Introduction

Figure 1. gigaSOM

This gigaSOM belongs to Exor’s gigaSOM System on Module family. The gigaSOM is very compact, smart, flexible and fully customizable solutions to be adapted for a vast array of IIoT products with simple carrier board design. The gigaSOM features the Intel Atom Apollo Lake SoCs and Intel Cyclone 10 GX FPGA.

This HW manual describes the gigaSOM. This document provides information about the features and capabilities available on the gigaSOM.

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2 Specifications

This chapter will show technical and mechanical details of gigaSOM.

2.1 Features

Intel Atom® Processor E3940

• 1.6 GHz, Quad Core

• Burst Freq. 1.8 GHz

• 2 MB L2 Cache

• Intel® HD Graphics 500

• Onboard Memory (LPDDR4)

o Data rates up to 2400 MTps

o Up to 8 GB capacity

• High Definition Audio interface with support for multiple codecs

• Gigabit Ethernet via Intel® i210 controller

• Trusted Platform Module

• Display Interfaces

o 2 x DP/HDMI

o 1x eDP

• MIPI/CSI Interface

• Communication interfaces

o USB Interface

- 2x USB 3.0

- 4x USB 2.0

o 4x PCIe

o 2x SATA

o 3x UART

o 1x SDIO

o 1x SD

o eMMC 512Gb (64G x 8)

o Buses

- 5x I2C, 1x SMB

- 2x I2S

- 3x SPI

- 1x Fast SPI

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Intel Cyclone 10 GX FPGA

• U484 UBGA Package

o 19 mm x 19 mm, 0.8 mm pitch

o 220K Logic Elements (LEs)

o 6 transceivers capable of 12.5 Gbps data rates

o 188 GPIOs with 70 pairs of LVDS

• Memory

o 2x DDR3 8Gb @ 800 MHz

• Interfaces

o 6x Transceiver

o 36x LVDS

• 28x GPIO

• LEDs

o 1 Config Done LED o 2 user LEDs

• Temperature Sensor

2.2 Temperature range

Operating Temperature Range

• -40 °C to +85 °C.

2.3 Power Supply

Input Voltage

• 4.75V - 5.25V

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2.4 Mechanical Dimensions

Figure 2. Physical Dimensions

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Figure 3. Recommended PCB Land Patter

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2.5 Block Diagram

This section shows the block diagram of gigaSOM.

Figure 4. Block Diagram

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3 gigaSOM Edge Pads

This chapter describes the pinout of gigaSOM edge pads.

3.1 Pin Layout

Figure 5. Pin Layout

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3.2 Pin Description

3.2.1 Display Interfaces

Signal name Pin Connector I/O Voltage Description

DDI0_TXP0 TB43 External Bottom

1V05 Transmit Signal 0 for DP/HDMI

DDI0_TXN0 TB42 External Bottom

1V05 Transmit Complement Signal 0 for DP/HDMI













DDI0_AUXP_R TB46 External Bottom

1V05 Display Port Auxiliary Channel 0 for DP

DDI0_AUXN_R TB45 External Bottom

1V05 Display Port Auxiliary Channel Complement 0 for DP

DDI0_CLK TB49 External Bottom

1V8 I2C Clock 0 for HDMI

DDI0_DATA TB48 External Bottom

1V8 I2C Data 0 for HDMI

DDI0_HPD TB47 External Bottom

1V8 Hot Plug Detect 0 for DP/HDMI

















DDI1_AUXP_R TB23 External Bottom

1V05 Display Port Auxiliary Channel 1 for DP

DDI1_AUXN_R TB22 External Bottom

1V05 Display Port Auxiliary Channel Complement 1 for DP

DDI1_CLK TB17 External Bottom

1V8 I2C Clock 1 for HDMI

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DDI1_DATA TB18 External Bottom

1V8 I2C Data 1 for HDMI

DDI1_HPD TB21 External Bottom

1V8 Hot Plug Detect 1 for DP/HDMI

EDP_TXN0 TL30 External Left 1V05 Transmit Complement Signal for eDP

EDP_TXP0 TL31 External Left 1V05 Transmit Signal for eDP







EDP_AUXN TL27 External Left 1V05 Display Port Auxiliary Channel Complement for eDP

EDP_AUXP TL28 External Left 1V05 Display Port Auxiliary Channel for eDP

EDP_HDP TL26 External Left 1V8 Hot Plug Detect 1 for eDP

PANEL0_BKLTCTL TB52 External Bottom

1V8 Panel Backlight Brightness Control 0 for eDP/MDSI

PANEL0_BKLTEN TB51 External Bottom

1V8 Panel Backlight Enable 0 for eDP/MDSI

PANEL0_VDDEN TB50 External Bottom

1V8 Panel Power Enable 0 for eDP/MDSI

PANEL1_BKLTCTL TB16 External Bottom

1V8 Panel Backlight Brightness Control 1 for eDP/MDSI

PANEL1_BKLTEN TB19 External Bottom

1V8 Panel Backlight Enable 1 for eDP/MDSI

PANEL1_VDDEN TB20 External Bottom

1V8 Panel Power Enable 1 for eDP/MDSI

Table 1. Display Interfaces

3.2.2 CSI Interface

Signal name Pin Connecto

r I/O Voltage Description

MCSI_RX_DATA0_P BB31 Internal Bottom

1V24 CSI Positive Data Lane 0

MCSI_RX_DATA0_N BB30 Internal Bottom

1V24 CSI Negative Data Lane 0







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MCSI_RX_CLK0_P BB26 Internal Bottom

1V24 CSI Positive Clock Lane 0

MCSI_RX_CLK0_N BB25 Internal Bottom

1V24 CSI Negative Clock Lane 0

GP_CAMERASB6 BB23 Internal Bottom

1V8

Camera Sensor 0 Strobe to Soc to indicate beginning of capture/active high signal to still camera to power down the device

GP_CAMERASB4 BB22 Internal Bottom

1V8 Active high Xenon Flash trigger/Enables Torch Mode on LED Flash IC

CAM1_PWR (GP_CAMERASB11)

TT36 External Top

1V8 Active low output signal to reset digital video camera

CAM1_RST (GP_CAMERASB5)

TT37 External Top

1V8 Enable Red Eye Reduction LED for Xenon/ Triggers STROBE on LED Flash IC

CAM_MCK (OSC_CLK_OUT_2)

TT33 External Top

1V8 Oscillator Clocks Output

Table 2. CSI Interface

3.2.3 SD Card, SDIO Interface


SDCARD_CLK TL10 External Left 3V3 SD Card Clock

SDCARD_D0 TL2 External Left 3V3 SD Card Data bits 0




SDCARD_CMD TL7 External Left 3V3 SD Card Comand

SDCARD_CD TL8 External Left 1V8 SD Card Detect, Active low when a card is present

SDCARD_WP TL9 External Left 1V8 SD Card Port Write Protect

SDCARD_PWR_EN TL11 External Left 1V8 SD Card Power Enable, GPIO_183 on SoC

SDIO_CLK TT24 External Top 1V8 SDIO Clock

SDIO_D0 TT19 External Top 1V8 SDIO Data bits 0


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SDIO_CMD TT23 External Top 1V8 SDIO Comand

Table 3. SD Card, SDIO Interface

3.2.4 SMBus Interface


SMB_CLK_3P3 TT39 External Top 3V3 SMBus Clock

SMB_DATA_3P3 TT40 External Top 3V3 SMBus Data

SMB_ALERT TT41 External Top 3V3 SMBus Alert

Table 4. SMBus Interface

3.2.5 USB Interfaces


USB2_P0 BL27 External Left 3V3 USB Positive Data 0

USB2_N0 BL26 External Left 3V3 USB Negative Data 0











USB2_VBUS_SNS BL30 External Left 1V8 USB Vbus Sense line

USB2_OTG_ID BL29 External Left 1V8 USB Dual Role Support

USB_OC0 BL32 External Left 1V8 Used by the controller to disable I/O in case overcurrent

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USB_OC1 BL31 External Left 1V8 Used by the controller to disable I/O in case overcurrent

USB3_RX0N BB33 Internal Bottom

1V24 Diff Receiver serial data negative input 0

USB3_RX0P BB34 Internal Bottom

1V24 Diff Receiver serial data positive input 0

USB3_TX0N BB35 Internal Bottom

1V24 Diff Transmitter serial data negative output 0

USB3_TX0P BB36 Internal Bottom

1V24 Diff Transmitter serial data positive output 0

USB3_RX1N BB38 Internal Bottom


USB3_RX1P BB39 Internal Bottom


USB3_TX1N BB40 Internal Bottom


USB3_TX1P BB41 Internal Bottom


Table 5. USB Interfaces

3.2.6 PCIe Interfaces


PCIE_RXN2 TB58 External Bottom


PCIE_RXP2 TB59 External Bottom


PCIE_TXN2 TB60 External Bottom


PCIE_TXP2 TB61 External Bottom


PCIE_RXN3 TB66 External Bottom

1V24 Diff Receiver serial data negative input 3, Multiplexed PCIe/USB3 Port 4

PCIE_RXP3 TB67 External Bottom

1V24 Diff Receiver serial data positive input 3, Multiplexed PCIe/USB3 Port 4

PCIE_TXN3 TB68 External Bottom

1V24 Diff Transmitter serial data negative output 3, Multiplexed with USB3 Port 4

PCIE_TXP3 TB69 External Bottom

1V24 Diff Transmitter serial data positive output 3, Multiplexed with USB3 Port 4

PCIE_CLKOUT3N TB63 External Bottom

1V05 PCIe Output Negative Clock 3

PCIE_CLKOUT3P TB64 External Bottom

1V05 PCIe Output Positive Clock 3

PCIE_CLKREQ3# TB54 External Bottom

1V8 PCIe Clock Request 3

PCIE1_RESET TB55 External Bottom

1V8 PCIe Reset

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PCIE_WAKE2# TB56 External Bottom

1V8 PCIe Wake Signal 2

PCIE_RXN5 BB50 Internal Bottom

1V24 Diff Receiver serial data negative input 5, Multiplexed with USB3 Port 2

PCIE_RXP5 BB51 Internal Bottom

1V24 Diff Receiver serial data positive input 5, Multiplexed with USB3 Port 2

PCIE_TXN5 BB52 Internal Bottom

1V24 Diff Transmitter serial data negative output 5, Multiplexed with USB3 Port 2

PCIE_TXP5 BB53 Internal Bottom

1V24 Diff Transmitter serial data positive output 5, Multiplexed with USB3 Port 2

PCIE_CLKOUT2N BB47 Internal Bottom

1V05 PCIe Output Negative Clock 2

PCIE_CLKOUT2P BB48 Internal Bottom

1V05 PCIe Output Positive Clock 2

PCIE2_RESET BB43 Internal Bottom

1V8 PCIe Reset

PCIE_WAKE1# BB44 Internal Bottom

1V8 PCIe Wake Signal 1

PCIE_CLKREQ2# BB45 Internal Bottom

1V8 PCIe Clock Request 2

Table 6. PCIe Interfaces

3.2.7 SATA Interfaces


SATA_RXN0 TB11 External Bottom

1V24 Serial ATA Diff Receive Negative 0

SATA_RXP0 TB12 External Bottom

1V24 Serial ATA Diff Receive Positive 0

SATA_TXN0 TB13 External Bottom

1V24 Serial ATA Diff Transmit Negative 0

SATA_TXP0 TB14 External Bottom

1V24 Serial ATA Diff Transmit Positive 0, Multiplexed with USB3 Port 5

SATA_RXN1 TB6 External Bottom

1V24 Serial ATA Diff Receive Negative 1, Multiplexed with USB3 Port 5

SATA_RXP1 TB7 External Bottom

1V24 Serial ATA Diff Receive Positive 1, Multiplexed with USB3 Port 5

SATA_TXN1 TB8 External Bottom

1V24 Serial ATA Diff Transmit Negative 1, Multiplexed with USB3 Port 5

SATA_TXP1 TB9 External Bottom

1V24 Serial ATA Diff Transmit Positive 1, Multiplexed with USB3 Port 5

SATA_LED_N TT44 External Top 1V8 Serial ATA LED, when active LED is ON

Table 7. SATA Interfaces

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3.2.8 Audio Interfaces


AVS_I2S1_SDI TT65 External Top 1V8 Analog microphone I2S Data in – serial data input 1

AVS_I2S1_SYNC TT66 External Top 1V8 Word Select or SYNC input 1

AVS_I2S1_MCLK TT67 External Top 1V8 MCLK for Master Mode operation or GPIO

AVS_I2S1_SDO TT68 External Top 1V8 Audio Codec I2S Data Out – serial data out 1

AVS_I2S1_BCLK TT69 External Top 1V8 Analog microphone I2S Bit Clock 1

AVS_I2S2_SYNC TT60 External Top 1V8 Word Select or SYNC input 2

AVS_I2S2_SDO TT61 External Top 1V8 Audio Codec I2S Data Out – serial data out 2

AVS_I2S2_SDI TT62 External Top 1V8 Analog microphone I2S Data in – serial data input 2

AVS_I2S2_BCLK TT63 External Top 1V8 Analog microphone I2S Bit Clock 2

HDA_BCLK (ISH_GPIO_0)

TT30 External Top 1V8 HD Audio Bit Clock

HDA_WS_SYNC (ISH_GPIO_1)

TT27 External Top 1V8 HD Audio Word Select or SYNC

HDA_SDI (ISH_GPIO_2)

TT29 External Top 1V8 HD Audio Serial Data In

HDA_SDO (ISH_GPIO_3)

TT28 External Top 1V8 HD Audio Serial Data Out

HDA_RST_N (AVS_I2S2_MCLK)

TT31 External Top 1V8 HD Audio Reset

HDA_SPKR (ISH_GPIO_9)

TT26 External Top 1V8 HD Audio Speaker Out

Table 8. AUDIO Interfaces

3.2.9 Gigabit Ethernet

Signal name Pin Connector Description

LAN_MDI0P TL24 External Left Media Dependent Interface Positive 0

LAN_MDI0N TL23 External Left Media Dependent Interface Negative 0






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LAN_GTREF TL22 External Left GTREF Out 1V5

LAN_LED_ACT# TL19 External Left LINK/ACTIVITY Indication

LAN_LINK1G# TL16 External Left LINK1000# Indication

LAN_LINK100# TL15 External Left LINK100# Indication

Table 9. Gigabit Ethernet

3.2.10 LPC Bus


LPC_AD0 BL1 Internal Bottom

1V8 LPC Data 0


1V8 LPC Data 1


1V8 LPC Data 2


1V8 LPC Data 3

LPC_FRAME BL6 Internal Bottom

1V8 LFRAME# indicates the start of an LPC cycle, or an abort

LPC_SERIRQ BL7 Internal Bottom

1V8 Serial Interrupt Request

LPC_CLKRUN BL8 Internal Bottom

1V8 Control LPC Clock Signals

LPC_CLK0 BL9 Internal Bottom

1V8 25 Mhz output clock

Table 10. LPC Bus

3.2.11 PWM Signals


SOC_PWM0 TB4 External Bottom

1V8 PWM Signal 0


1V8 PWM Signal 1


1V8 PWM Signal 2


1V8 PWM Signa3

Table 11. PWM Signals

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3.2.12 SPI Interfaces


FST_SPI_CLK BB15 Internal Bottom

1V8 Fast SPI Clock

FST_SPI_CS1# BB14 Internal Bottom

1V8 Fast SPI Chip Select 1

FST_SPI_CS2# BB13 Internal Bottom

1V8 Fast SPI Chip Select 2

FST_SPI_MISO BB12 Internal Bottom

1V8 Fast SPI Data Input

FST_SPI_MOSI BB11 Internal Bottom

1V8 Fast SPI Data Output

FST_SPI_WP# BB10 Internal Bottom

1V8 Fast SPI Write Ptrotect

FST_SPI_HOLD# BB9 Internal Bottom

1V8 Fast SPI Hold

SIO_SPI1_RXD BB4 Internal Bottom

1V8 SIO SPI Data Input

SIO_SPI1_TXD BB5 Internal Bottom

1V8 SIO SPI Data Output

SIO_SPI1_CLK BB6 Internal Bottom

1V8 SIO SPI Data Clock

SIO_SPI1_FS0 BB3 Internal Bottom

1V8 SIO SPI Frame Select 0

SIO_SPI1_FS1 BB7 Internal Bottom

1V8 SIO SPI Frame Select 1

Table 12. SPI Interfaces

3.2.13 UART Interfaces


UART0_TXD TL51 External Left 1V8 UART 0 data output

UART0_RXD TL50 External Left 1V8 UART 0 data send

UART0_CTS TL49 External Left 1V8 UART 0 Clear to Send

UART0_RTS TL48 External Left 1V8 UART 0 Ready to Send






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Table 13. UART Interfaces

3.2.14 I2C Interfaces


LPSS_I2C0_SDA TT45 External Top 1V8 I2C Serial Data 0

LPSS_I2C0_SCL TT46 External Top 1V8 I2C Serial Clock 0







CAM_I2C2_SDA (LPSS_I2C4_SDA)

TT35 External Top 1V8 I2C Serial Data 4

CAM_I2C2_SCL (LPSS_I2C4_SCL)

TT34 External Top 1V8 I2C Serial Clock 4

Table 14. I2C Interfaces

3.2.15 SoC GPIO Signals

Signal name Pin Connector I/O

Voltage Description

GPIO8 (GPIO_8) BB1 Internal Bottom

1V8 GPIO_8 Signal on SoC

GPIO1 (GPIO_0) TL58 External Left 1V8 GPIO_0 Signal on SoC




GPIO5 (GPIO_4) BL43 External Right 1V8 GPIO_4 Signal on SoC


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Table 15. SoC GPIO Signals

3.2.16 FPGA Transceiver Interfaces

Signal name Pin Connector FPGA Ball

Description

F_SPF_TX0_P (GXBL1C_TX_CH2P)

BR27 Internal Right

R22 High speed positive differential transmitter channel

F_SPF_TX0_N (GXBL1C_TX_CH2N)

BR26 Internal Right

R21 High speed negative differential transmitter channel

F_SPF_RX0_P (GXBL1C_RX_CH2P, GXBL1C_REFCLK2P)

BR25 Internal Right

N22 High speed positive differential receiver channel

F_SPF_RX0_N (GXBL1C_RX_CH2N, GXBL1C_REFCLK2N)

BR24 Internal Right

N21 High speed negative differential receiver channel

F_SPF_TX1_P (GXBL1C_TX_CH3P)

BR22 Internal Right

L22 High speed positive differential transmitter channel

F_SPF_TX1_N (GXBL1C_TX_CH3N)

BR21 Internal Right

L21 High speed negative differential transmitter channel

F_SPF_RX1_P (GXBL1C_RX_CH3P, GXBL1C_REFCLK3P)

BR20 Internal Right

J22 High speed positive differential receiver channel

F_SPF_RX1_N (GXBL1C_RX_CH3N, GXBL1C_REFCLK3N)

BR19 Internal Right

J21 High speed negative differential receiver channel

F_SPF_REFCLK_P (GXBL1C_RX_CH0P, GXBL1C_REFCLK0P)

BR17 Internal Right

Y20 High speed positive differential receiver channel

F_SPF_REFCLK_N (GXBL1C_RX_CH0N, GXBL1C_REFCLK0N)

BR16 Internal Right

Y19 High speed negative differential receiver channel

F_FMC_DP_C2M_N (GXBL1C_TX_CH1N)

TR26 External Right

W21 High speed negative differential transmitter channel

F_FMC_DP_C2M_P (GXBL1C_TX_CH1P)

TR27 External Right

W22 High speed positive differential transmitter channel

F_FMC_DP_M2C_N (GXBL1C_RX_CH1N, GXBL1C_REFCLK1N)

TR24 External Right

U21 High speed negative differential receiver channel

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F_FMC_DP_M2C_P (GXBL1C_RX_CH1P, GXBL1C_REFCLK1P)

TR25 External Right

U22 High speed positive differential receiver channel

F_FMC_DP_C2M_RES_P (GXBL1C_TX_CH0P)

BR15 Internal Right

AA21 High speed positive differential transmitter channel

F_FMC_DP_C2M_RES_N (GXBL1C_TX_CH0N)

BR14 Internal Right

AA22 High speed negative differential transmitter channel

F_FMC_GBTCLK_M2C0_N (REFCLK_GXBL1C_CHTN)

TR29 External Right

K19

High speed differential reference clock negative receiver channel

F_FMC_GBTCLK_M2C0_0 (REFCLK_GXBL1C_CHTP)

TR30 External Right

K20

High speed differential reference clock positive receiver channel

Table 16. Transceiver Interfaces

3.2.17 FPGA LVDS Interface

Signal name Pin Connector FPGA Ball

Matched Lenghts

(mil) Description

F_FMC_LA_RXN7 (LVDS2A_23N)

TB86 External Bottom

V10 1192 LVDS negative receiver / transmitter channel

F_FMC_LA_RXP7 (LVDS2A_23P)


W9 1194 LVDS positive receiver / transmitter channel

F_FMC_LA_RXN14 (LVDS2J_17N)


W10 1245 LVDS negative receiver / transmitter channel

F_FMC_LA_RXP14 (LVDS2J_17P)


V9 1245 LVDS positive receiver / transmitter channel


BB55 Internal Bottom

Y1 891 LVDS negative receiver / transmitter channel



Y2 890 LVDS positive receiver / transmitter channel





















T6 1038 LVDS negative receiver / transmitter channel



U6 1034 LVDS positive receiver / transmitter channel




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F_FMC_LA_TXN7 (LVDS2A_24N)

TT88 External Top

R10 1192 LVDS negative receiver / transmitter channel

F_FMC_LA_TXP7 (LVDS2A_24P)

TT89 External Top

T11 1194 LVDS positive receiver / transmitter channel


BR1 Internal Right



BR2 Internal Right



BR4 Internal Right



BR5 Internal Right



BR6 Internal Right



BR7 Internal Right



BR9 Internal Right



BR10 Internal Right



BR11 Internal Right

U13 929 LVDS negative receiver / transmitter channel


BR12 Internal Right



BR29 Internal Right



BR30 Internal Right

AA16 473 LVDS positive receiver / transmitter channel


BR31 Internal Right



BR32 Internal Right


F_FMC_LA_CC_N1 (CLK_2J_1N/LVDS2J_12N)

BR34 Internal Right

W15 747 LVDS negative receiver / transmitter channel, Clock input

F_FMC_LA_CC_P1 (CLK_2J_1P/LVDS2J_12P)

BR35 Internal Right

Y15 751 LVDS positive receiver / transmitter channel, Clock input

F_FMC_CLK_M2C_N1 (CLK_2J_0N/LVDS2J_13N)

BR36 Internal Right

AB11 597 LVDS negative receiver / transmitter channel, Clock input

F_FMC_CLK_M2C_P1 (CLK_2J_0P/LVDS2J_13P)

BR37 Internal Right

AB10 597 LVDS positive receiver / transmitter channel, Clock input

F_FMC_CLK_M2C_N0 (CLK_2A_0N/LVDS2A_13N)

BR39 Internal Right

V3 1045 LVDS negative receiver / transmitter channel, Clock input

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F_FMC_CLK_M2C_P0 (CLK_2A_0P/LVDS2A_13P)

BR40 Internal Right

U3 1047 LVDS positive receiver / transmitter channel, Clock input

F_FMC_LA_CC_N0 (CLK_2A_1N/LVDS2A_12N)

BR41 Internal Right

V1 1518 LVDS negative receiver / transmitter channel, Clock input

F_FMC_LA_CC_P0 (CLK_2A_1P/LVDS2A_12P)

BR42 Internal Right

U1 1519 LVDS positive receiver / transmitter channel, Clock input

F_FMC_LA_TXN10 (LVDS2J_5N)

TR1 External Right


F_FMC_LA_TXP10 (LVDS2J_5P)

TR2 External Right



TR3 External Right



TR4 External Right



TR6 External Right



TR7 External Right



TR8 External Right



TR9 External Right



TR32 External Right



TR33 External Right



TR34 External Right

AA14 578 LVDS negative receiver / transmitter channel


TR35 External Right

AB14 582 LVDS positive receiver / transmitter channel


TR37 External Right

AB13 649 LVDS negative receiver / transmitter channel


TR38 External Right



TR39 External Right



TR40 External Right



TR42 External Right



TR43 External Right



TR44 External Right



TR45 External Right



TR47 External Right



TR48 External Right



TR50 External Right


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TR51 External Right



TR52 External Right



TR53 External Right

AB3 1331 LVDS positive receiver / transmitter channel


TR55 External Right



TR56 External Right

R1 1579 LVDS positive receiver / transmitter channel


TR57 External Right

AB1 1431 LVDS negative receiver / transmitter channel


TR58 External Right


Table 17. LVDS Interface

3.2.18 FPGA GPIO Signals

FPGA Bank 2L


Voltage FPGA Ball

Description

F_SPI_CLK_1V5 (IO_2L_47_D9/1N/DQ0)

TR11 External Right 1V5 D9 I/O Pin

F_SPI_MISO_1V5 (IO_2L_42_E11/3P/DQ0)

TR13 External Right 1V5 E11 I/O Pin

F_SPI_MOSI_1V5 (IO_2L_46_D8/1P/DQ0)


F_SPI_CS0_1V5 (IO_2L_45_D10/2N/DQ0)


F_SPI_CS1_1V5 (IO_2L_44_E10/2P/DQ0)

TR14 External Right 1V5 E10 I/O Pin

IO_INT* (IO_2L_43_F11/3N/DQ0)

TT80 External Top 1V5 F11 I/O Pin

F_TX1_1V5 (IO_2L_41_F9/4N/DQSN0)


1V5 F9 I/O Pin

F_RX1_1V5 (IO_2L_39_E12/5N/DQ0)


1V5 E12 I/O Pin

F_RTS1_1V5 (IO_2L_40_E9/4P/DQSP0)


1V5 E9 I/O Pin

F_CTS1_1V5 (IO_2L_25_B11/12N/DQ1)


1V5 B11 I/O Pin

F_CAN_TX1_1V5 (IO_2L_11_B3/19N/DQ3)

TR20 External Right 1V5 B3 I/O Pin

F_CAN_RX1_1V5 (IO_2L_37_H11/6N/DQ0)

TR19 External Right 1V5 H11 I/O Pin

F_CAN_TX2_1V5 (IO_2L_10_A3/19P/DQ3)

TR18 External Right 1V5 A3 I/O Pin

F_CAN_RX2_1V5 (IO_2L_36_G11/6P/DQ0)

TR17 External Right 1V5 G11 I/O Pin

Table 18. FPGA Bank 2L GPIO Signals

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FPGA Bank 2J


Voltage FPGA Ball

Description

F_SDA (IO_2J_8_R18)


R18 1V8 I/O Pin

F_SCL (IO_2J_9_R19)


R19 1V8 I/O Pin

F_SPF0_SDA (IO_2J_2_V18)

TT86 External Top V18 1V8 I/O Pin

F_SPF0_SCL (IO_2J_3_V19)

TT87 External Top V19 1V8 I/O Pin

F_SPF1_SDA (IO_2J_6_T19)


T19 1V8 I/O Pin

F_SPF1_SCK (IO_2J_7_U19)


U19 1V8 I/O Pin

F_FMC_SDA (IO_2J_4_P17)

TR22 External Right P17 1V8 I/O Pin

F_FMC_SCL (IO_2J_5_N17)

TR21 External Right N17 1V8 I/O Pin

FMC_PRESENT (IO_2J_1_T17)


T17 1V8 I/O Pin

Table 19. FPGA Bank 2J GPIO Signals

FPGA Bank 2A


Voltage FPGA Ball

Description

F_GPIO_0 (IO_2A_12_AB6)

TT74 External Top 1V8 AB6 I/O Pin

F_GPIO_1 (IO_2A_11_AB9)

TT75 External Top 1V8 AB9 I/O Pin

F_GPIO_2 (IO_2A_9_Y9)

TT76 External Top 1V8 Y9 I/O Pin

F_GPIO_3 (IO_2A_7_V11)

TT77 External Top 1V8 V11 I/O Pin

F_GPIO_4 (IO_2A_5_T12)

TT78 External Top 1V8 T12 I/O Pin

Table 20. FPGA Bank 2A GPIO Signals

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3.2.19 FPGA JTAG Interface


Voltage FPGA Ball

Description

F_FPGA_TCK TT84 External Top 1V8 P5 JTAG Clock

F_FPGA_TDO TT83 External Top 1V8 M5 JTAG Data Out

F_FPGA_TDI TT82 External Top 1V8 M4 JTAG Data In

F_FPGA_TMS TT81 External Top 1V8 L3 JTAG Mode Select

Table 21. FPGA JTAG Intreface

3.2.20 Power Signals

Power Hard Signals


Voltage Description

5VSB

TT1,TT2, TT3 TT4, TT5, TT6 TT7, TT8,TT9 TT10

External Top 5V Power Input 5V

1V8A TT58 External Top 1V8 Power Output SoC 1V8

VCC_ADJ_F TT70, TT71, TT72, TT73

External Top 1V8 Power Output FPGA 1V8

VCCRTC_3P3 TT42 External Top 3V Power Input Battery 3V

1V5_MEM_F TB80 External Bottom

1V5 Power Output FPGA 1V5

Table 22. Power Signals

Power Management Signals


Voltage Description

PLTRST_N TT56 External Top 3V3 Platform Reset

PMU_RSTBTN# TT55 External Top 3V3 Reset Button Input

POWERBTNIN_N TT54 External Top 3V3 System Power Button Input

SOC_SLP_S3_N TT57 External Top 3V3 S3 Sleep Control

PMU_SUSCLK TL53 External Left 3V3 Suspend Clock

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CB_POK TL54 External Left 5V Power Input Enable SoC

F_EN_GROUP4 TT79 External Top 5V Power Output Enable FPGA

F_VREF_FMC (VREFB2xN0)


1V8 Input reference voltage for FPGA Bank 2J and 2A (T13 ,T17 Ball)

Note If PWRBTNIN_N is used CB_POK should be tied to low

Table 23. Power Management Signals

Ground Signal

Signal name

Pin Description

GND

TT11, TT12, TT13, TT14, TT15, TT16, TT17, TT18, TT25, TT32, TT38, TT43, TT53, TT59, TT64, TT85, TL52, TL34, TL39, TL12, TL29, TL6, TL1, TL25, TR46, TR49, TR54, TR36, TR41, TR31, TR16, TR10, TR5, TR28, TR23 TB39, TB29, TB24, TB15, TB10, TB5, TB34, TB53, TB57, TB62, TB65, TB70, TB79, TB44, TB85 BL33, BL25, BL28, BL13, BL22, BL10, BL5, BL19, BL16 BR33, BR38, BR43, BR28, BR23, BR13, BR8, BR3, BR18 BB32, BB21, BB16, BB8, BB2, BB27, BB24, BB46, BB49, BB54, BB57, BB62, BB67, BB37, BB42

Ground

Table 24. Ground Signal

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4 SoC Ambient

This chapter introduces all major components and features the Intel Atom Processor.

4.1 Display Interfaces

The gigaSOM offers the following display interfaces:

• 2x DDI (DP/HDMI)

• 1x eDP 1.3

DDI interface supports HDMI 1.4b, maximum resolution is up to 3840x2160 @ 30 Hz and DP 1.2, maximum resolution is up to 4096x2160 @ 60 Hz. HDMI 2.0 supported using a protocol converter on DP lanes. An eDP interface can be configured to up-to 4 lanes. Maximum resolution is 3840x2160 @ 60Hz. For control signal can be used Panel0 or Panel1.

4.2 CSI Interface

The gigaSOM support CSI image sensor connected on four dedicated DPHY 1.1 lanes and one differential clock lane, running at a maximum frequency of 1.5 GHz.

4.3 SD Card, SDIO Interface

The gigaSOM has SD card controller, which conforms to the SD card SD3.01 specification. The data rates supported are SDR104/50/25/12 and DDR50. The Default speed mode supports 2.5MB/s and the High-Speed mode supports 25MB/s. The gigaSOM support SDIO specification version 3.00. The data rate support up to 104 MB/s using 4 parallel data lines (SDR104 mode).

4.4 USB Interfaces

The gigaSOM offers the following USB interfaces:

• 4x USB 2.0

• 2x USB 3.0

USB 2.0 supports 2.0 specifications, data transfer up to 480 Mbps, high-speed, full-speed and low-speed signaling. USB 3.0 supports 3.0 specifications, data transfer up to 5 Gbps, SuperSpeed, high-speed, full-speed and low-speed signaling.

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4.5 PCIe Interfaces

The gigaSOM features up to 4 PCI Express ports and 6 lanes can be allocated over those 4 ports. The lanes support up to 5 GT/s (Gen 2) speed, lane polarity inversion. One PCIe with 2 lanes is connected to the FPGA, then another PCIe with 1 lane is connected to I210 Gigabit transceiver. For the carrier board has provided up to 2 PCIe and 3 lanes.

Figure 6. PCIe Diagram

4.6 SATA Interfaces

The gigaSOM offers up to two SATA ports that are capable of independent DMA operation. The SATA controllers are completely software transparent with an AHCI interface, while providing a lower pin count and higher performance than the legacy parallel ATA interface. The interface support data transfer rates up to 6.0 Gb/s.

4.7 Audio Interfaces

The gigaSOM offers the following audio interfaces:

• 2x I2S interfaces (I2S0, I2S1)

• 1x HDA interface (I2S3)

High Definition Audio PINs are multiplexed with the I2S3 bus and can be configured for connection to an end device. The architecture of the Intel HD Audio link allows a maximum of one codec to be connected. HDA_BCLK signal is the clock for HD Audio interface. HDA_BCLK is a 24.000 MHz clock driven by SoC to any codec present on the link.

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4.8 Gigabit Ethernet

The gigaSOM offers Gigabit ethernet interfaces via Intel i210 Gigabit transceiver. The interfaces support full-duplex operation at 10/100/1000 Mbps and half-duplex operation at 10/100 Mbps.

4.9 I2C Interfaces

The gigaSOM offers the following I2C interfaces:

• 5x I2C

• 1x SMBus

Each I2C interface supports standard mode (up to 100 Kb/s), fast mode (up to 400 Kb/ s), and fast mode plus (up to 1 Mb/s). High-speed mode (up to 3.1 Mb/s) is also supported. Both 7-bit and 10-bit addressing modes are supported. The I2C interface supports 1.8 V signaling. SMBus 2.0 host controller is part of the PCU. The SMBus host controller provides a mechanism for the SoC to initiate communications with SMBus peripherals (slaves). The controller is also capable of operating in a mode in which it can communicate with I2C compatible devices.

4.10 SPI Interfaces

The gigaSOM offers the following SPI interfaces:

• 3x SPI (LPSS)

• 1x Fast SPI

Low-Power Sub-System SPI (LPSS SPI) is a dedicated SPI interface to connect to Finger Print Sensors. SPI_0 is connected to the FRAM Memory (64K x 8, MB85RS512T). SPI_2 is connected via multiplexor to the Serial NOR Flash Memory (128M x 8, MT25QU01GBBB). For the carrier board has provided SPI_1.

Figure 7. SPI Diagram

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Fast SPI interface can be used as the primary boot device. Maximum frequency of operation of Fast SPI interface is 50MHz. This interface is 1.8V compliant only. This Interface supports up to 2 SPI flash devices via 2 chip select (SPI_CS0_N and SPI_CS1_N), dedicated chip select pin (SPI_CS2_N) for TPM. Fast SPI is connected to Serial Flash Memory (128Mbit, W25Q128FW) and it is provided for the carrier board. Also, it is connected on TPM SLB9670.

Figure 8. Fast SPI Diagram

4.11 UART Interfaces

The gigaSOM provides three UART ports. Each supports up to 3.8 Mbit/s. The controllers can be used in the low-speed, full-speed, and high-speed modes. The controllers are based on the 16550 industry standard and communicate with serial data ports that conform to the RS-232 interface protocol. The UART controllers integrate a 4-wire interface using RTS/CTS Flow Control. These UART ports can be used as part of the LPSS subsystems. On gigaSOM platform the UART port usage is as below:

• UART0: Generic Usage

• UART1: GNSS

• UART2: Debug/Serial port output

For multifunction devices, function0 cannot be disabled/hidden, or PCIe discovery of the other functions won't work correctly. In this case, UART0 is Function0, so it needs to be enabled (or not disabled) in order to see the other exposed UART ports/functions to be available. Only UART2 supports debug functionality.

4.12 Soc GPIO Signals

The gigaSOM offers 15 SoC GPIOs. These GPIOs are controlled by SoC.

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4.13 LPC Bus

The gigaSOM offers LPC interfaces for legacy device support.

4.14 Onboard Interfaces

The gigaSOM offers the following standard interfaces:

• eMMC 5.0 (SSD) with up to 64 GB capacity

• Quad- or dual-channel low voltage memory (LPDDR4) with up to 2400 MTps and up to 8 GB

capacity

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5 FPGA Ambient

This chapter introduces all major components and features the Intel Cyclone 10GX.

5.1 Transceiver Interfaces

The gigaSOM (Cyclone 10GX) has 6 channels of transceivers that can support data rates up to 12.5 Gbps for chip-to-chip and chip-to-module communication, and up to 6.6 Gbps for backplane communication. You can achieve transmit and receive data rates below 1.0 Gbps with oversampling. Also, the Cyclone 10GX has 2 master clocks. The master clocks divides and distributes bonded clocks to a bonded channel group. It also distributes non-bonded clocks to non-bonded channels across the x6/xN clock network. Each transceiver channel has a local clock. The local clock is used for dividing and distributing non-bonded clocks to its own PCS and PMA blocks. Two channels and 1 master clock are connected to PCIe from SoC. For the carrier board has provided up to 4 channels and 1 master clock.

5.2 LVDS

The gigaSOM has provided up to 36 LVDS with 4 LVDS Clock for the carrier board.

5.3 FPGA GPIO Signals

The gigaSOM offers 28 FPGA GPIOs. These GPIOs are controlled by FPGA.

5.4 Memory

The gigaSOM (Cyclone 10GX) offers the following memory interfaces:

• 2x DDR3 memory up to 800 MHz

• SPI Flash memory

FPGA SPI for Flash memory is shared with SPI_2 by SoC via multiplexer. By using the signal MUX_SEL, it is possible to determine whether the interface FPGA SPI or SoC SPI_2 active. MUX_SEL (GPIO_24) is controlled by SoC.

MUX_SEL Configuration

Low Enable FPGA SPI, disable SoC SPI

High Enable SoC SPI, disable FPGA SPI

Table 25. Mux Selector Description

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5.5 LEDs

The gigaSOM offers the following LEDs:

Signal Name FPGA Ball Colour Function

F_CONF_DONE M1 Yellow Indicates programing FPGA

DL_LED AB16 Red Indicates diagnostic

FAULT_LED R17 Green Indicates error

Table 26. LED Description

5.6 JTAG

The gigaSOM provides a JTAG interface. This interface is used for programming and debugging Cyclone 10GX FPGA.

5.7 FPGA reconfiguration from CPU

During SPI flash programming from CPU FPGA should be in reset state. After FPGA file is written to flash, FPGA should be active again. This can be done by triggering CPUs GPIO_3 in a way described in table below.

GPIO_3 Configuration

Low FPGA in active state

High FPGA in reset state

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6 Additional Features

This chapter will show additional features of gigaSOM.

6.1 Power Control

The gigaSOM operates only with 5 V input voltage. Its power-up sequence is described below:

1. The 5 V input voltage (5VSB) supplied to the carrier board powers the gigaSOM.

2. The gigaSOM enables its power circuits if the CB_POK signal is high.

3. Depending on the carrier board design and configuration, the gigaSOM detects a power

button event (POWERBTNIN_N) if implemented.

4. The gigaSOM enables the carrier board power by asserting F_EN_GROUP4 and

SOC_SLP_S3_N.

5. The gigaSOM releases the PLTRST_N and starts the boot process.

The power control signals are described below:

Signal Name Description

CB_POK When is low, it indicates that the input voltage to the gigaSOM is either not ready or out of specified range. Carrier board hardware should drive this signal low until the input power is up and stable

F_EN_GROUP4 The gigaSOM asserts this signal when its power supplies for SoC are up, and subsequently enables the carrier board power supplies

SOC_SLP_S3_N Can be used to indicate that the gigaSOM is going into suspend state, where only power management functions and system memory are powered

PMU_RSTBTN# The signal may be used to force the gigaSOM to reset or reboot

PLTRST_N The gigaSOM asserts this signal during the power-up sequencing to allow the carrier board power circuits to come up

POWERBTNIN_N This power button signal is used to wake up or shut down

Table 27. Power Control Description

6.2 Temperature Sensor

The gigaSOM is equipped with a temperature sensor, TMP513, which provides temperature sensing. This function is accomplished by connecting the temperature sensor to the internal temperature sensing diode of the FPGA device. The temperature status and alarm threshold registers of the temperature sensor can be programmed by a two-wire SMBus, which is connected to the SoC.

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6.3 Booting

The gigaSOM is booting via BIOS SPI flash memory on the Fast SPI interface. Signals for booting are on header (1.27 mm pitch).

Pin Signal name Description Pin Signal name Description

1 +1V8 Input voltage (1V8) 2 GND Ground

3 BIOS_SPI_CS#0 Bios (Fast) SPI Chip Select

4 BIOS_SPI_CLK Bios (Fast) SPI Clock

5 BIOS_SPI_SO Bios (Fast) SPI Data Output

6 BIOS_SPI_SI Bios (Fast) SPI Data Input

Table 28. Booting Header Description

6.4 Flexible I/O Adapter

Flexible I/O is a technology that allows some high-speed I/O (HSIO) lanes to be configured for connection to a PCI Express, USB 3.0, or SATA controller. The Flexible I/O enables customers to optimize the allocation of high-speed I/O interfaces to better meet the I/O needs of their system. The selection of the I/O technology is handled through soft straps in the SPI flash.

There are 7 HSIO lanes in gigaSOM Edge Pads that split between PCI Express, USB 3.0, or SATA controller. The following figure shows the multiplexing of the gigaSOM HSIO Lanes.

0 1 2 3 4 5 6

US

B 3

.0 P

0

US

B 3

.0 P

1

US

B 3

.0 P

2

US

B 3

.0 P

4 PC

Ie P

2

SA

TA

3.0

P1

SA

TA

3.0

P0

PC

Ie P

5

PC

Ie P

3

US

B 3

.0 P

5

Figure 9. High-speed I/O Lane Multiplexing

The 7 HSIO lanes on gigaSOM Edge Pads support the following port configurations:

• Up to 3 PCIe lanes (multiplexed with USB 3.0 ports)

• Up to 2 SATA 3.0 ports (multiplexed with USB 3.0)

• Up to 5 USB 3.0 ports (multiplexed with PCIe and SATA Port

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7 Soldering profile

The gigaSOM board must be attached to the host carrier board using industry standard reflow processes. Recommended solder paste stencil thickness is 150um to ensure solder joint reliability. In order to avoid component damage, consider following reflow parameters:

• Preheat and cool-down ramps should not exceed 3°C/sec to prevent internal component failures due to thermal stress

• The reflow temperatures must exceed the nominal melting point of the solder paste for at least 30 seconds, not to exceed 90 seconds

• Maximal peak reflow temperature is 260°C • The time reflow temperature is within 5°C of peak temperature must not exceed 30 seconds

The gigaSOM is moisture sensitive and should be handled by heeding MSL 3 guidelines (JEDEC standard J-STD-020) to prevent any damage from moisture absorption and exposure to the solder reflow temperatures that can result in yield and reliability degradation. Once the package is unsealed, following conditions should be adhered:

• Relative humidity <50% • Temperature 20-25°C • Fingerprints must be avoided, gloves are highly recommended

• Do not expose the board to the corrosive or liquid environments • Pre-dry according to the IPC-1601 before assembly

• The device should go through reflow within 72 hours, otherwise baking is required before board mounting

• If baking is required, device should be baked for a minimum of 8 hours at 120°C • Unused board can either be baked and dry-packed before storage, or it can be baked just

before the next board assembly

Figure 10. Soldering Thermal Profile

Software Notes SHW · 2020. 11. 17. · PANEL1_VDDEN TB20 External Bottom 1V8 Panel Power Enable 1 for eDP/MDSI Table 1. Display Interfaces 3.2.2 CSI Interface Signal name Pin Connecto

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