PRE CLK D CLR Q Q C C C C C C C C C C TG TG TG TG Product Folder Sample & Buy Technical Documents Tools & Software Support & Community SN54HC74, SN74HC74 SCLS094E – DECEMBER 1982 – REVISED DECEMBER 2015 SNx4HC74 Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and Preset 1 Features 3 Description The SNx4HC74 devices contain two independent D- 1• Wide Operating Voltage Range: 2 V to 6 V type positive-edge-triggered flip-flops. A low level at • Outputs Can Drive Up To 10 LSTTL Loads the preset (PRE) or clear (CLR) inputs sets or resets • Low Power Consumption, 40-μA Maximum I CC the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data • Typical t pd = 15 ns at the data (D) input meeting the setup time • ±4-mA Output Drive at 5 V requirements are transferred to the outputs on the • Very Low Input Current of 1 μA positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly 2 Applications related to the rise time of CLK. Following the hold- time interval, data at the D input can be changed • Ultrasound System without affecting the levels at the outputs. • Fans • Lab Instrumentation Device Information (1) PART NUMBER PACKAGE BODY SIZE (NOM) • Vacuum Cleaners SN74HC74N PDIP (14) 19.30 mm x 6.40 mm • Video Communications System SN74HC74NS SO (14) 10.20 mm x 5.30 mm • IP Phone: Wired SN74HC74D SOIC (14) 8.70 mm x 3.90 mm SN74HC74DB SSOP (14) 6.50 mm x 5.30 mm SN74HC74PW TSSOP (14) 5.00 mm x 4.40 mm SNJ54HC74J CDIP (14) 21.30 mm x 7.60 mm SNJ54HC74W CFP (14) 9.20 mm x 6.29 mm SNJ54HC74FK LCCC (20) 8.90 mm x 8.90 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Logic Diagram (Positive Logic) 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.
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PRE
CLK
D
CLR
Q
Q
C
C
C
C
C
C
C
C
C
C
TG
TG TGTG
Product
Folder
Sample &Buy
Technical
Documents
Tools &
Software
Support &Community
SN54HC74, SN74HC74SCLS094E –DECEMBER 1982–REVISED DECEMBER 2015
SNx4HC74 Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and Preset1 Features 3 Description
The SNx4HC74 devices contain two independent D-1• Wide Operating Voltage Range: 2 V to 6 V
type positive-edge-triggered flip-flops. A low level at• Outputs Can Drive Up To 10 LSTTL Loads the preset (PRE) or clear (CLR) inputs sets or resets• Low Power Consumption, 40-µA Maximum ICC the outputs, regardless of the levels of the other
inputs. When PRE and CLR are inactive (high), data• Typical tpd = 15 nsat the data (D) input meeting the setup time• ±4-mA Output Drive at 5 V requirements are transferred to the outputs on the
• Very Low Input Current of 1 µA positive-going edge of the clock (CLK) pulse. Clocktriggering occurs at a voltage level and is not directly
2 Applications related to the rise time of CLK. Following the hold-time interval, data at the D input can be changed• Ultrasound Systemwithout affecting the levels at the outputs.
• Fans• Lab Instrumentation Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)• Vacuum CleanersSN74HC74N PDIP (14) 19.30 mm x 6.40 mm• Video Communications SystemSN74HC74NS SO (14) 10.20 mm x 5.30 mm• IP Phone: WiredSN74HC74D SOIC (14) 8.70 mm x 3.90 mmSN74HC74DB SSOP (14) 6.50 mm x 5.30 mmSN74HC74PW TSSOP (14) 5.00 mm x 4.40 mmSNJ54HC74J CDIP (14) 21.30 mm x 7.60 mmSNJ54HC74W CFP (14) 9.20 mm x 6.29 mmSNJ54HC74FK LCCC (20) 8.90 mm x 8.90 mm
(1) For all available packages, see the orderable addendum atthe end of the data sheet.
Logic Diagram (Positive Logic)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN54HC74, SN74HC74www.ti.com SCLS094E –DECEMBER 1982–REVISED DECEMBER 2015
5 Pin Configuration and Functions
N, NS, D, DB, PW, J, or W Package FK Package14-Pin PDIP, SO, SOIC, SSOP, TSSOP, CDIP, or CFP 20-Pin LCCC
Top View Top View
NC – No internal connection
Pin FunctionsPIN
SOIC, SSOP, CDIP, I/O DESCRIPTIONNAME LCCC PDIP, SO, TSSOP, CFP
NO.1CLK 4 3 I Clock input1CLR 2 1 I Clear input - Pull low to set 1Q output low1D 3 2 I Input1PRE 6 4 I Preset input1Q 8 5 O Output1Q 9 6 O Inverted output2CLK 16 11 I Clock input2CLR 19 13 I Clear input - Pull low to set 1Q output low2D 18 12 I Input2PRE 14 10 I Preset input2Q 13 9 O Output2Q 12 8 O Inverted outputGND 10 7 — Ground
SN54HC74, SN74HC74SCLS094E –DECEMBER 1982–REVISED DECEMBER 2015 www.ti.com
6 Specifications
6.1 Absolute Maximum Ratingsover operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNITVCC Supply voltage range –0.5 7 VIIK Input clamp current (2) VI < 0 or VI > VCC ±20 mAIOK Output clamp current (2) VO < 0 or VO > VCC ±20 mAIO Continuous output current VO = 0 to VCC ±25 mA
Continuous current through VCC or GND ±50 mATj Junction temperature range 150 °CTstg Storage temperature range –65 150 °C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operatingconditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
6.2 ESD RatingsVALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000V(ESD) Electrostatic discharge VCharged-device model (CDM), per JEDEC specification JESD22- ±1500C101 (2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing withless than 500-V HBM is possible with the necessary precautions.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing withless than 250-V CDM is possible with the necessary precautions.
6.3 Recommended Operating ConditionsSee (1)
SN54HC74 SN74HC74UNIT
MIN NOM MAX MIN NOM MAXVCC Supply voltage 2 5 6 2 5 6 V
VCC = 2 V 1.5 1.5VIH High-level input voltage VCC = 4.5 V 3.15 3.15 V
VCC = 6 V 4.2 4.2VCC = 2 V 0.5 0.5
VIL Low-level input voltage VCC = 4.5 V 1.35 1.35 VVCC = 6 V 1.8 1.8
VI Input voltage 0 VCC 0 VCC VVO Output voltage 0 VCC 0 VCC V
VCC = 2 V 1000 1000∆t/∆v Input transition rise and fall time VCC = 4.5 V 500 500 ns
VCC = 6 V 400 400TA Operating free-air temperature –55 125 –40 85 °C
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,Implications of Slow or Floating CMOS Inputs, SCBA004.
SN54HC74, SN74HC74www.ti.com SCLS094E –DECEMBER 1982–REVISED DECEMBER 2015
7 Parameter Measurement Information
A. CL includes probe and test-fixture capacitance.B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having
the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.C. For clock inputs, fmax is measured when the input duty cycle is 50%.D. The outputs are measured one at a time with one input transition per measurement.E. tPLH and tPHL are the same as tpd.
SN54HC74, SN74HC74SCLS094E –DECEMBER 1982–REVISED DECEMBER 2015 www.ti.com
8 Detailed Description
8.1 OverviewFigure 3 describes the SNx4HC74 devices. As the SNx4HC74 is a dual D-Type positive-edge-triggered flip-flopwith clear and preset, the diagram below describes one of the two device flip-flops.
8.2 Functional Block Diagram
Figure 3. Logic Diagram (Positive Logic)
8.3 Feature DescriptionThe SNx4HC74 inputs accept voltage levels up to 5.5 V. Refer to the Recommended Operating Conditions forappropriate input high and low logic levels.
8.4 Device Functional ModesTable 1 lists the functional modes of the SNx4HC74.
Table 1. Function TableINPUTS OUTPUTS
PRE CLR CLK D Q QL H X X H LH L X X L HL L X X H (1) H (1)
H H ↑ H H LH H ↑ L L HH H L X Q0 Q0
(1) This configuration is nonstable; that is, it does not persist when PRE or CLR returns to its inactive(high) level.
SN54HC74, SN74HC74www.ti.com SCLS094E –DECEMBER 1982–REVISED DECEMBER 2015
9 Application and Implementation
NOTEInformation in the following applications sections is not part of the TI componentspecification, and TI does not warrant its accuracy or completeness. TI’s customers areresponsible for determining suitability of components for their purposes. Customers shouldvalidate and test their design implementation to confirm system functionality.
9.1 Application InformationA low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of theother inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup timerequirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occursat a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval,data at the D input can be changed without affecting the levels at the outputs.
The resistor and capacitor at the CLR pin are optional. If they are not used, the CLR pin should be connecteddirectly to VCC to be inactive.
9.2 Typical Application
Figure 4. Device Power Button Circuit
9.2.1 Design RequirementsThis device uses CMOS technology and has balanced output drive. Take care to avoid bus contention because itcan drive currents that would exceed maximum limits. Outputs may be combined to produce higher drive, but thehigh drive will also create faster edges into light loads. Because of this, routing and load conditions should beconsidered to prevent ringing.
– For rise time and fall time specifications, see (Δt/ΔV) in Recommended Operating Conditions table.– For specified high and low levels, see (VIH and VIL) in Recommended Operating Conditions table.– Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC.
2. Recommended Output Conditions:– Load currents should not exceed 25 mA per output and 50 mA total for the part.– Series resistors on the output may be used if the user desires to slow the output edge signal or limit the
10 Power Supply RecommendationsThe power supply can be any voltage between the minimum and maximum supply voltage rating located in theRecommended Operating Conditions table. Each VCC terminal should have a good bypass capacitor to preventpower disturbance. For devices with a single supply, a 0.1-μF capacitor is recommended and if there are multipleVCC terminals then .01-μF or .022-μF capacitors are recommended for each power terminal. It is acceptable toparallel multiple bypass caps to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors arecommonly used in parallel. The bypass capacitor should be installed as close to the power terminal as possiblefor best results.
SN54HC74, SN74HC74www.ti.com SCLS094E –DECEMBER 1982–REVISED DECEMBER 2015
11 Layout
11.1 Layout GuidelinesWhen using multiple bit logic devices, inputs should not float. In many cases, functions or parts of functions ofdigital logic devices are unused. Some examples are when only two inputs of a triple-input AND gate are used,or when only 3 of the 4-buffer gates are used. Such input pins should not be left unconnected because theundefined voltages at the outside connections result in undefined operational states.
Specified in Figure 6 are rules that must be observed under all circumstances. All unused inputs of digital logicdevices must be connected to a high or low bias to prevent them from floating. The logic level that must beapplied to any particular unused input depends on the function of the device. Generally they are tied to GND orVCC, whichever makes more sense or is more convenient. It is acceptable to float outputs unless the part is atransceiver. If the transceiver has an output enable pin, it disables the output section of the part when asserted.This pin keeps the input section of the I/Os from being disabled and floated.
SN54HC74, SN74HC74SCLS094E –DECEMBER 1982–REVISED DECEMBER 2015 www.ti.com
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related DocumentationFor related documentation, see the following:
Implications of Slow or Floating CMOS Inputs, SCBA004
12.2 Related LinksThe table below lists quick access links. Categories include technical documents, support and communityresources, tools and software, and quick access to sample or buy.
Table 2. Related LinksTECHNICAL TOOLS & SUPPORT &PARTS PRODUCT FOLDER SAMPLE & BUY DOCUMENTS SOFTWARE COMMUNITY
SN54HC74 Click here Click here Click here Click here Click hereSN74HC74 Click here Click here Click here Click here Click here
12.3 Community ResourcesThe following links connect to TI community resources. Linked contents are provided "AS IS" by the respectivecontributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms ofUse.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaborationamong engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and helpsolve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools andcontact information for technical support.
12.4 TrademarksE2E is a trademark of Texas Instruments.All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge CautionThese devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.
12.6 GlossarySLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable InformationThe following pages include mechanical packaging and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and revision ofthis document. For browser based versions of this data sheet, refer to the left hand navigation.
SN74HC74DG4 ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC74
SN74HC74DR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 85 HC74
SN74HC74DRG4 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC74
SN74HC74DT ACTIVE SOIC D 14 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC74
SN74HC74N ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 SN74HC74N
SN74HC74NE4 ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 SN74HC74N
SN74HC74NSR ACTIVE SO NS 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC74
SN74HC74PW ACTIVE TSSOP PW 14 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC74
SN74HC74PWG4 ACTIVE TSSOP PW 14 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC74
SN74HC74PWR ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 85 HC74
SN74HC74PWT ACTIVE TSSOP PW 14 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC74
SNJ54HC74FK ACTIVE LCCC FK 20 1 Non-RoHS& Green
SNPB N / A for Pkg Type -55 to 125 84056012ASNJ54HC74FK
SNJ54HC74J ACTIVE CDIP J 14 1 Non-RoHS& Green
SNPB N / A for Pkg Type -55 to 125 8405601CASNJ54HC74J
SNJ54HC74W ACTIVE CFP W 14 1 Non-RoHS& Green
SNPB N / A for Pkg Type -55 to 125 8405601DASNJ54HC74W
(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substancedo not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI mayreference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide basedflame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to twolines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54HC74, SN54HC74-SP, SN74HC74 :
• Catalog : SN74HC74, SN54HC74
• Automotive : SN74HC74-Q1, SN74HC74-Q1
• Enhanced Product : SN74HC74-EP, SN74HC74-EP
• Military : SN54HC74
• Space : SN54HC74-SP
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
NOTES: A. All linear dimensions are in millimeters.B. This drawing is subject to change without notice.C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.D. Falls within JEDEC MO-150
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PACKAGE OUTLINE
C
14X .008-.014 [0.2-0.36]TYP
-150
AT GAGE PLANE
-.314.308-7.977.83[ ]
14X -.026.014-0.660.36[ ]14X -.065.045
-1.651.15[ ]
.2 MAX TYP[5.08]
.13 MIN TYP[3.3]
TYP-.060.015-1.520.38[ ]
4X .005 MIN[0.13]
12X .100[2.54]
.015 GAGE PLANE[0.38]
A
-.785.754-19.9419.15[ ]
B -.283.245-7.196.22[ ]
CDIP - 5.08 mm max heightJ0014ACERAMIC DUAL IN LINE PACKAGE
4214771/A 05/2017
NOTES: 1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M.2. This drawing is subject to change without notice. 3. This package is hermitically sealed with a ceramic lid using glass frit.4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only.5. Falls within MIL-STD-1835 and GDIP1-T14.
7 8
141
PIN 1 ID(OPTIONAL)
SCALE 0.900
SEATING PLANE
.010 [0.25] C A B
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EXAMPLE BOARD LAYOUT
ALL AROUND[0.05]
MAX.002
.002 MAX[0.05]ALL AROUND
SOLDER MASKOPENING
METAL
(.063)[1.6]
(R.002 ) TYP[0.05]
14X ( .039)[1]
( .063)[1.6]
12X (.100 )[2.54]
(.300 ) TYP[7.62]
CDIP - 5.08 mm max heightJ0014ACERAMIC DUAL IN LINE PACKAGE
4214771/A 05/2017
LAND PATTERN EXAMPLENON-SOLDER MASK DEFINED
SCALE: 5X
SEE DETAIL A SEE DETAIL B
SYMM
SYMM
1
7 8
14
DETAIL ASCALE: 15X
SOLDER MASKOPENING
METAL
DETAIL B13X, SCALE: 15X
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