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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN54HC00, SN74HC00SCLS181F –DECEMBER 1982–REVISED JULY 2016
SNx4HC00 Quadruple 2-Input Positive-NAND Gates
1
1 Features1• Wide Operating Voltage Range of 2 V to 6 V• Outputs Can Drive Up to 10 LSTTL Loads• Low Power Consumption: ICC 20-µA (Maximum)• Typical tpd: 8 ns• ±4-mA Output Drive at 5 V• Low Input Current: 1 µA (Maximum)• On Products Compliant to MIL-PRF-38535,
All Parameters Are Tested Unless OtherwiseNoted. On All Other Products, ProductionProcessing Does Not Necessarily Include Testingof All Parameters.
2 Applications• AV Receivers• Portable Audio Docks• Blu-ray Players and Home Theater• MP3 Players or Recorders• Personal Digital Assistants (PDAs)• Power: Telecom or Server AC/DC Supply
(Single Controller: Analog and Digital)• Solid State Drives (SSDs): Client and Enterprise• TVs: LCD, Digital, and High-Definition (HDTV)• Tablets: Enterprise• Video Analytics: Server• Wireless Headsets, Keyboards, and Mice
3 DescriptionThe SN54HC00 and SN74HC00 devices contain fourindependent, 2-input NAND gates. They perform theBoolean function Y = A × B or Y = A + B in positivelogic.
Device Information(1)
PART NUMBER PACKAGE (PINS) BODY SIZE (NOM)
SN54HC00CDIP (14) 6.92 mm × 19.94 mmCFP (14) 6.20 mm × 9.41 mmLCCC (20) 8.89 mm × 8.89 mm
SN74HC00D SOIC (14) 8.65 mm × 3.91 mmSN74HC00DB SSOP (14) 6.20 mm × 5.30 mmSN74HC00N PDIP (14) 19.30 mm × 6.35 mmSN74HC00NS SOP (14) 10.30 mm × 5.30 mmSN74HC00PW TSSOP (14) 5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum atthe end of the data sheet.
10 Power Supply Recommendations ..................... 1011 Layout................................................................... 10
11.1 Layout Guidelines ................................................ 1011.2 Layout Example ................................................... 10
12 Device and Documentation Support ................. 1112.1 Documentation Support ........................................ 1112.2 Related Links ........................................................ 1112.3 Receiving Notification of Documentation Updates 1112.4 Community Resources.......................................... 1112.5 Trademarks ........................................................... 1112.6 Electrostatic Discharge Caution............................ 1112.7 Glossary ................................................................ 11
13 Mechanical, Packaging, and OrderableInformation ........................................................... 11
4 Revision HistoryNOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (August 2003) to Revision F Page
• Added Applications section, Device Information table, ESD Ratings table, Typical Characteristics section, FeatureDescription section, Device Functional Modes, Application and Implementation section, Power SupplyRecommendations section, Layout section, Device and Documentation Support section, and Mechanical,Packaging, and Orderable Information section ...................................................................................................................... 1
• Added Military Disclaimer to Features list .............................................................................................................................. 1• Removed Ordering Information table; see POA at the end of data sheet.............................................................................. 1• Changed values in the Thermal Information table to align with JEDEC standards................................................................ 5• Deleted Operating Characteristics table; moved Cpd row to Electrical Characteristics......................................................... 5
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratingsonly, which do not imply functional operation of the device at these or any other conditions beyond those indicated under RecommendedOperating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
6 Specifications
6.1 Absolute Maximum Ratingsover operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNITSupply voltage, VCC –0.5 7 VInput clamp current, IIK (VI < 0 or VI > VCC) (2) ±20 mAOutput clamp current, IOK (VO < 0 or VO > VCC)(2) ±20 mAContinuous output current, IO (VO = 0 to VCC) ±25 mAContinuous current through VCC or GND ±50 mAStorage temperature, Tstg –65 150 °C
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.2 ESD RatingsVALUE UNIT
V(ESD) Electrostatic dischargeHuman-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000
VCharged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±1000
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to Implications of Slow or FloatingCMOS Inputs application report.
6.3 Recommended Operating Conditionsover operating free-air temperature range (unless otherwise noted) (1)
MIN NOM MAX UNITVCC Supply voltage 2 5 6 V
VIH High-level input voltageVCC = 2 V 1.5
VVCC = 4.5 V 3.15VCC = 6 V 4.2
VIL Low-level input voltageVCC = 2 V 0.5
VVCC = 4.5 V 1.35VCC = 6 V 1.8
VI Input voltage 0 VCC VVO Output voltage 0 VCC V
∆t/∆v Input transition rise and fall timeVCC = 2 V 1000
NOTES: A. CL includes probe and test-fixture capacitance.B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by
generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.C. The outputs are measured one at a time with one input transition per measurement.D. tPLH and tPHL are the same as tpd.
8.1 OverviewThe SNx4HC00 devices perform the NAND Boolean function Y = A × B or Y = A + B in positive logic. Thedevices have a wide operating range of VCC from 2 V to 6 V.
8.2 Functional Block Diagram
8.3 Feature DescriptionThe SNx4HC00 devices have a wide operating voltage range that operates from 2 V to 6 V. They allow inputsand outputs up to VCC. The devices can drive outputs at 4 mA at 5-V VCC.
8.4 Device Functional ModesTable 1 lists the functional modes for the SNx4HC00.
NOTEInformation in the following applications sections is not part of the TI componentspecification, and TI does not warrant its accuracy or completeness. TI’s customers areresponsible for determining suitability of components for their purposes. Customers shouldvalidate and test their design implementation to confirm system functionality.
9.1 Application InformationThe SNx4HC00 is a low-power, wide-operating-voltage NAND gate. This device can drive up to 10 LSTTL loadsand can drive 4-mA outputs at 5-V VCC.
9.2 Typical Application
Figure 3. Typical NAND Gate Application and Supply Voltage
9.2.1 Design RequirementsThe SNx4HC00 devices use CMOS technology and have balanced output drive. Take care to avoid buscontention because it drives currents that would exceed maximum limits. The high drive also creates fast edgesinto light loads. Routing and load conditions must be considered to prevent ringing.
10 Power Supply RecommendationsThe power supply can be any voltage between the MIN and MAX supply voltage rating located in RecommendedOperating Conditions.
Each VCC pin must have a good bypass capacitor to prevent power disturbance. For devices with a single supply,TI recommends a 0.1-µF bypass capacitor; if there are multiple VCC pins, then TI recommends 0.01-µF or0.022-µF bypass capacitors for each power pin. It is acceptable to parallel multiple bypass capacitors to rejectdifferent frequencies of noise. A 0.1 µF and a 1 µF are commonly used in parallel. The bypass capacitor must beinstalled as close to the power pin as possible for best results.
11 Layout
11.1 Layout GuidelinesWhen using multiple bit logic devices inputs must never float.
In many cases, functions or parts of functions of digital logic devices are unused, for example, when only twoinputs of a triple-input and gate are used or only 3 of the 4 buffer gates are used. Such input pins must not be leftunconnected because the undefined voltages at the outside connections result in undefined operational states.Figure 5 specifies the rules that must be observed under all circumstances. All unused inputs of digital logicdevices must be connected to a high or low bias to prevent them from floating. The logic level that must beapplied to any particular unused input depends on the function of the device. Generally they are tied to GND orVCC, whichever makes more sense or is more convenient. It is generally acceptable to float outputs, unless thepart is a transceiver.
12.1.1 Related DocumentationFor related documentation see the following:
Implications of Slow or Floating CMOS Inputs (SCBA004)
12.2 Related LinksThe table below lists quick access links. Categories include technical documents, support and communityresources, tools and software, and quick access to sample or buy.
Table 2. Related Links
PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICALDOCUMENTS
TOOLS &SOFTWARE
SUPPORT &COMMUNITY
SN54HC00 Click here Click here Click here Click here Click hereSN74HC00 Click here Click here Click here Click here Click here
12.3 Receiving Notification of Documentation UpdatesTo receive notification of documentation updates, navigate to the device product folder on ti.com. In the upperright corner, click on Alert me to register and receive a weekly digest of any product information that haschanged. For change details, review the revision history included in any revised document.
12.4 Community ResourcesThe following links connect to TI community resources. Linked contents are provided "AS IS" by the respectivecontributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms ofUse.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaborationamong engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and helpsolve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools andcontact information for technical support.
12.5 TrademarksE2E is a trademark of Texas Instruments.All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge CautionThese devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.
12.7 GlossarySLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable InformationThe following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and revision ofthis document. For browser-based versions of this data sheet, refer to the left-hand navigation.
(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substancedo not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI mayreference these types of products as "Pb-Free".RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide basedflame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to twolines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54HC00, SN54HC00-SP, SN74HC00 :
CDIP - 5.08 mm max heightJ0014ACERAMIC DUAL IN LINE PACKAGE
4214771/A 05/2017
NOTES: 1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M.2. This drawing is subject to change without notice. 3. This package is hermitically sealed with a ceramic lid using glass frit.4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only.5. Falls within MIL-STD-1835 and GDIP1-T14.
7 8
141
PIN 1 ID(OPTIONAL)
SCALE 0.900
SEATING PLANE
.010 [0.25] C A B
www.ti.com
EXAMPLE BOARD LAYOUT
ALL AROUND[0.05]
MAX.002
.002 MAX[0.05]ALL AROUND
SOLDER MASKOPENING
METAL
(.063)[1.6]
(R.002 ) TYP[0.05]
14X ( .039)[1]
( .063)[1.6]
12X (.100 )[2.54]
(.300 ) TYP[7.62]
CDIP - 5.08 mm max heightJ0014ACERAMIC DUAL IN LINE PACKAGE
4214771/A 05/2017
LAND PATTERN EXAMPLENON-SOLDER MASK DEFINED
SCALE: 5X
SEE DETAIL A SEE DETAIL B
SYMM
SYMM
1
7 8
14
DETAIL ASCALE: 15X
SOLDER MASKOPENING
METAL
DETAIL B13X, SCALE: 15X
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE
4040065 /E 12/01
28 PINS SHOWN
Gage Plane
8,207,40
0,550,95
0,25
38
12,90
12,30
28
10,50
24
8,50
Seating Plane
9,907,90
30
10,50
9,90
0,38
5,605,00
15
0,22
14
A
28
1
2016
6,506,50
14
0,05 MIN
5,905,90
DIM
A MAX
A MIN
PINS **
2,00 MAX
6,90
7,50
0,65 M0,15
0°–�8°
0,10
0,090,25
NOTES: A. All linear dimensions are in millimeters.B. This drawing is subject to change without notice.C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.D. Falls within JEDEC MO-150
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS.These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources.TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products.