SN74CBT3244 Octal FET Bus Switch (Rev. O) - TI.com · 1OE 1A1 1A4 1B1 1B4 2 8 1 18 12 2OE 2A1 2A4 2B1 2B4 11 17 19 9 3 SN74CBT3244 (Each 4-Bit Bus Switch) SN74CBT3244

1OE

1A1

1A4

1B1

1B4

2

8

1

18

12

2OE

2A1

2A4

2B1

2B4

11

17

19

9

3

Product

Folder

Sample &Buy

Technical

Documents

Tools &

Software

Support &Community

SN74CBT3244SCDS001O –NOVEMBER 1992–REVISED SEPTEMBER 2015

SN74CBT3244 Octal FET Bus Switch1 Features 3 Description

The SN74CBT3244 device provides eight bits of high-1• High-Bandwidth Data Path (Up to 200 MHz)

speed TTL-compatible bus switching. The SOIC,• Control Inputs Can Be Driven by TTL or 5-V/3.3-V SSOP, TSSOP, and TVSOP packages provide aCMOS Outputs standard ’244 device pinout. The low ON-state

• Low and Flat ON-State Resistance (ron) resistance of the switch allows connections to bemade with minimal propagation delay. The device isCharacteristics Over Operating Rangeorganized as two 4-bit low-impedance switches with(ron= 5 Ω Typical)separate output-enable (OE) inputs.• Bidirectional Data Flow With Near-Zero

Propagation Delay Device Information(1)

• Low Input/Output Capacitance Minimizes Loading PART NUMBER PACKAGE BODY SIZE (NOM)and Signal Distortion

SN74CBT3244RGY VQFN (20) 3.35 mm x 4.35 mm(Cio(OFF) = 6 pF Typical)SN74CBT3244DW SOIC (20) 9.97 mm x 12.60 mm

• Low Power Consumption (ICC = 50 µA Maximum)SN74CBT3244DB SSOP (20) 5.80 mm x 8.55 mm

• VCC Operating Range From 4.5 V to 5 V SN74CBT3244DBQ SSOP (20) 8.65 mm × 3.90 mm• Data I/Os Support 0- to 5-V Signaling Levels (0.8 SN74CBT3244PW TSSOP (20) 5.00 mm × 4.40 mm

V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V, 5 V)(1) For all available packages, see the orderable addendum at

• Standard ’244-Type Pinout the end of the data sheet.

2 Applications• Multi-Processor Communications• Test and Measurement Systems• Factory Automation Control Boards• Building Automation Control Boards

Simplified Schematic

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,intellectual property matters and other important disclaimers. PRODUCTION DATA.

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SN74CBT3244SCDS001O –NOVEMBER 1992–REVISED SEPTEMBER 2015 www.ti.com

Table of Contents8.3 Feature Description................................................... 71 Features .................................................................. 18.4 Device Functional Modes.......................................... 72 Applications ........................................................... 1

9 Application and Implementation .......................... 83 Description ............................................................. 19.1 Application Information.............................................. 84 Revision History..................................................... 29.2 Typical Application ................................................... 85 Pin Configuration and Functions ......................... 3

10 Power Supply Recommendations ....................... 96 Specifications......................................................... 411 Layout................................................................... 106.1 Absolute Maximum Ratings ...................................... 4

11.1 Layout Guidelines ................................................. 106.2 ESD Ratings.............................................................. 411.2 Layout Example .................................................... 106.3 Recommended Operating Conditions....................... 4

12 Device and Documentation Support ................. 116.4 Thermal Information Package................................... 412.1 Documentation Support ........................................ 116.5 Electrical Characteristics........................................... 512.2 Community Resources.......................................... 116.6 Switching Characteristics .......................................... 512.3 Trademarks ........................................................... 116.7 Typical Characteristics .............................................. 512.4 Electrostatic Discharge Caution............................ 117 Parameter Measurement Information .................. 612.5 Glossary ................................................................ 118 Detailed Description .............................................. 7

13 Mechanical, Packaging, and Orderable8.1 Overview ................................................................... 7Information ........................................................... 118.2 Functional Block Diagram ......................................... 7

4 Revision History

Changes from Revision N (September 2003) to Revision O Page

• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device FunctionalModes, Application and Implementation section, Power Supply Recommendations section, Layout section, Deviceand Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1

2 Submit Documentation Feedback Copyright © 1992–2015, Texas Instruments Incorporated

Product Folder Links: SN74CBT3244


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1 20

10 11

2

3

4

5

6

7

8

9

19

18

17

16

15

14

13

12

2OE

1B1

2A4

1B2

2A3

1B3

2A2

1B4

1A1

2B4

1A2

2B3

1A3

2B2

1A4

2B1

2A

1V

GN

D

CC

1O

E

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

1OE

1A1

2B4

1A2

2B3

1A3

2B2

1A4

2B1

GND

VCC

2OE

1B1

2A4

1B2

2A3

1B3

2A2

1B4

2A1

SN74CBT3244www.ti.com SCDS001O –NOVEMBER 1992–REVISED SEPTEMBER 2015

5 Pin Configuration and FunctionsRGY Package20-Pin VQFNDB, DBQ, DGV, or PW Package

Top View20-Pin SSOP, TVSOP, or TSSOPTop View

Pin FunctionsPIN

I/O DESCRIPTIONDB, DBQ, DGV, PW, SSOP,NAME TVSOP,TSSOP, VQFN

1A1 2 I/O Transceiver I/O pin








1B1 18 I/O Transceiver I/O pin








1OE 1 I Output Enable. When high A and B are disconnected, when Low A and B are connected

2OE 19 I Output Enable. When high A and B are disconnected, when Low A and B are connected

GND 10 — Ground

VCC 20 — Power pin

Copyright © 1992–2015, Texas Instruments Incorporated Submit Documentation Feedback 3



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6 Specifications

6.1 Absolute Maximum Ratingsover operating free-air temperature range (unless otherwise noted) (1)

MIN MAX UNITSupply voltage, VCC –0.5 7 VInput voltage, VI

(2) –0.5 7 VContinuous channel current 128 mAClamp current, IK (VI/O < 0) –50 mAStorage temperature, Tstg –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratingsonly, which do not imply functional operation of the device at these or any other conditions beyond those indicated under RecommendedOperating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

6.2 ESD RatingsVALUE UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±1500V(ESD) Electrostatic discharge VCharged-device model (CDM), per JEDEC specification JESD22- ±500C101 (2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditionsover operating free-air temperature range (unless otherwise noted) (1)

MIN MAX UNITVCC Supply voltage 4.5 5.5 VVIH High-level control input voltage 2 VVIL Low-level control input voltage 0.8 VTA Operating free-air temperature –40 85 °C

(1) All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,Implications of Slow or Floating CMOS Inputs, SCBA004.

6.4 Thermal Information PackageSN74CBT3244

DB DBQ DGV PW RGYTHERMAL METRIC (1) (2) UNIT(SSOP) (SSOP) (TVSOP) (TSSOP) (VQFN)20 PINS 20 PINS 20 PINS 20 PINS 20 PINS

RθJA Junction-to-ambient thermal resistance 70 68 92 83 37 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics applicationreport, SPRA953.

(2) The package thermal impedance is calculated in accordance with JESD 51-7.




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Temperature (qC)

I CC (P

A)

-45 -30 -15 0 15 30 45 60 75 900.07

0.075

0.08

0.085

0.09

0.095

0.1

D001


6.5 Electrical Characteristicsover operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNITVIK VCC = 4.5 V II = –18 mA –1.2 VII VCC = 5.5 V VI = 5.5 V or GND ±5 µAICC VCC = 5.5 V IO = 0, VI = VCC or GND 50 µA

Other inputs atΔICC(2) Control inputs VCC = 5.5 V One input at 3.4 V, 3.5 mAVCC or GND

Ci Control inputs VI = 3 V or 0 3 pFCio(OFF) VO = 3 V or 0 OE = VCC 6 pF

II = 64 mA 5 7VI = 0 V

ron(3) VCC = 4.5 V II = 30 mA 5 7 Ω

VI = 2.4 V II = 15 mA 10 15

(1) All typical values are at VCC = 5 V, TA = 25°C.(2) This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.(3) Measured by the voltage drop between the A and the B terminals at the indicated current through the switch. On-state resistance is

determined by the lowest voltage of the two (A or B) terminals.

6.6 Switching Characteristicsover operating free-air temperature range (unless otherwise noted)

PARAMETER FROM (INPUT) TO (OUTPUT) MIN TYP MAX UNITtpd

(1) A or B B or A 0.25 nsten OE A or B 1 8.9 nstdis OE A or B 1 7.4 ns

(1) This propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified loadcapacitance, when driven by an ideal voltage source (zero output impedance).

6.7 Typical Characteristics

Note device variation mentioned in Electrical Characteristics

Figure 1. ICC variation With Temperature




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VOH

VOL

From Output

Under Test

CL = 50 pF

(see Note A)

LOAD CIRCUIT

S17 V

Open

GND

500 Ω

500 Ω

tPLH tPHL

Output

Control

Output

Waveform 1

S1 at 7 V

(see Note B)

Output

Waveform 2

S1 at Open

(see Note B)

tPZL

tPZH

tPLZ

tPHZ

3 V

0 V

VOH

VOL

0 V

VOL + 0.3 V

VOH − 0.3 V

0 V

Input

3 V

3.5 V

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

Output

tpd

tPLZ/tPZL

tPHZ/tPZH

Open

7 V

Open

TEST S1

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR≤ 10 MHz, ZO = 50 Ω, tr ≤2.5 ns, tf ≤2.5 ns.

D. The outputs are measured one at a time with one transition per measurement.

E. tPLZ and tPHZ are the same as tdis.

F. tPZL and tPZH are the same as ten.

G. tPLH and tPHL are the same as tpd.

H. All parameters and waveforms are not applicable to all devices.

1.5 V 1.5 V

1.5 V 1.5 V

1.5 V 1.5 V

1.5 V

1.5 V


7 Parameter Measurement Information

Figure 2. Load Circuit and Voltage Waveforms




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1OE

1A1

1A4

1B1

1B4

2

8

1

18

12

2OE

2A1

2A4

2B1

2B4

11

17

19

9

3


8 Detailed Description

8.1 OverviewThe SN74CBT3244 has eight bits of high-speed TTL-compatible bus switching. The switches are grouped in the2 groups of 4 bits each. Each group has output-enabled inputs to allow signals to pass between A and B ports.The signals can travel from A port to B port or vice versa.

The low ON-state resistance of the switch allows connections to be made with minimal propagation delay. Thedevice is ideal for switching high speed digital signals between microprocessors and peripheral devices which isuseful in test applications, measurement applications, and control boards for factory automation.

8.2 Functional Block Diagram

Figure 3. Simplified Schematic

8.3 Feature DescriptionThe SN74CBT3244 device support same pin configuration as industry standard '244. This device has a nearzero propagation delay allowing high speed signal switching up to 200 Mhz. The signals see lower distortionsince the device has low ON-resistance (5 Ω) coupled with low-output capacitance (6 pF) . SN74CBT3244 has avery low power consumption in idle state consuming ICC of 50 µA only allowing power-saving for the system. Thedevice supports signal inputs any where between 0 V to 5 V.

8.4 Device Functional ModesThe device is organized as two 4-bit low-impedance switches with separate output-enable (OE) inputs.TheOutput Enable OE is active low, implying when low A port is connected to B port. This switch is bidirectional innature. Asserting OE high will disconnect A port from B port. To ensure the high-impedance state during powerup or power down, OE should be tied to VCC through a pullup resistor. The minimum value of the resistor isdetermined by the current-sinking capability of the driver.

Table 1. Function Table(Each 4-Bit Bus Switch)INPUT OE FUNCTION

L A port = B portH Disconnect




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3

12

18

8

11

2

Bus Controller

ron

ron

11OE

1A1

1A4

8

1A2 1A3

Device

8

ron

ron

19

17

2OE

2A1

2A4

2A2 2A3

1B1

1B4

1B2 1B3

2B1

2B4

9

2B2 2B3

2010 0.1uFVCC Gnd


9 Application and Implementation

NOTEInformation in the following applications sections is not part of the TI componentspecification, and TI does not warrant its accuracy or completeness. TI’s customers areresponsible for determining suitability of components for their purposes. Customers shouldvalidate and test their design implementation to confirm system functionality.

9.1 Application InformationThe SN74CBT3244 device can be used to control up to 4 bits with 2 channels simultaneously. The applicationshown in Figure 4 is a 8-bit bus being controlled. The OE pins are used to control the chip from the buscontroller. This is a generic example and can apply to many situations. If an application requires fewer than 8bits, ensure that the A side is tied either high or low on unused channels.

9.2 Typical Application

Figure 4. Typical Application

9.2.1 Design RequirementsA 0.1-µF bypass capacitor should be placed between each VCC pin and GND. Each capacitor should be placedas close as possible to the SN74CBT3244 device.

9.2.2 Detailed Design Procedure1. Recommended input conditions:

– For specified high and low levels, see VIH and VIL in Electrical Characteristics– Inputs and outputs are overvoltage tolerant, which allows them to go as high as 5.5 V at any valid VCC

2. Recommended output conditions:– Load currents must not exceed ±64 mA per channel

3. Frequency selection criterion:– Added trace resistance or capacitance can reduce maximum frequency capability; use layout practices as

directed in Layout Guidelines




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Temperature (qC)

ON

-Res

ista

nce

(RO

N)

-45 -30 -15 0 15 30 45 60 75 900

2

4

6

8

10

12

14

D002

VI = 0VI = 2.4 V


Typical Application (continued)9.2.3 Application Curve

Figure 5. ON-Resistance (Ron) Variation vs Temperature(1) Note device variation mentioned in Electrical Characteristics

10 Power Supply RecommendationsThe power supply can be any voltage between the minimum and maximum supply voltage rating listed in theAbsolute Maximum Ratings table.

Each VCC terminal should have a good bypass capacitor to prevent power disturbance. For devices with a singlesupply, a 0.1-μF bypass capacitor is recommended. If multiple pins are labeled VCC, then a 0.01-μF or 0.022-μFcapacitor is recommended for each VCC because the VCC pins are tied together internally. For devices with dual-supply pins operating at different voltages, for example VCC and VDD, a 0.1-µF bypass capacitor is recommendedfor each supply pin. To reject different frequencies of noise, use multiple bypass capacitors in parallel. Capacitorswith values of 0.1 μF and 1 μF are commonly used in parallel. The bypass capacitor must be installed as close tothe power terminal as possible for best results.




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WORST BETTER BEST

1W min.

W

2W


11 Layout

11.1 Layout GuidelinesReflections and matching are closely related to the loop antenna theory but are different enough to be discussedseparately from the theory. When a PCB trace turns a corner at a 90° angle, a reflection can occur. A reflectionoccurs primarily because of the change of width of the trace. At the apex of the turn, the trace width increases to1.414 times the width. This increase upsets the transmission-line characteristics, especially the distributedcapacitance and self-inductance of the trace, which results in the reflection. Not all PCB traces can be straight;therefore, some traces must turn corners. Figure 6 shows progressively better techniques of rounding corners.Only the last example (BEST) maintains constant trace width and minimizes reflections.

11.2 Layout Example

Figure 6. Trace Example




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12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related DocumentationFor related documentation see the following:• Implications of Slow or Floating CMOS Inputs, SCBA004• Selecting the Right Texas Instruments Signal Switch, SZZA030

12.2 Community ResourcesThe following links connect to TI community resources. Linked contents are provided "AS IS" by the respectivecontributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms ofUse.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaborationamong engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and helpsolve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools andcontact information for technical support.

12.3 TrademarksE2E is a trademark of Texas Instruments.All other trademarks are the property of their respective owners.

12.4 Electrostatic Discharge CautionThese devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.

12.5 GlossarySLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable InformationThe following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and revision ofthis document. For browser-based versions of this data sheet, refer to the left-hand navigation.




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PACKAGE OPTION ADDENDUM

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Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status(1)

Package Type PackageDrawing

Pins PackageQty

Eco Plan(2)

Lead/Ball Finish(6)

MSL Peak Temp(3)

Op Temp (°C) Device Marking(4/5)

Samples

SN74CBT3244DBQR ACTIVE SSOP DBQ 20 2500 Green (RoHS& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR -40 to 85 CBT3244

SN74CBT3244DBR ACTIVE SSOP DB 20 2000 Green (RoHS& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM -40 to 85 CU244

SN74CBT3244DBRG4 ACTIVE SSOP DB 20 2000 Green (RoHS& no Sb/Br)


SN74CBT3244DGVR ACTIVE TVSOP DGV 20 2000 Green (RoHS& no Sb/Br)


SN74CBT3244DW ACTIVE SOIC DW 20 25 Green (RoHS& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM -40 to 85 CBT3244

SN74CBT3244DWR ACTIVE SOIC DW 20 2000 Green (RoHS& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM -40 to 85 CBT3244

SN74CBT3244PW ACTIVE TSSOP PW 20 70 Green (RoHS& no Sb/Br)


SN74CBT3244PWE4 ACTIVE TSSOP PW 20 70 Green (RoHS& no Sb/Br)


SN74CBT3244PWR ACTIVE TSSOP PW 20 2000 Green (RoHS& no Sb/Br)


SN74CBT3244PWRE4 ACTIVE TSSOP PW 20 2000 Green (RoHS& no Sb/Br)


SN74CBT3244PWRG4 ACTIVE TSSOP PW 20 2000 Green (RoHS& no Sb/Br)


SN74CBT3244RGYR ACTIVE VQFN RGY 20 3000 Green (RoHS& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR -40 to 85 CU244

(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availabilityinformation and additional product content details.TBD: The Pb-Free/Green conversion plan has not been defined.

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Addendum-Page 2

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement thatlead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used betweenthe die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weightin homogeneous material)

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finishvalue exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device PackageType

PackageDrawing

Pins SPQ ReelDiameter

(mm)

ReelWidth

W1 (mm)

A0(mm)

B0(mm)

K0(mm)

P1(mm)

W(mm)

Pin1Quadrant

SN74CBT3244DBQR SSOP DBQ 20 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1

SN74CBT3244DBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1

SN74CBT3244DGVR TVSOP DGV 20 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

SN74CBT3244DWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1

SN74CBT3244PWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1

SN74CBT3244RGYR VQFN RGY 20 3000 330.0 12.4 3.8 4.8 1.6 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

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Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

SN74CBT3244DBQR SSOP DBQ 20 2500 367.0 367.0 38.0

SN74CBT3244DBR SSOP DB 20 2000 367.0 367.0 38.0

SN74CBT3244DGVR TVSOP DGV 20 2000 367.0 367.0 35.0

SN74CBT3244DWR SOIC DW 20 2000 367.0 367.0 45.0

SN74CBT3244PWR TSSOP PW 20 2000 367.0 367.0 38.0

SN74CBT3244RGYR VQFN RGY 20 3000 367.0 367.0 35.0

PACKAGE MATERIALS INFORMATION

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Pack Materials-Page 2

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PACKAGE OUTLINE

C

TYP10.639.97

2.65 MAX

18X 1.27

20X 0.510.31

2X11.43

TYP0.330.10

0 - 80.30.1

0.25GAGE PLANE

1.270.40

A

NOTE 3

13.012.6

B 7.67.4

4220724/A 05/2016

SOIC - 2.65 mm max heightDW0020ASOIC

NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.5. Reference JEDEC registration MS-013.

120

0.25 C A B

1110

PIN 1 IDAREA

NOTE 4

SEATING PLANE

0.1 C

SEE DETAIL A

DETAIL ATYPICAL

SCALE 1.200

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EXAMPLE BOARD LAYOUT

(9.3)

0.07 MAXALL AROUND

0.07 MINALL AROUND

20X (2)

20X (0.6)

18X (1.27)

(R )TYP

0.05

4220724/A 05/2016


SYMM

SYMM

LAND PATTERN EXAMPLESCALE:6X

1

10 11

20

NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

METALSOLDER MASKOPENING

NON SOLDER MASKDEFINED

SOLDER MASK DETAILS

SOLDER MASKOPENING

METAL UNDERSOLDER MASK

SOLDER MASKDEFINED

www.ti.com

EXAMPLE STENCIL DESIGN

(9.3)

18X (1.27)

20X (0.6)

20X (2)

4220724/A 05/2016


NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design.

SYMM

SYMM

1

10 11

20

SOLDER PASTE EXAMPLEBASED ON 0.125 mm THICK STENCIL

SCALE:6X

MECHANICAL DATA

MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN

14

3,70

3,50 4,90

5,10

20DIM

PINS **

4073251/E 08/00

1,20 MAX

Seating Plane

0,050,15

0,25

0,500,75

0,230,13

1 12

24 13

4,304,50

0,16 NOM

Gage Plane

A

7,90

7,70

382416

4,90

5,103,70

3,50

A MAX

A MIN

6,606,20

11,20

11,40

56

9,60

9,80

48

0,08

M0,070,40

0°–8°

NOTES: A. All linear dimensions are in millimeters.B. This drawing is subject to change without notice.C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.D. Falls within JEDEC: 24/48 Pins – MO-153

14/16/20/56 Pins – MO-194

MECHANICAL DATA

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE

4040065 /E 12/01

28 PINS SHOWN

Gage Plane

8,207,40

0,550,95

0,25

38

12,90

12,30

28

10,50

24

8,50

Seating Plane

9,907,90

30

10,50

9,90

0,38

5,605,00

15

0,22

14

A

28

1

2016

6,506,50

14

0,05 MIN

5,905,90

DIM

A MAX

A MIN

PINS **

2,00 MAX

6,90

7,50

0,65 M0,15

0°–8°

0,10

0,090,25

NOTES: A. All linear dimensions are in millimeters.B. This drawing is subject to change without notice.C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.D. Falls within JEDEC MO-150

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http://www.ti.com/lit/slua271

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