[Type text] Page 1 DEPARTMENT OF COLLEGIATE AND TECHNICAL EDUCATION DEPARTMENT OF ELECTRONICS & COMMUNICATIONS ENGINEERING STUDY MATERIAL ON DIGITAL ELECTRONICS (15EC32T) UNIT 1: COMBINATIONAL LOGIC CIRCUITS Prepared by SMT. SAVITA NAIK LECTURER, E&CE DEPT GOVERNMENT POLYTECHNIC, RAICHUR-117 DIST:-RAICHUR-584101 2020-2021
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DEPARTMENT OF COLLEGIATE AND TECHNICAL
EDUCATION
DEPARTMENT OF ELECTRONICS & COMMUNICATIONS ENGINEERING
STUDY MATERIAL ON
DIGITAL ELECTRONICS
(15EC32T)
UNIT 1: COMBINATIONAL LOGIC CIRCUITS
Prepared by
SMT. SAVITA NAIK
LECTURER, E&CE DEPT
GOVERNMENT POLYTECHNIC, RAICHUR-117
DIST:-RAICHUR-584101
2020-2021
Digital Electronics (15EC32T)
DEPT ECE,GPT RAICHUR Page 2
CONTENTS
S.NO CHAPTERS
Page no.
01 COMBINATIONAL LOGIC CIRCUITS
1.1 COMBINATIONAL CIRCUITS
3
1.2 MULTIPLEXERS
3-4
1.3. 2-Input Multiplexer (2:1 Multiplexer)
4
1.4. Realization Of Gates Using 2:1 Multiplexer
5-6
1.5 Realization Of Gates Using 4:1 Multiplexer
6-7
1.6 Realization Of Higher –Order Multiplexer Using Lower-Order Multiplexer Ics.
8-11
1.7. Multiplexer ICS And Features.
11
1.8. Applications Of Multiplexers
12
1.9 Demultiplexer
13
1.20 . Realization Of 1:2 Demultiplexer.
14
1.21. Demultiplexer Ics
14
1.22 Applications Of Demultiplexers
15
1.23. Encoder
15
1.24 Decimal-To- BCD Encoder
16
1.25: Decimal- To – BCD Priority Encoder (4-Input Priority Encoder)
17-19
1.26 . Encoder Ics And Their Features.
19
1.27. Applications Of Encoder
20
1.28. Decoder
20-21
1.29: BCD-TO SEVEN SEGMENT DECODER
21-24
1.30 : Decoder Ics And Their Features
25-26
Digital Electronics (15EC32T)
DEPT ECE,GPT RAICHUR Page 3
UNIT: 1
COMBINATIONAL LOGIC CIRCUITS
1.1 Combinational circuits
Combinational switching circuits are those whose output levels at any instant of time are
dependent only on the level present at the inputs at that time .Any prior input level
conditions have no effect on the present outputs, because combinational logic circuits have
no memory. Examples are logic gates, adders, subtractors, comparators, encoders, decoders,
multiplexers and demultiplexers. A combinational circuits can have a n number of inputs
and m number of outputs as shown in fig:1 .
Fig:1 Combinational logic circuit.
1.2 MULTIPLEXERS
The term Multiplex means “many into one”. Multiplexing is the process of transmitting a
large number of information over a single line . A digital multiplexer is a combinational
circuit that select one digital information several sources and transmits the selected
information on a single output line. A multiplexer is also called a data sector. The
multiplexer has several data input lines and single output line. The routing of the desired
data input to the output is controlled by SELECT (control) inputs. The relation between
number of select lines and number of data inputs are 2m
= n .
2 to 1
MUX
4 to 1
MUX
Fig: 1.1 . Logic Symbol for multiplexer.
1.3. 2-Input Multiplexer (2:1 Multiplexer)
Fig: 1.3: 2-Input
Multiplexer
Fig.1.3 shows the logic symbol, logic circuit and functional table for a 2-input
multiplexer. The circuit consists of two AND gates G1 and G2, an OR gate G3 and a NOT gate
G4. I0 and I1 are the data inputs and S is the data select input . The logic level applied to the S
input enable one of the two And gates and allows data input to pass through the OR gate to the
output Y . Boolean expression for output Y is
Y= E(S‟I0 +SI1) --------- (1)
When S=0, gate G4 outputs a 1 to gate G1 and a 0 to gate G2 . Thus G1 is enabled and
G2 is disabled. Data from input line I0 goes to output line Y and from I1 is blocked .
Substituting S=0 in equation (1),
Y= 1(1.I0 +0.I1)
= I0 ----- (2)
This shows that output Y follows input I0.
When S=1, gate G4 outputs a 0 to gate G1 and a 1 to gate G2 . Thus G1 is disabled and G2 is
enabled. Data from input line I1 goes to output line Y and from I0 is blocked . Substituting S=0
in equation (1), AND gate G1 is disabled and G2 is enabled. Substituting S=1 in equation (1)
Y= 1(0.I0 +1.I1)
= I1 ----- (3)
This shows that output Y follows input I1.
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1.4. Realization of Gates using 2:1 Multiplexer
(a) Implementation of NOT gate using 2 : 1 Mux
We can analyze it Y = x’.1 + x.0 = x’ It is NOT Gate using 2:1 MUX. The implementation of NOT gate is done using “n” selection lines.
(b) Implementation of AND gate using 2 : 1 Mux
c) Implementation of OR gate using 2 : 1 Mux using “n-1” selection lines.
d) Implementation of NAND gate using 2 : 1 Mux
Implementation of NAND, NOR, XOR and XNOR gates requires two 2:1 Mux. First
multiplexer will act as NOT gate which will provide complemented input to the second
multiplexer.
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e) Implementation of NOR gate using 2 : 1 Mux
f) Implementation of EX-OR gate using 2 : 1 Mux
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g) Implementation of EX-NOR gate using 2 : 1 Mux
1.5 Realization of Gates using 4:1 Multiplexer
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Fig: 1.4 Implementation of gates using 4:1 mux.
1.6 Realization of higher –order multiplexer using Lower-order multiplexer Ics.
Now, let us implement the following two higher-order Multiplexers using lower-order
Multiplexers.
8x1 Multiplexer
16x1 Multiplexer
8x1 Multiplexer
In this section, let us implement 8x1 Multiplexer using 4x1 Multiplexers and 2x1
Multiplexer. We know that 4x1 Multiplexer has 4 data inputs, 2 selection lines and one
output. Whereas, 8x1 Multiplexer has 8 data inputs, 3 selection lines and one output.
So, we require two 4x1 Multiplexers in first stage in order to get the 8 data inputs.
Since, each 4x1 Multiplexer produces one output, we require a 2x1 Multiplexer in
second stage by considering the outputs of first stage as inputs and to produce the final
output.
Let the 8x1 Multiplexer has eight data inputs I7 to I0, three selection lines s2, s1 & s0 and
one output Y. The Truth table of 8x1 Multiplexer is shown below.
Selection Inputs Output
S2 S1 S0 Y
0 0 0 I0
0 0 1 I1
0 1 0 I2
0 1 1 I3
1 0 0 I4
1 0 1 I5
1 1 0 I6
1 1 1 I7
We can implement 8x1 Multiplexer using lower order Multiplexers easily by considering
the above Truth table. The block diagram of 8x1 Multiplexer is shown in the following
figure.
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Fig: 1.5 implement 8x1 Multiplexer using 4x1 Multiplexers and 2x1 mux
The same selection lines, s1 & s0 are applied to both 4x1 Multiplexers. The data
inputs of upper 4x1 Multiplexer are I7 to I4 and the data inputs of lower 4x1 Multiplexer are I3 to
I0. Therefore, each 4x1 Multiplexer produces an output based on the values of selection lines, s1 &
s0. The outputs of first stage 4x1 Multiplexers are applied as inputs of 2x1 Multiplexer that is
present in second stage. The other selection line, s2 is applied to 2x1 Multiplexer.
If s2 is zero, then the output of 2x1 Multiplexer will be one of the 4 inputs I3 to I0 based
on the values of selection lines s1 & s0.
If s2 is one, then the output of 2x1 Multiplexer will be one of the 4 inputs I7 to I4 based
on the values of selection lines s1 & s0.
Therefore, the overall combination of two 4x1 Multiplexers and one 2x1 Multiplexer performs
as one 8x1 Multiplexer.
1.7 16x1 Multiplexer
In this section, let us implement 16x1 Multiplexer using 8x1 Multiplexers and 2x1
Multiplexer. We know that 8x1 Multiplexer has 8 data inputs, 3 selection lines and one output.
Whereas, 16x1 Multiplexer has 16 data inputs, 4 selection lines and one output. So, we require
two 8x1 Multiplexers in first stage in order to get the 16 data inputs. Since, each 8x1
Multiplexer produces one output, we require a 2x1 Multiplexer in second stage by considering
the outputs of first stage as inputs and to produce the final output. Let the 16x1 Multiplexer has
sixteen data inputs I15 to I0, four selection lines s3 to s0 and one output Y. The Truth table of
16x1 Multiplexer is shown below.
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Selection Inputs
Output
S3 S2 S1 S0 Y
0 0 0 0 I0
0 0 0 1 I1
0 0 1 0 I2
0 0 1 1 I3
0 1 0 0 I4
0 1 0 1 I5
0 1 1 0 I6
0 1 1 1 I7
1 0 0 0 I8
1 0 0 1 I9
1 0 1 0 I10
1 0 1 1 I11
1 1 0 0 I12
1 1 0 1 I13
1 1 1 0 I14
1 1 1 1 I15
We can implement 16x1 Multiplexer using lower order Multiplexers easily by
considering the above Truth table. The block diagram of 16x1 Multiplexer is shown in the
following figure.
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Fig: 1.6
implement 16x1 Multiplexer using 8x1 Multiplexers and 2x1.
1.7. Multiplexer ICS and features.
Multiplexers are available as MSI- IC format. The table indicates Multiplexer IC
numbers for TTL logic family.CMOS Multiplexer ICs are also popular amongst the Digital
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system designer because of low power consumption. Below table indicates list of few CMOS
multiplexer ICs.
1.8. Applications of multiplexers
Multiplexer or data selectors are combinational circuits which transfer data from many
sources to output under the control of data select lines. Multiplexer has many applications right
from data routing, time division multiplexing, function generator to parallel to serial converter
etc. A single multiplexer can replace several logic gates ICs, saving PCB area, interconnections,
design efforts and cost. A list of popular applications is given below.
1. Data routing
2. Data bussing
3. Switch setting comparator
4. Multiplexer as a function generator
5. Parallel to serial converter
6. Cable TV signal distribution
7. Telephone network
8. Sharing printer /resources
1.9 Demultiplexer
Demultiplexer has a single input and n output lines. Demultiplexer can be visualized as
reverse multi-position switch. The select lines permit input data from single line to be switched
to any one of the many output lines as shown in fig.
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Fig: 1.7 . Multi-position switch as Demultiplexer
Demultiplex means one into many. A demultiplexer reverses the multiplexing operation.
In other words, the demultiplexer takes one data input source and selectively distributes it to 1 of
N output channels just like multi-position switch. It also has „m’ select lines for selecting the
desired output for the input data as shown in fig. 1.8 .The mathematical relation between select
lines and „n’ output are: 2m
= n
Figure 1.8: Logic symbol of basic demultiplexer
As a demultiplexer takes data from one input line and distributes over a 2m output line,
hence it is often referred to as 1 to 2m line converter. There are four basic types
demultiplexers: 1 to 2 demultiplexer, 1 to 4 demultiplexer, 1 to 8 demultiplexer and 1 to 16
demultiplexer .
1.20 . Realization of 1:2 Demultiplexer.
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Fig:1.9 - 1:2 Demultipexer
Fig 1.9 (a),(b),(c) and (d) shows the logic symbol, function table ,logic diagram and
Boolean expression respectively,for 1:2 demultiplexer. The input data bit is labelled D . The
input data line is connected to both AND gates . The select line S enables only one gate at a
time. The data D will pass through the enabled gate to the output line. When S=0 the upper And
gate is enabled while the lower and gate is disabled. Therefore data bit D is transmitted only to
the Y0 output, giving Y0=D . If D is low ,Y0 is low . If D is high, Y0 is high . The value of Y0
depends on value of D . The other output Y1 is low state . If control input is changed to S=1, the
lower AND gate is enabled while the upper AND gate is disabled. Then D is transmitted only to
the Y1 output and Y1=D. The Boolean expressions for the output as follows:
Y0=S‟D
Y1=SD
1.21. Demultiplexer ICs
So far we have discussed construction of demultiplexers using discreet logic gates.
Commercially,demultiplexers are available as MSI- IC format. Below indicates a table of
demultiplexer IC numbers for TTL logic family.
CMOS ICs provide a combination of Multiplexer and Demultiplexer in a single chip IC.
These are also popular amongst the Digital system designer because of low power consumption.
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1.22 Applications of Demultiplexers
Digital demultiplexers are combinational devices controlled by a selector address that
routes input data to one of many outputs of the demultiplexers. These can be used in following
applications.
1. Data demultiplexing
2. Clock demultiplexing
3. Memory addressing
4. Four phase clock generator
5. Function generation using DMUX
6. Switch encoding
7. Serial to parallel converter
1.23. ENCODER
The process of converting from human readable code to machine readable code i.e.
binary is known as encoding. An encoder is a combinational circuit that coverts more familiar
numbers, symbols or character into binary code. An encoder has a number of input lines but only
one of them is activated at a time representing a digit or character and produces a binary code
depending on which input is activated. Figure 1.20 is the logic symbol of encoder with „m‟
inputs and „n‟ outputs. In short, it is multiple inputs and multiple outputs device with proper
conversion system. Note that encoder performs the reverse operation of the decoder. An encoder
has „m‟ number of input lines and „n‟ number of output lines. The numbers of outputs (n) are
always less than number of inputs (m). Some of the most commonly used encoders are – (1)
Linear encoders are octal to binary, Decimal to BCD and Hexadecimal to binary where normal
encoding is implemented and (2) Priority encoders.
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1.24 Decimal-To- BCD Encoder
A decimal to BCD (binary coded decimal) encoder is also known as 10-line to 4-line
encoder. It accepts 10- inputs and produces a 4-bit output corresponding to the activated decimal
input. Figure-1.21 shows the logic symbol of decimal to BCD encoder.
Fig: 1.21: logic symbol of decimal to BCD encoder
The truth table of Decimal to BCD encoder is shown in below Table . There are ten