SMT Attack: Next Generation Attack on Obfuscated Circuits with Capabilities and Performance Beyond the SAT Attacks Conference on Cryptographic Hardware and Embedded Systems 2019 ( CHES 2019) Kimia Zamiri Azar, Hadi Mardani Kamali, Houman Homayoun, and Avesta Sasan Department of Electrical and Computer Engineering George Mason University, USA.
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SMT Attack: Next Generation Attack on
Obfuscated Circuits with Capabilities and
Performance Beyond the SAT Attacks
Conference on Cryptographic Hardware and Embedded Systems 2019 (CHES 2019)
Kimia Zamiri Azar, Hadi Mardani Kamali,
Houman Homayoun, and Avesta Sasan
Department of Electrical and Computer Engineering
George Mason University, USA.
Outline
Intro to Hardware Security
Intro to Logic Locking
SAT Attack and its Limitations
SMT attack
SMT reduced to SAT Attack
Eager SMT Attack
Lazy SMT Attack
Accelerated Lazy SMT Attack
Experimental Results
Conclusion
2
Design Flow
High Cost of Manufacturing in ASIC Design has pushed most of needed
fabrication offshore
Some Fabs are untrusted
Security threats for untrusted supply chain
Trojan Insertion
Overproduction
Intellectual Property (IP) Theft
Counterfeiting
Reverse Engineering, etc.
3
In-house
Design
Teams
Integration
Team
IP Vendor 1
IP Vendor 2
RT
L
Net
list
Des
ign
Inte
gra
tion
RT
L V
erif
icat
ion
Log
ic S
ynth
esis
Gat
e-L
evel
Net
list
Ph
ysic
al S
ynth
esis
Lay
out
Ver
ific
atio
n
Lay
ou
t
(GD
SII
)
Design Synthesis & Verification Fabrication Testing Packing System Integration
Waf
er
Tes
t
Sys
tem
Recycle/Repackage
for Outdated
Pac
kag
e &
Ass
embly
PC
B A
ssem
bly
SoC Design Flow System Design
Logic Locking Logic Locking: Adding Ambiguity to the Design
Inserting Key Programmable Gates (KPGs)
No Information on Key at Untrusted Entities
4
Circuit
x1
x2
x3
xn
Y = f(x1, x2, …, xn)
x4
EPIC (2008)
Random
Insertion
Policy
(RLL)
Original Netlist
Logic Locking
x1
x2
x3
xn
Yn = f(x1, x2, …, xn, k1, k2)
x4
k1
k2
SAT Attack: a Turning Point in Logic Locking
SAT Attack Recipe:
1. Reverse-engineered netlist (CL)
2. A functionally activated chip (CO)
SAT attack broke all logic obfuscation scheme prior to its debut!
Input model model which is understood by that theory solver
Different translation step for each theory solver
Bit-vectors Arrays Equality Graph...
Theory-n extraction
...Theory-2
extraction
Translationmodule
Obfuscated netlist Circuit extraction
Graph extraction
SAT solver
Update TLC
Update SMTLC
Update SATCC + LLK
Quantifier-free SMT solver
SMT solver
SAT/UNSAT
Graph solver
Theory solvers
SMT Attack
18
Invoking the SMT solver returns
A satisfiable assignment
list of learned theory
conflict clauses
Bit-vectors Arrays Equality Graph...
Theory-n extraction
...Theory-2
extraction
Translationmodule
Obfuscated netlist Circuit extraction
Graph extraction
SAT solver
Update TLC
Update SMTLC
Update SATCC + LLK
Quantifier-free SMT solver
SMT solver
SAT/UNSAT
Graph solver
Theory solvers
Attack Modes
19
Mode 1: SMT reduced to SAT Attack
To show SMT is a superset of SAT
Mode 2: Eager SMT Attack
To show the Strength of SMT
Theory solver(s) and SAT solver are Serialized!
Mode 3: Lazy SMT Attack
To show the Strength of SMT
Theory solver(s) and SAT solver are Parallelized!
Mode 4: Accelerated Lazy SMT Attack (AccSMT)
To show more efficiency
Uses BitVector Theory Solver
Attack Modes
20
Mode 1: SMT reduced to SAT Attack
To show SMT is a superset of SAT
Mode 2: Eager SMT Attack
To show the Strength of SMT
Theory solver(s) and SAT solver are Serialized!
Mode 3: Lazy SMT Attack
To show the Strength of SMT
Theory solver(s) and SAT solver are Parallelized!
Mode 4: Accelerated Lazy SMT Attack (AccSMT)
To show more efficiency
Uses BitVector Theory Solver
Mode 1: SMT reduced to SAT Attack
21
SMT solver is a superset of SAT solver
Any attack formulated for SAT can be formulated using SMT
one-to-one translation of the original SAT attack
The recently found Conflict Clauses (CC) are added to the set of
previously found Learned Clauses (LC).
Note that this step is done implicitly if SMT is stateful.
Mode 1: SMT reduced to SAT Attack
22
Attack Modes
23
Mode 1: SMT reduced to SAT Attack
To show SMT is a superset of SAT
Mode 2: Eager SMT Attack
To show the Strength of SMT
Theory solver(s) and SAT solver are Serialized!
Mode 3: Lazy SMT Attack
To show the Strength of SMT
Theory solver(s) and SAT solver are Parallelized!
Mode 4: Accelerated Lazy SMT Attack (AccSMT)
To show more efficiency
Uses BitVector Theory Solver
Case Study
24
Case Study: Delay and Logic Locking (DLL) *1
*1 Y. Xie and A. Srivastava, “Delay Locking: Security Enhancement of Logic Locking against IC Counterfeiting and Overproduction,” In Proceedings of the 54th Annual Design Automation Conference (DAC’17), 2017.
yk1
x
k2
C
Tunable Delay Buffer (TDB)
TDK
i1
i2i3
i4K0 K1
g1 g2
g3
g4
y
K2 K3
TDK
i4
i2i3
K0
K1 K3
i1 y
K2
i1
i2
i3
i4
yg1 g2K1 = 0
K1 = 1 g3 g4
Case Study
25
Case Study: Delay and Logic Locking (DLL) *1
K1 and K3
No impact on the logical behavior of the circuit
Only changes its delay
SAT attack results
Random assignment to K1 and K3
*1 Y. Xie and A. Srivastava, “Delay Locking: Security Enhancement of Logic Locking against IC Counterfeiting and Overproduction,” In Proceedings of the 54th Annual Design Automation Conference (DAC’17), 2017.
i4
i2i3
K0
K1 K3
i1 y
K2
i1
i2
i3
i4
yg1 g2K1 = 0
K1 = 1 g3 g4
Mode 2: Eager SMT Attack
26
µ
Theory
SAT Solver
µ*
SAT/UNSAT
Mode 2: Eager SMT Attack
27
Calculating Hold Time and Setup Time
Common
Launch
Capture
Data
tcs-lrtpd
tsetu
p
tcs-cr
tcq
Mode 2: Eager SMT Attack
28
Calculating Hold Time and Setup Time
Common
Launch
Capture
Data
tcs-lrtpd
tsetu
p
tcs-cr
tcq
Mode 2: Eager SMT Attack
29
Mode 2: Eager SMT Attack
30
Limitation of Eager SMT Attack
For some problems the Eager approach does not work!
Why? Eager relies on reduction of a problem to a SAT problem
SRCLock
# of cycles is exponential w.r.t. the # of inserted feedbacks
The run time of pre-processing is exponential
w.r.t. the # of inserted feedbacks
Preventing us to ever reach the SAT attack
31
Attack Modes
32
Mode 1: SMT reduced to SAT Attack
To show SMT is a superset of SAT
Mode 2: Eager SMT Attack
To show the Strength of SMT
Theory solver(s) and SAT solver are Serialized!
Mode 3: Lazy SMT Attack
To show the Strength of SMT
Theory solver(s) and SAT solver are Parallelized!
Mode 4: Accelerated Lazy SMT Attack (AccSMT)
To show more efficiency
Uses BitVector Theory Solver
Mode 3: Lazy SMT Attack
Lazy approach of SMT attack
Moves from pre-processing to co-processing
33
µ
Theory SAT Solver
SAT/UNSAT
Mode 3: Lazy SMT Attack
34
The big difference between
Eager and Lazy approach:
After model generation for
Theory solver the SMT solve
function is not called.
The theory model is defined
but is not solved.
Mode 3: Lazy SMT Attack
35
The SMT solve function is
then called to find the
assignment for keys which
can satisfy both SAT solver
and Theory solver(s).
Mode 3: Lazy SMT Attack
36
The decision tree and search
Space for the SMT solver is
Significantly Reduced.
Attack Modes
37
Mode 1: SMT reduced to SAT Attack
To show SMT is a superset of SAT
Mode 2: Eager SMT Attack
To show the Strength of SMT
Theory solver(s) and SAT solver are Serialized!
Mode 3: Lazy SMT Attack
To show the Strength of SMT
Theory solver(s) and SAT solver are Parallelized!
Mode 4: Accelerated Lazy SMT Attack (AccSMT)
To show more efficiency
Uses BitVector Theory Solver
38
DIPs are Important
Number of DIPs = Number of Iterations
Categorizing DIPs based on their Pruning Power
Stronger DIP rule outs more incorrect keys
Based on the number of inconsistencies that could sensitize to the