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• Register for the course - sign list• From the list I will generate an email alias, [email protected],
where I will post various information. Note that You are encouraged to use the mail alias if you find bugs in labs, have questions etc.
• Write down your user name at sm! If you don’t you will not get any extra qouta!
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Course goalsCourse goals
• Give the student an understanding of functionally complex digital systems
• Give the student a fundamental competence in methods for designand implementation of digital systems
• Familiarize the student with synchronous digital design
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Course contentsCourse contents
• A few (10) lectures focusing on:
– Design alternatives
– Register Transfer Level (RTL) design with VHDL– Synchronous design
– Design methodologies
– FPGA implementations
– CMOS technology
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Course examinationCourse examination
• 4 “point” course, labs 2 points and exam is worth 2 points
• Grade determined by results on exam
• Some material covered in lectures is not available in the text book, but will be in the final exam.
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Teaching...Teaching...
• There are few lectures and you are supposed to pick up most of the material while working with the labs
• When you have questions you are encouraged to contact me personally or by email. You may also use the mail alias
• Investigate alternate data sources other than me and the textbook
• I plan to put as much material as possible on the course web pages
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Required text bookRequired text book
• Digital System Design with VHDL, Mark Zwolinsky, 2000
• Start reading chapters 1- 3• Your old book from “Digitalteknik”
might be useful as well• Most of the material for todays
lecture can be found in the paper “ASIC Design”, S. Gupta and R. K. Gupta. Make sure you get a copy of the paper!
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LabsLabs
• Software available on Solaris machines. 30 licenses of NC VHDL, 15 licenses of Synplify and unlimited (?) licenses available for Xilinx. Let me know if you experience any problems with the licenses
• Hardware available in A1502. Detail about this next lecture
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Hardware Hardware -- XSV100 boardsXSV100 boards
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Hardware Hardware -- XSV100 boardsXSV100 boards
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LabsLabs
• Lab 1 Tutorial November 6
• Lab 2 ALU design November 13
• Lab 3.1 PS/2 keyboard interfacing November 21
• Lab 3.2 RS232 serial port interfacing November 27
• Lab 3.3 Ethernet PHY interfacing December 11
In all labs, except lab 2, the XSV board will be usedYou will have one week to complete each lab, except lab 3.3 where you will have two weeks
Deadline
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Key competence areas in design of embedded systemsKey competence areas in design of embedded systems
• Digital design – what this course is all about • Analog design
• Mixed mode design
• Software engineering and hardware/software co-design
• In this course, when we talk about ASIC design we most often mean digital ASIC design
• Common for students to think that digital designer does not have to know anything about analog design! Not true! Digital circuits are analog at low level. Every digital designer should now the basics of circuit theory and analog design. Take a few SME courses!
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What’s an ASIC?What’s an ASIC?
• Application Specific Integrated Circuit– “Specialized circuits block or entire chip which are designed
specifically for a given application”
– So, it’s not a CPU but the ASIC may contain a CPU
What’s a SOC?What’s a SOC?
• System-on-a-chip
– Systems that previously needed to be implemented on PCBs (Printed Circuit Boards) may be implemented on a single chip.
• The requirements is the basis for the specification
• A behavioral model may be written in C or some other high level language.
• A RTL model for the design is written in the design entry phase… flow continues on following slides
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Design entryDesign entry
• Traditionally performed with schematic entry tools, but with increased complexity schematic entry is not feasible
• Hardware Description Languages (HDL) allows designer to model hardware using abstract programming. Two HDLs are dominant: VHDL and Verilog (both are standardized by IEEE)
• Mixed HDL and schematic entry tools
• Module generators. Generate multiplexers, memory, data path elements for the specific target technology
• IP cores, Intellectual Property. Synthesizable VHDL/Verilog model or netlist of complex cores. For instance PCI, processor core, etc
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What is VHDL?What is VHDL?
• VHSIC (Very High Speed Integrated Circuits) Hardware Description Language
• Created by USA Department of Defense. Adopted as an IEEE standard in 1987. Latest standard is IEEE 1076 ‘93
• Intended for documenting and and modeling digital systems at different abstraction levels ranging from system level down to gate level
• Only a subset of the language is synthesizable, and that subset may differ from tool to tool. We will write RTL VHDL
• More about VHDL next lecture and in the first lab
• At this stage you have a HDL RTL model with no timing information. Only the function of the RTL model is verified
• The Unit Under Test (UUT) is instantiated in a HDL test bench and verified in a simulator
• The reference vector may come from a high level model
WAVEFORM GENERATION
COMPARE RESULTS
UNIT UNDER TEST
REFERENCE VECTORS
STIMULUS VECTORS OUTPUT VECTORS
TEST VECTOR
FILERESULTS
FILE
Optional Optional
HDL TESTBENCH
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SynthesisSynthesis
• Language synthesis. HDL code is compiled to known structural elements
• Optimization. Different algorithms are used to make your design as small and/or as fast as possible, depending on what you are optimizing for
• Technology mapping. The optimized structure is mapped to the target technology. The available components in the target technology isdefined in a technology library
• The output is a netlist readable for the implementation tools
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FloorplanningFloorplanning, placement and route, placement and route
• Floorplanning. Arranges some or all of the blocks or cells in the design. Floorplanning is done manually by the aid of tools
• Placement. Decides the placement of all cells• Route. Makes the connections between the cells
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Circuit extractionCircuit extraction• The implemented design is converted to a HDL description
• The delays of logic and interconnects are determined
Static timing analysisStatic timing analysis• Evaluates if timing constraints have been met
• Uses graph algorithms to evaluate delay through all paths
Post layout simulationPost layout simulation• Simulates the implemented design using same test bench as in
functional simulation
• Timing information is available. But for a fully synchronous design static timing analysis should cover all timing constraints
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FPGA design flow FPGA design flow -- used in labsused in labs
FPGA design is much less complex than to ASIC design –this is why we use FPGAs in the course.
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Design alternativesDesign alternatives
• Microprocessors
– Digital Signal Processors (DSP), micro controllers, etc
• Dedicated standard chipsets– PCI chipset, GPS chipset, etc
• Application specific integrated circuits (ASIC)
– Full custom, cell based, gate arrays
• Programmable logic
– Simple Programmable Logic Devices (SPLD), Complex Programmable Logic Devices (CPLD), Field Programmable Gate Arrays (FPGA) will be used in the labs