Slobodan Lubura, Milomir Šoja, Srđan Lale, Marko Ikić

Projekt „ESSNBS“

Niš, November 4th – 7th, 2012 - 1 -

DAAD

Experimental verification of single-phase Experimental verification of single-phase PLL with novel two-phase generator for PLL with novel two-phase generator for

grid-connected convertersgrid-connected converters

Slobodan Lubura, Milomir Šoja, Srđan Lale, Marko Ikić

The Faculty of Electrical Engineering, University East Sarajevo, East Sarajevo, Bosnia and Herzegovina

Projekt „ESSNBS“

Niš, November 4th – 7th, 2012 - 2 -

DAAD

Introduction

Two-phase generator

Vgrid_measured

Vα

Vβ

Park’s transformation

Vq_est

Vgrid_magnitude_est

0

PI

ωnom

ωest

s

1 θest

The general structure of single-phase PLL based on SRF theory

Projekt „ESSNBS“

Niš, November 4th – 7th, 2012 - 3 -

DAAD

Novel two-phase generator with noise and DC offset rejection

2

Vbeta

1

Valfa

Product3

Product1

Product

1s

Integrator2

1s

Integrator1

1s

Integrator

ki

Gain1 0

Constant

Add

2

w

1

Vin

The new two-phase generator with DC offset rejection realized inSimulink environment

Projekt „ESSNBS“

Niš, November 4th – 7th, 2012 - 4 -

DAAD

Novel two-phase generator with noise and DC offset rejection

• Proposed structure of novel two-phase generator can be presented with following transfer functions:

𝑊𝑚𝛼ሺ𝑠ሻ= 𝜔𝑠2𝑠3 + (𝜔+ 𝑘𝑖)𝑠2 + 𝜔2𝑠+ 𝑘𝑖𝜔2 (1)

𝑊𝑚𝛽ሺ𝑠ሻ= 𝜔2𝑠𝑠3 + (𝜔+ 𝑘𝑖)𝑠2 + 𝜔2𝑠+ 𝑘𝑖𝜔2 . (2)

• Both (1) and (2) represent transfer functions of band-pass filters.

Projekt „ESSNBS“

Niš, November 4th – 7th, 2012 - 5 -

DAAD

Experimental results of proposed PLL

3

Estimated gridamplitude

2

Estimated gridangular frequency

1

Estimatedreference current

Vin

w

Valf a

Vbeta

Two-phasegenerator

cos

TrigonometricFunction

Valf a

Vbeta

teta

Vde

Vqe

Synchronousreference system

Rate Transition

In1 Out1

PI regulator

w

Nominal gridangular frequency

w teta

Integrator with reset

Irefm

Gain5

k

Gain

100

Constant

Band-LimitedWhite Noise

AnalogInput

Analog InputHumusof t

MF624 [auto]

Block-diagram of proposed PLL topology realized in Simulink using Real Time Windows Target library

Projekt „ESSNBS“

Niš, November 4th – 7th, 2012 - 6 -

DAAD

Experimental results of proposed PLL – continuous model of PLL

4.45 4.46 4.47 4.48 4.49 4.5 4.51

-300

-200

-100

0

100

200

300

time [s]

Vin

, V

alfa

, V

beta

[V

]

Vin

ValfaVbeta

The response of two-phase generator on grid voltage with noise

Projekt „ESSNBS“

Niš, November 4th – 7th, 2012 - 7 -

DAAD

Experimental results of proposed PLL – continuous model of PLL

a) Input grid voltage with 30% DC offset and estimated grid amplitude, without control loop for DC offset rejection

b) Input grid voltage with 30% DC offset and estimated grid frequency, without control loop for DC offset rejection

4 4.05 4.1 4.15 4.2-500

0

500

time [s]

Vin

[V

]

4 4.05 4.1 4.15 4.2200

300

400

500

time [s]

Vest

[V]

4 4.05 4.1 4.15 4.2-500

0

500

time [s]

Vin

[V

]

4 4.05 4.1 4.15 4.245

50

55

time [s]

fest

[Hz]

a) b)

Projekt „ESSNBS“

Niš, November 4th – 7th, 2012 - 8 -

DAAD

Experimental results of proposed PLL – continuous model of PLL

a) Input grid voltage with 30% DC offset and estimated grid amplitude, with control loop for DC offset rejection

b) Input grid voltage with 30% DC offset and estimated grid frequency, with control loop for DC offset rejection

a) b)

4 4.05 4.1 4.15 4.2-400

-200

0

200

400

600

time [s]

Vin

[V

]

4 4.05 4.1 4.15 4.2332

334

336

338

time [s]

Vest

[V]

4 4.05 4.1 4.15 4.2-500

0

500

time [s]

Vin

[V

]

4 4.05 4.1 4.15 4.249.6

49.8

50

50.2

time [s]fe

st

[Hz]

Projekt „ESSNBS“

Niš, November 4th – 7th, 2012 - 9 -

DAAD

Experimental results of proposed PLL – continuous model of PLL

0 0.5 1 1.5 2 2.5 3 3.5 4

-400

-200

0

200

400

600

time [s]

Vest

[V]

ki=100

ki=10ki=500

0 0.5 1 1.5 2 2.5 3 3.5 420

40

60

80

time [s]

fest

[Hz]

ki=100

ki=10

ki=500

Estimated grid frequency (top) and amplitude (bottom) for ki = 10, 100 and 500 (robustness against step changes of grid frequency and amplitude)

Projekt „ESSNBS“

Niš, November 4th – 7th, 2012 - 10 -

DAAD

Experimental results of proposed PLL – continuous model of PLL

Input grid voltage with 30% DC offset and generated referencevoltage.

2 2.01 2.02 2.03 2.04 2.05 2.06 2.07 2.08-400

-300

-200

-100

0

100

200

300

400

500

time [s]

Vin

, V

out

[V]

Vin

Vout

Projekt „ESSNBS“

Niš, November 4th – 7th, 2012 - 11 -

DAAD

Experimental results of proposed PLL – discrete model of PLL

• Discretization of proposed PLL was performed in two ways:1𝑠 ≈ 𝑇𝑠2 ൬

𝑧+ 1𝑧− 1൰. (3)

1𝑠 ≈ 𝑇𝑠12ቆ5+ 8𝑧−1 − 𝑧−21− 𝑧−1 ቇ. (4)

Tustin approximation

Schneider approximation

Projekt „ESSNBS“

Niš, November 4th – 7th, 2012 - 12 -

DAAD

Experimental results of proposed PLL – discrete model of PLL

0 1 2 3 4 5 6-400

-300

-200

-100

0

100

200

300

400

time [s]

Ves

t [V

]

Schneider

Tustin

Estimated grid amplitude for two discrete models of PLL(step changes of grid parameters)

Ts=50μs

Projekt „ESSNBS“

Niš, November 4th – 7th, 2012 - 13 -

DAAD

Experimental results of proposed PLL – discrete model of PLL

Estimated grid frequency for two discrete models of PLL(step changes of grid parameters)

Ts=50μs

0 1 2 3 4 5 636

38

40

42

44

46

48

50

52

54

time [s]

fest

[H

z]

Tustin

Schneider

Projekt „ESSNBS“

Niš, November 4th – 7th, 2012 - 14 -

DAAD

Conclusion

• The results show that proposed PLL (both continual and discrete) can solve important issues of presence of DC offset and noise in measured values of grid voltage.

• Proposed PLL can be used for both, grid-connected systems (e.g. Photovoltaic and Wind turbines) and power condition equipment (uninterruptible power supply (UPS), active filters) which rely on PLL based synchronization.

• The further work should be implementation of proposed PLL topology on digital platform (using dsPIC).