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ONET1151P
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11.3 Gbps Limiting AmplifierCheck for Samples: ONET1151P
1FEATURES • Output Disable• Surface Mount Small Footprint 3 mm ×
3 mm• Up to 11.3 Gbps Operation
16-Pin RoHS Compliant QFN Package• Two-Wire Digital Interface•
Pin Compatible to the ONET8501PB• Adjustable LOS Threshold
• Digitally Selectable Output Voltage APPLICATIONS• Digitally
Selectable Output De-Emphasis
• 10 Gigabit Ethernet Optical Receivers• Adjustable Input
Threshold Voltage
• 2x/4x/8x and 10x Fibre Channel Optical• Output Polarity Select
Receivers• Programmable LOS Masking Time • SONET OC-192/SDH-64
Optical Receivers• Input Offset Cancellation • SFP+ and XFP
Transceiver Modules• CML Data Outputs with On-Chip 50-Ω Back- •
Cable Driver and Receiver
Termination to VCC• Single +3.3-V Supply• Low Power
Consumption
DESCRIPTIONThe ONET1151P is a high-speed, 3.3-V limiting
amplifier for multiple fiber optic and copper cable
applicationswith data rates up to 11.3 Gbps.
The device provides a two-wire serial interface which allows
digital control of the output amplitude, output pre-emphasis, input
threshold voltage (slice level) and the loss of signal assert
level.
The ONET1151P provides a gain of about 33dB which ensures a
fully differential output swing for input signalsas low as 20
mVp-p. The output amplitude can be adjusted between 350 mVp-p and
850 mVp-p. To compensate forfrequency dependent loss of microstrips
or striplines connected to the output of the device, programmable
de-emphasis is included in the output stage. A settable loss of
signal (LOS) detection with programmable outputmasking time and
output disable are also provided.
The part, available in RoHS compliant small footprint 3 mm x 3
mm 16-pin QFN package, typically dissipates 132mW with 550 mVp-p
output and is characterized for operation from −40°C to 100°C.
1
Please be aware that an important notice concerning
availability, standard warranty, and use in critical applications
ofTexas Instruments semiconductor products and disclaimers thereto
appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2013, Texas Instruments IncorporatedProducts conform to
specifications per the terms of the TexasInstruments standard
warranty. Production processing does notnecessarily include testing
of all parameters.
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Output BufferGain Stage
5050
VCC
100
Settings
4 Bit
Input Threshold
CPRNG and DE
Amplitude
LOS Adjust
Power-On Reset
Bandgap Voltage Reference and Bias Current Generation2-Wire
Interface &
Control Logic
SDA
SCK
DIS
DIN+
DIN-
SDA
SCK
DIS
DOUT+
DOUT-
Gain Stage
Offset Cancellation
8 Bit Register
3 Bit
LOS DetectionLOS
COC1 COC2
VCC
GND
8 Bit Register
8 Bit Register
LOS Masking8 Bit Register
4 Bit
LOS Masking8 Bit Register
Settings8 Bit Register
Input Buffer
ONET1151P
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This integrated circuit can be damaged by ESD. Texas Instruments
recommends that all integrated circuits be handled withappropriate
precautions. Failure to observe proper handling and installation
procedures can cause damage.
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be
moresusceptible to damage because very small parametric changes
could cause the device not to meet its published
specifications.
BLOCK DIAGRAM
A simplified block diagram of the ONET1151P is shown in Figure
1.
This compact, low power 11.3 Gbps limiting amplifier consists of
a high-speed data path with offset cancellationblock (DC feedback)
combined with an analog settable input threshold adjust, a loss of
signal detection blockusing 2 peak detectors, a two-wire interface
with a control-logic block and a bandgap voltage reference and
biascurrent generation block.
Figure 1. Simplified Block Diagram of the ONET1151P
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SCK
NC
GND
DIN+
DIN-
GND
DOUT+
VCC
DOUT-
VCCSD
A
NC
CO
C2
CO
C1
DIS
LO
S
2
1
3
4
11
12
10
9
65 7 8
1516 14 13
ONET1151P
16 Pin QFN
ONET1151P
www.ti.com SLLSEH8 –SEPTEMBER 2013
PACKAGE
The ONET1151P is available in a small footprint 3 mm × 3 mm
16-pin RoHS compliant QFN package with a leadpitch of 0.5 mm. The
pinout is shown in Figure 2.
Figure 2. Pinout of ONET1151P in a 3mm x 3mm 16-Pin QFN Package
(Top View)
Table 1. PIN DESCRIPTIONSPIN
TYPE DESCRIPTIONNAME NO.GND 1, 4, EP Supply Circuit ground.
Exposed die pad (EP) must be grounded.DIN+ 2 Analog-input
Non-inverted data input. Differentially 100 Ω terminated to
DIN–.DIN– 3 Analog-input Inverted data input. Differentially 100 Ω
terminated to DIN+.
Offset cancellation filter capacitor plus terminal. An external
capacitor can be connectedCOC1 5 Analog between this pin and COC2
to reduce the low frequency cutoff. To disable the offset
cancellation loop, connect COC1 and COC2 together.Offset
cancellation filter capacitor minus terminal. An external capacitor
can be connected
COC2 6 Analog between this pin and COC1 to reduce the low
frequency cutoff. To disable the offsetcancellation loop, connect
COC1 and COC2 together.
DIS 7 Digital-input Disables the output stage when set to a high
level.Open drain High level indicates that the input signal
amplitude is below the programmed threshold level.LOS 8 MOS Open
drain output. Requires an external 10kΩ pull-up resistor to VCC for
proper operation.
VCC 9, 12 Supply 3.3-V supply voltage.DOUT– 10 CML-out Inverted
data output. On-chip 50 Ω back-terminated to VCC.DOUT+ 11 CML-out
Non-inverted data output. On-chip 50 Ω back-terminated to VCC.NC
13, 14 No Connect Do not connectSCK 15 Digital-input Serial
interface clock input. Connect a pull-up resistor (10 kΩ typical)
to VCC.SDA 16 Digital-input Serial interface data input. Connect a
pull-up resistor (10 kΩ typical) to VCC.
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ONET1151P
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ABSOLUTE MAXIMUM RATINGS (1)over operating free-air temperature
range (unless otherwise noted)
VALUEPARAMETER UNIT
MIN MAXVCC Supply voltage (2) –0.3 4 VVDIN+, VDIN– Voltage at
DIN+, DIN– (2) 0.5 4 VVLOS, VCOC1, VCOC2,VDOUT+, VDOUT–, VDIS,
Voltage at LOS, COC1, COC2, DOUT+, DOUT-, DIS, SDA, SCK (2) –0.3
4.0 VVSDA, VSCKVDIN, DIFF Differential voltage between DIN+ and
DIN– ±2.5 VIDIN+, IDIN–, IDOUT+, Continuous current at inputs and
outputs 25 mAIDOUT–ESD ESD rating at all pins 2 kV (HBM)TA
Characterized free-air operating temperature range –40 100 °CTJ,
max Maximum junction temperature 125 °CTSTG Storage temperature
range –65 150 °CTC Case temperature –40 110 °CTLEAD Lead
temperature 1.6mm (1/16 inch) from case for 10 seconds 260 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. These are stress
ratingsonly, and functional operation of the device at these or any
other conditions beyond those indicated under Recommended
OperatingConditions is not implied. Exposure to
absolute–maximum–rated conditions for extended periods may affect
device reliability.
(2) All voltage values are with respect to network ground
terminal.
RECOMMENDED OPERATING CONDITIONSover operating free-air
temperature range (unless otherwise noted)
VALUEPARAMETER TEST CONDITIONS UNIT
MIN TYP MAXTA = –40°C to +100°C 2.9 3.3 3.63VCC Supply voltage
VTA = –30°C to +100°C 2.85 3.3 3.63
TA Operating free-air temperature –40 100 °CDIGITAL input high
voltage 2.0 VDIGITAL input low voltage 0.8 V
DC ELECTRICAL CHARACTERISTICSover recommended operating
conditions with 50-Ω output load, 550 mVp-p output voltage and BIAS
bit (Register 7) set to 1,unless otherwise noted. Typical operating
condition is at 3.3 V and TA = 25°C
VALUEPARAMETER TEST CONDITIONS UNIT
MIN TYP MAXTA = –40°C to +100°C 2.9 3.3 3.63VCC Supply voltage
VTA = –30°C to +100°C 2.85 3.3 3.63
IVCC Supply current DIS = 0, CML currents included 40 52 mARIN
Data input resistance Differential 100 ΩROUT Data output resistance
Single-ended, referenced to VCC 50 Ω
LOS HIGH voltage ISOURCE = 50 µA with 10 kΩ pull-up to VCC 2.3
VLOS LOW voltage ISINK = 10 mA with 10 kΩ pull-up to VCC 0.4 V
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ONET1151P
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AC ELECTRICAL CHARACTERISTICSover recommended operating
conditions with 50-Ω output load, 550mVpp output voltage and BIAS
bit (Register 7) set to 1,unless otherwise noted. Typical operating
condition is at VCC = 3.3 V and TA = 25°C.
VALUEPARAMETER TEST CONDITIONS UNIT
MIN TYP MAXf3dB-H -3dB bandwidth default settings 7.5 9.5
GHzf3dB-L Low frequency -3dB bandwidth With 330 pF COC capacitor 10
45 kHz
PRBS31 pattern at 11.3 Gbps, BER < 10–12 6 9VIN,MIN Data
input sensitivity mVp-pVOD-min ≥ 0.95 * VOD (output limited) 20
40
0.01 GHz < f < 5 GHz –15SDD11 Differential input return
gain dB
5 GHz < f < 12.1 GHz –8SDD22 Differential output return
gain 0.01 GHz < f < 5 GHz –15 dB
5 GHz < f < 12.1 GHz –8SCD11 Differential to common mode
conversion gain 0.01 GHz < f < 12.1 GHz –15 dB
0.01 GHz < f < 5 GHz –13SCC22 Common mode output return
gain dB
5 GHz < f < 12.1 GHz –9A Small signal gain 26 33 dBVIN-MAX
Data input overload BIAS (Reg7 bit 0) set to 1 2000 mVp-p
VIN = 15 mVp-p, K28.5 pattern 3 8DJ Deterministic jitter at 11.3
Gbps VIN = 30 mVp-p, K28.5 pattern 3 10 psp-p
VIN = 2000 mVp-p, K28.5 pattern 6 15RJ Random jitter VIN = 30
mVp-p 1 psrms
VIN > 30 mVp-p, DIS = 0, AMP[0..2] = 000 380 mVp-pVOD
Differential data output voltage VIN > 30 mVp-p, DIS = 0,
AMP[0..2] = 111 820DIS = 1 5 mVrms
VPREEM Output de-emphasis step size 1 dBtR Output rise time 20%
– 80%, VIN > 30 mVp-p 30 40 pstF Output fall time 20% – 80%, VIN
> 30 mVp-p 30 40 psCMOV AC common mode output voltage PRBS31
pattern; AMP[0..2] = 010 7 mVrms
LOW LOS assert threshold range min. K28.5 pattern at 11.3 Gbps,
LOSRNG = 0 15VTH mVp-pLOW LOS assert threshold range max. K28.5
pattern at 11.3 Gbps, LOSRNG = 0 35
HIGH LOS assert threshold range min. K28.5 pattern at 11.3 Gbps,
LOSRNG = 1 35VTH mVp-pHIGH LOS assert threshold range max. K28.5
pattern at 11.3 Gbps, LOSRNG = 1 80
Versus temperature at 11.3 Gbps 1.5 dBLOS threshold variation
Versus supply voltage VCC at 11.3 Gbps 1 dB
Versus data rate 1.5 dBLOS hysteresis (electrical) K28.5 pattern
at 11.3 Gbps 2 4 6.5 dB
TLOS_AST LOS assert time 2.5 10 80 µsTLOS_DEA LOS deassert time
2.5 10 80 µs
Maximum LOS output masking time 2000 µsLOS masking time step
size 32 µs
TDIS Disable response time 20 ns
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ONET1151P
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DETAILED DESCRIPTION
HIGH-SPEED DATA PATHThe high-speed data signal is applied to the
data path by means of input signal pins DIN+ / DIN–. The data
pathconsists of a 100-Ω differential termination resistor followed
by an input buffer. A gain stage and an output bufferstage follow
the input buffer, which together provide a gain of 33dB. The device
can accept input amplitudelevels from 6mVp-p up to 2000mVp-p. The
amplified data output signal is available at the output pins DOUT+
/DOUT– which include on-chip 2 × 50-Ω back-termination to VCC.
Offset cancellation compensates for internal offset voltages and
thus ensures proper operation even for verysmall input data
signals. The offset cancellation can be disabled so that the input
threshold voltage can beadjusted to optimize the bit error rate or
change the eye crossing to compensate for input signal pulse
widthdistortion. The offset cancellation can be disabled by setting
OCDIS = 1 (bit 1 of register 0). The input thresholdlevel can be
adjusted using register settings THADJ[0..7] (register 1). When
register 1 is set to 0x00, thethreshold adjustment circuitry is
disabled to reduce the supply current. Setting register 1 to any
other value willenable the circuitry and the supply current will
increase by approximately 2 mA. The amount of adjustment
thatregister 1 can provide is controlled by the CPRNG[1..0] bits
(register 2). For details regarding input thresholdadjust and
range, see Table 12.
The low frequency cutoff is as low as 80 kHz with the built-in
filter capacitor. For applications, which require evenlower cutoff
frequencies, an additional external filter capacitor may be
connected to the COC1 and COC2 pins. Avalue of 330 pF results in a
low frequency cutoff of 10 kHz.
The receiver can be optimized for various applications using the
settings in register 7. To enable the settings, setthe SEL bit (bit
7 of register 7) to 1. It is recommended that the BIAS bit (bit 0
of register 7) be set to 1, especiallyif the input voltage to the
ONET1151P will exceed about 500 mVp-p differential. Setting BIAS to
1 adds 2 mA ofbias current to the input stage, making it more
robust for high input voltages. For input voltages lower than
500mVp-p, as typically would be supplied from a transimpedance
amplifier (TIA), BIAS can be set to 0 to reduce thesupply current.
In addition, the RXOPT[1..0] bits (register 7) can be used to
optimize the jitter based upon the TIAthat is used. When RXOPT is
set to 00, there is some input equalization set at the input to the
limiting amplifier.This is a good general setting to use and for
most applications it is recommended to set register 7 to 0x81. If
theinput voltage to the limiting amplifier does not exceed about
500 mVp-p differential, then the jitter may be reducedby setting
register 7 to 0x85.
BANDGAP VOLTAGE AND BIAS GENERATIONThe ONET1151P limiting
amplifier is supplied by a single +3.3-V supply voltage connected
to the VCC pins. Thisvoltage is referred to ground (GND).
On-chip bandgap voltage circuitry generates a reference voltage,
independent of supply voltage, from which allother internally
required voltages and bias currents are derived.
HIGH-SPEED OUTPUT BUFFERThe output amplitude of the buffer can
be varied from 350 mVp-p to 850 mVp-p using the register
settingsAMP[0..2] (register 3) via the serial interface. The
default amplitude setting is AMP[0..2] = 010 which provides550
mVp-p differential output voltage. To compensate for frequency
dependant losses of transmission linesconnected to the output, the
ONET1151P has adjustable de-emphasis of the output stage. The
de-emphasis canbe set from 0 to 8dB in 1dB steps using register
settings DEADJ[0..3] (register 2).
In addition, the polarity of the output pins can be inverted by
setting the output polarity switch bit, POL (bit 4 ofregister 0) to
1.
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ONET1151P
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LOSS OF SIGNAL DETECTIONThe loss of signal detection is done by
2 separate level detectors to cover a wide dynamic range. The
peakvalues of the input signal and the output signal of the gain
stage are monitored by the peak detectors. The peakvalues are
compared to a pre-defined loss of signal threshold voltage inside
the loss of signal detection block. Asa result of the comparison,
the LOS signal, which indicates that the input signal amplitude is
below the definedthreshold level, is generated. The LOS assert
level is settable through the serial interface. There are 2
LOSranges settable with the LOSRNG bit (bit 2 register 0). By
setting LOSRNG = 1, the high range of the LOS assertvalues are used
(35 mVp-p to 80 mVp-p) and by setting LOSRNG = 0, the low range of
the LOS assert values areused (15 mVp-p to 35 mVp-p).
There are 128 possible internal LOS settings (7bit) for each LOS
range to adjust the LOS assert level. If the LOSregister selection
bit is set low, LOSSEL = 0 (bit 7 of register 11), then the default
LOS assert level ofapproximately 25 mVp-p is used. If the register
selection bit is set high, LOSSEL = 1 (bit 7 of register 11), then
thecontent of LOS[0..6] (register 11) is used to set the LOS assert
level.
An LOS output masking time can be enabled on the raising and
falling edges of the LOS output signal. The LOSrising edge masking
time is enabled by setting LOSTMRENA = 1 (bit 7 of register 13) and
the time programmedusing LOSTMR[0..6] (register 13). The LOS
falling edge masking time is enabled by setting LOSTMFENA = 1 (bit7
of register 12) and the time programmed using LOSTMF[0..6]
(register 12).This feature is used to mask a falseinput to the
limiting amplifier after a loss of signal has occurred or when the
input signal is re-applied. Themasking time can be set from 10 μs
to 2 ms.
2-WIRE INTERFACE AND CONTROL LOGICThe ONET1151P uses a 2-wire
serial interface for digital control. The two circuit inputs, SDA
and SCK, aredriven, respectively, by the serial data and serial
clock from a microcontroller, for example. Both inputs
include100-kΩ pull-up resistors to VCC. For driving these inputs,
an open drain output is recommended.
The 2-wire interface allows write access to the internal memory
map to modify control registers and read accessto read out control
and status signals. The ONET1151P is a slave device only which
means that it can not initiatea transmission itself; it always
relies on the availability of the SCK signal for the duration of
the transmission. Themaster device provides the clock signal as
well as the START and STOP commands. The protocol for a
datatransmission is as follows:1. START command2. 7 bit slave
address (1000100) followed by an eighth bit which is the data
direction bit (R/W). A zero indicates
a WRITE and a 1 indicates a READ.3. 8-bit register address4.
8-bit register data word5. STOP command
Regarding timing, the ONET1151P is I2C compatible. The typical
timing is shown in Figure 3 and complete datatransfer is shown in
Figure 4. Parameters for Figure 3 are defined in Table 2.
Bus Idle: Both SDA and SCK lines remain HIGH.Start Data
Transfer: A change in the state of the SDA line, from HIGH to LOW,
while the SCK line is HIGH,defines a START condition (S). Each data
transfer is initiated with a START condition.
Stop Data Transfer: A change in the state of the SDA line from
LOW to HIGH while the SCK line is HIGHdefines a STOP condition (P).
Each data transfer is terminated with a STOP condition; however, if
the master stillwishes to communicate on the bus, it can generate a
repeated START condition and address another slavewithout first
generating a STOP condition.
Data Transfer: Only one data byte can be transferred between a
START and a STOP condition. The receiveracknowledges the transfer
of data.
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tBUF
tHDSTA
tRtLOW
tHDDAT
tHIGHtF
tSUDAT tSUSTA
tHDSTA
tSUSTO
P S S P
SDA
SCK
ONET1151P
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Acknowledge: Each receiving device, when addressed, is obliged
to generate an acknowledge bit. Thetransmitter releases the SDA
line and a device that acknowledges must pull down the SDA line
during theacknowledge clock pulse in such a way that the SDA line
is stable LOW during the HIGH period of theacknowledge clock pulse.
Setup and hold times must be taken into account. When a
slave-receiver doesn’tacknowledge the slave address, the data line
must be left HIGH by the slave. The master can then generate aSTOP
condition to abort the transfer. If the slave-receiver does
acknowledge the slave address but some timelater in the transfer
cannot receive any more data bytes, the master must abort the
transfer. This is indicated bythe slave generating the not
acknowledge on the first byte to follow. The slave leaves the data
line HIGH and themaster generates the STOP condition.
Figure 3. I2C Timing Diagram
Table 2. Timing Diagram DefinitionsParameter Symbol Min Max
Unit
SCK clock frequency fSCK 400 kHzBus free time between STOP and
START conditions tBUF 1.3 μsHold time after repeated START
condition. After this period, the first clock pulse is tHDSTA 0.6
μsgeneratedLow period of the SCK clock tLOW 1.3 μsHigh period of
the SCK clock tHIGH 0.6 μsSetup time for a repeated START condition
tSUSTA 0.6 μsData HOLD time tHDDAT 0 μsData setup time tSUDAT 100
nsRise time of both SDA and SCK signals tR 300 nsFall time of both
SDA and SCK signals tF 300 nsSetup time for STOP condition tSUSTO
0.6 μs
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S Slave Address Wr A Register Address A Data Byte A P
1 7 11 8 1 8 11
S Slave Address Wr A Register Address A Data Byte N P
1 7 11 8 1 8 11
Write Sequence
Read Sequence
S
1
Slave Address Rd A
7 11
Legend
S Start Condition
Wr Write Bit (bit value = 0)
Rd Read Bit (bit value = 1)
A Acknowledge
N Not Acknowledge
P Stop Condition
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Figure 4. Data Transfer
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ONET1151P
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REGISTER MAPPING
The register mapping for read/write register addresses 0 (0x00)
through 13 (0x0D) are shown in Table 3 throughTable 10. The
register mapping for the read only register address 15 (0x0F) is
shown in Table 11. Table 12describes the circuit functionality
based on the register settings.
Table 3. Register 0 (0x00) Mapping – Control SettingsRegister
Address 0 (0x00)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0- - CLKDIS POL
DIS LOSRNG OCDIS -
Table 4. Register 1 (0x01) Mapping – Input Threshold
AdjustRegister Address 1 (0x01)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0THADJ7 THADJ6
THADJ5 THADJ4 THADJ3 THADJ2 THADJ1 THADJ0
Table 5. Register 2 (0x02) Mapping – Cross Point Range and
De-emphasis AdjustRegister Address 2 (0x02)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0- - CPRNG1 CPRNG0
DEADJ3 DEADJ2 DEADJ1 DEADJ0
Table 6. Register 3 (0x03) Mapping – Output Amplitude
AdjustRegister Address 3 (0x03)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0- - - - - AMP2
AMP1 AMP0
Table 7. Register 7 (0x07) Mapping – Receiver
OptimizationRegister Address 7 (0x07)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0SEL - - - RXOPT1
RXOPT0 - BIAS
Table 8. Register 11 (0x0B) Mapping – LOS Assert LevelRegister
Address 11 (0x0B)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0LOSSEL LOSA6
LOSA5 LOSA4 LOSA3 LOSA2 LOSA1 LOSA0
Table 9. Register 12 (0x0C) Mapping – Falling Edge LOS Masking
RegisterRegister Address 12 (0x0C)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0LOSTMFENA LOSTMF6
LOSTMF5 LOSTMF4 LOSTMF3 LOSTMF2 LOSTMF1 LOSTMF0
Table 10. Register 13 (0x0D) Mapping – Rising Edge LOS Masking
RegisterRegister Address 13 (0x0D)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0LOSTMRENA LOSTMR6
LOSTMR5 LOSTMR4 LOSTMR3 LOSTMR2 LOSTMR1 LOSTMR0
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ONET1151P
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Table 11. Register 15 (0x0F) Mapping – Selected LOS Level (Read
Only)Register Address 15 (0x0F)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0- SELLOS6 SELLOS5
SELLOS4 SELLOS3 SELLOS2 SELLOS1 SELLOS0
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ONET1151P
SLLSEH8 –SEPTEMBER 2013 www.ti.com
Table 12. Register FunctionalityRegister Bit Symbol Function
7 -6 -
Disable I2C clock:5 CLKDIS 1 = clock disabled when DIS pin is
high
0 = clock enabledOutput polarity switch bit:
4 POL 1 = inverted polarity0 = normal polarityOutput disable
bit:0
3 DIS 1 = output disabled0 = output enabledLOS range bit:
2 LOSRNG 1 = high LOS assert voltage range0 = low LOS assert
voltage rangeOffset cancellation disable bit:
1 OCDIS 1 = offset cancellation is disabled0 = offset
cancellation is enabled
0 - Reserved7 THADJ7 Input threshold adjustment setting:6 THADJ6
Circuit disabled for 00000000 (0) – low supply current option5
THADJ5 Maximum positive shift for 00000001 (1)4 THADJ4 Minimum
positive shift for 01111111 (127)
13 THADJ3 Zero shift for 10000000 (128) – added supply current2
THADJ2 Minimum negative shift for 10000001 (129)1 THADJ1 Maximum
negative shift for 11111111 (255)0 THADJ07 -6 -5 CPRNG1 Cross point
range setting:
Minimum range for 004 CPRNG0 Maximum range for 1123 PEADJ3
De-emphasis setting:2 PEADJ2 0000 = 0dB 0100 = 3dB 1100 = 6dB1
PEADJ1 0001 = 1dB 0101 = 4dB 1101 = 7dB0 PEADJ0 0011= 2dB 0111 =
5dB 1111 = 8dB7 -6 -5 -4 -
3 3 -2 AMP2 Output amplitude adjustment:
000 = 350 mVp-p, 001 = 450 mVp-p, 010 = 550 mVp-p (default), 011
= 6001 AMP1 mVp-p0 AMP0 100 = 650 mVp-p, 101 = 700 mVp-p, 110 = 750
mVp-p, 111 = 850 mVp-p
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ONET1151P
www.ti.com SLLSEH8 –SEPTEMBER 2013
Table 12. Register Functionality (continued)Register Bit Symbol
Function
Receiver Optimization:7 SEL 1 = Content of register used to
optimize the receiver
0 = Default receiver settings6 -5 -4 -
73 RXOPT1 00 = Some input equalization (recommended)
01 = Reduced input equalization2 RXOPT01 -
Bias current for input stage control bit:0 BIAS 1 = Add 2 mA
extra bias current to the input stage (recommended).
0 = Default7 LOSSEL LOS assert level:6 LOSA6 LOSSEL = 15 LOSA5
Content of register bits 6 to 0 is used to select the LOS assert
level4 LOSA4 Minimum LOS assert level for 0000000
113 LOSA3 Maximum LOS assert level for 11111112 LOSA2 LOSASEL =
01 LOSA1 Default LOS assert level of 25 mVp-p is used0 LOSA07
LOSTMFENA Falling edge LOS mask enable and duration:6 LOSTMF6
LOSTMFENA = 1 enables falling edge LOS masking5 LOSTMF5 LOSTMFENA =
0 disables falling edge LOS masking4 LOSTMF4 Mask time < 10 μs
for 000000
123 LOSTMF3 Mask time > 2 ms for 1111112 LOSTMF21 LOSTMF10
LOSTMF07 LOSTMRENA Rising edge LOS mask enable and duration:6
LOSTMR6 LOSTMRENA = 1 enables rising edge LOS masking5 LOSTMR5
LOSTMRENA = 0 disables rising edge LOS masking4 LOSTMR4 Mask time
< 10 μs for 000000
133 LOSTMR3 Mask time > 2 ms for 1111112 LOSTMR21 LOSTMR10
LOSTMR0- - Selected LOS assert level (read only)6 SELLOS65 SELLOS54
SELLOS4
153 SELLOS32 SELLOS21 SELLOS10 SELLOS0
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-
VCC
DIN+
DIN- DOUT±
DOUT+
LOS
CO
C1
DIN+
DIN- DOUT±
DOUT+
NC
SC
K
SD
A
VCC
VCC
GND
GNDN
C
LOS
DIS
CO
C2
ONET1151P
16 Pin QFN
C1 0.1�F
C5 330pF
L1 BLM15HD102SN1
DISABLE
C2 0.1�F
SD
A
SC
K
C3 0.1�F
C4 0.1�F
C6 0.1�F
ONET1151P
SLLSEH8 –SEPTEMBER 2013 www.ti.com
APPLICATION INFORMATION
Figure 5 shows a typical application circuit using the
ONET1151P.
Figure 5. Typical Application Circuit
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-
±55
±50
±45
±40
±35
±30
±25
±20
±15
±10
±5
0
0.1 1.0 10.0 100.0
SD
D11
(dB
)
Frequency (GHz)
±50
±45
±40
±35
±30
±25
±20
±15
±10
±5
0
0.1 1.0 10.0 100.0
SD
D22
(dB
)
Frequency (GHz)
0
5
10
15
20
25
30
35
40
45
50
0.01 0.1 1 10 100
SD
D21
(dB
)
Frequency (GHz)
0
100
200
300
400
500
600
700
800
0 20 40 60 80 100 V
OU
T -
Out
put
Vol
tage
(m
Vp-
p)
VIN - Input Voltage (mVp-p)
ONET1151P
www.ti.com SLLSEH8 –SEPTEMBER 2013
TYPICAL CHARACTERISTICSTypical operating condition is at VCC =
3.3 V, TA = 25°C, and Register 7 set to 0x81 (unless otherwise
noted).
FREQUENCY RESPONSE TRANSFER FUNCTION
Figure 6. Figure 7.
DIFFERENTIAL INPUT RETURN GAIN DIFFERENTIAL OUTPUT RETURN GAINvs
vs
FREQUENCY FREQUENCY
Figure 8. Figure 9.
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-
0.0
0.4
0.8
1.2
1.6
2.0
2.4
2.8
3.2
0 10 20 30 40 50 60 70 80 90 100
RJ
- R
ando
m J
itter
(ps
RM
S)
VIN - Input Voltage (mVp-p)
0
10
20
30
40
50
60
70
80
90
128 138 148 158 168 178 188 198 208 218 228 238 248 258
LOS
Ass
ert/D
eass
ert
Vol
tage
(m
Vp-
p)
Register Setting (Decimal)
LOS Deassert Voltage
LOS Assert Voltage
1.0E-15
1.0E-14
1.0E-13
1.0E-12
1.0E-11
1.0E-10
1.0E-09
0 1 2 3 4 5
BE
R
VIN - Input Voltage (mVp-p)
0
1
2
3
4
5
6
7
8
9
10
0 200 400 600 800 1,000 1,200 1,400 1,600 1,800 2,000 D
J -
Det
erm
inis
tic J
itter
(ps
p-p)
VIN - Input Voltage (mVp-p)
ONET1151P
SLLSEH8 –SEPTEMBER 2013 www.ti.com
TYPICAL CHARACTERISTICS (continued)Typical operating condition
is at VCC = 3.3 V, TA = 25°C, and Register 7 set to 0x81 (unless
otherwise noted).
BIT-ERROR RATIO DETERMINISTIC JITTERvs vs
INPUT AMPLITUDE (11.3GBPS) INPUT AMPLITUDE
Figure 10. Figure 11.
RANDOM JITTER LOS ASSERT / DEASSERT VOLTAGEvs vs
INPUT AMPLITUDE REGISTER SETTING (LOSRNG = 0)
Figure 12. Figure 13.
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-
0
1
2
3
4
5
6
7
8
158 168 178 188 198 208 218 228 238 248 258
LOS
Hys
tere
sis
(dB
)
Register Setting (Decimal)
0
20
40
60
80
100
120
140
160
180
200
220
158 168 178 188 198 208 218 228 238 248 258
LOS
Ass
ert/D
eass
ert
Vol
tage
(m
Vp-
p)
Register Setting (Decimal)
LOS Deassert Voltage
LOS Assert Voltage
0
1
2
3
4
5
6
7
8
128 138 148 158 168 178 188 198 208 218 228 238 248 258 LO
S H
yste
resi
s (d
B)
Register Setting (Decimal)
ONET1151P
www.ti.com SLLSEH8 –SEPTEMBER 2013
TYPICAL CHARACTERISTICS (continued)Typical operating condition
is at VCC = 3.3 V, TA = 25°C, and Register 7 set to 0x81 (unless
otherwise noted).
LOS ASSERT / DEASSERT VOLTAGE LOS HYSTERESISvs vs
REGISTER SETTING (LOSRNG = 1) REGISTER SETTING (LOSRNG = 0)
Figure 14. Figure 15.
LOS HYSTERESISvs
REGISTER SETTING (LOSRNG = 1)
Figure 16.
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ONET1151P
SLLSEH8 –SEPTEMBER 2013 www.ti.com
TYPICAL CHARACTERISTICS (continued)Typical operating condition
is at VCC = 3.3 V, TA = 25°C, and Register 7 set to 0x81 (unless
otherwise noted).
OUTPUT EYE-DIAGRAM AT 11.3 GBPS OUTPUT EYE-DIAGRAM AT 11.3
GBPSAND 20 mVp-p INPUT VOLTAGE AND MAXIMUM INPUT VOLTAGE (2000
mVp-p)
Figure 17. Figure 18.
OUTPUT EYE-DIAGRAM AT 10.3 GBPS OUTPUT EYE-DIAGRAM AT 10.3
GBPSAND 20 mVp-p INPUT VOLTAGE (20 mVp-p) AND MAXIMUM INPUT VOLTAGE
(2000 mVp-p)
Figure 19. Figure 20.
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-
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status(1)
Package Type PackageDrawing
Pins PackageQty
Eco Plan(2)
Lead finish/Ball material
(6)
MSL Peak Temp(3)
Op Temp (°C) Device Marking(4/5)
Samples
ONET1151PRGTR ACTIVE VQFN RGT 16 3000 RoHS & Green NIPDAU
Level-2-260C-1 YEAR -40 to 100 1151P
ONET1151PRGTT ACTIVE VQFN RGT 16 250 RoHS & Green NIPDAU
Level-2-260C-1 YEAR -40 to 100 1151P
(1) The marketing status values are defined as follows:ACTIVE:
Product device recommended for new designs.LIFEBUY: TI has
announced that the device will be discontinued, and a lifetime-buy
period is in effect.NRND: Not recommended for new designs. Device
is in production to support existing customers, but TI does not
recommend using this part in a new design.PREVIEW: Device has been
announced but is not in production. Samples may or may not be
available.OBSOLETE: TI has discontinued the production of the
device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that
are compliant with the current EU RoHS requirements for all 10 RoHS
substances, including the requirement that RoHS substancedo not
exceed 0.1% by weight in homogeneous materials. Where designed to
be soldered at high temperatures, "RoHS" products are suitable for
use in specified lead-free processes. TI mayreference these types
of products as "Pb-Free".RoHS Exempt: TI defines "RoHS Exempt" to
mean products that contain lead but are compliant with EU RoHS
pursuant to a specific EU RoHS exemption.Green: TI defines "Green"
to mean the content of Chlorine (Cl) and Bromine (Br) based flame
retardants meet JS709B low halogen requirements of
-
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 2
-
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device PackageType
PackageDrawing
Pins SPQ ReelDiameter
(mm)
ReelWidth
W1 (mm)
A0(mm)
B0(mm)
K0(mm)
P1(mm)
W(mm)
Pin1Quadrant
ONET1151PRGTR VQFN RGT 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0
Q2
ONET1151PRGTT VQFN RGT 16 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0
Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 19-Sep-2019
Pack Materials-Page 1
-
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width
(mm) Height (mm)
ONET1151PRGTR VQFN RGT 16 3000 367.0 367.0 35.0
ONET1151PRGTT VQFN RGT 16 250 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 19-Sep-2019
Pack Materials-Page 2
-
www.ti.com
PACKAGE OUTLINE
C
16X 0.300.18
1.68 0.07
16X 0.50.3
1.00.8
(0.2) TYP
0.050.00
12X 0.5
4X1.5
A 3.12.9B
3.12.9
VQFN - 1 mm max heightRGT0016CPLASTIC QUAD FLATPACK - NO
LEAD
4222419/C 04/2021
PIN 1 INDEX AREA
0.08
SEATING PLANE
1
49
12
5 8
16 13
(OPTIONAL)PIN 1 ID 0.1 C A B
0.05
EXPOSEDTHERMAL PAD
SYMM
SYMM
NOTES: 1. All linear dimensions are in millimeters. Any
dimensions in parenthesis are for reference only. Dimensioning and
tolerancing per ASME Y14.5M. 2. This drawing is subject to change
without notice. 3. The package thermal pad must be soldered to the
printed circuit board for thermal and mechanical performance.
SCALE 3.600
-
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MINALL AROUND
0.07 MAXALL AROUND
16X (0.24)
16X (0.6)
( 0.2) TYPVIA
12X (0.5)
(2.8)
(2.8)
(0.58)TYP
( 1.68)
(R0.05)ALL PAD CORNERS
(0.58) TYP
VQFN - 1 mm max heightRGT0016CPLASTIC QUAD FLATPACK - NO
LEAD
4222419/C 04/2021
SYMM
1
4
5 8
9
12
1316
SYMM
LAND PATTERN EXAMPLESCALE:20X
NOTES: (continued) 4. This package is designed to be soldered to
a thermal pad on the board. For more information, see Texas
Instruments literature number SLUA271 (www.ti.com/lit/slua271).5.
Vias are optional depending on application, refer to device data
sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled,
plugged or tented.
SOLDER MASKOPENING
METAL UNDERSOLDER MASK
SOLDER MASKDEFINED
METAL
SOLDER MASKOPENING
SOLDER MASK DETAILS
NON SOLDER MASKDEFINED
(PREFERRED)
-
www.ti.com
EXAMPLE STENCIL DESIGN
16X (0.6)
16X (0.24)
12X (0.5)
(2.8)
(2.8)
( 1.55)
(R0.05) TYP
VQFN - 1 mm max heightRGT0016CPLASTIC QUAD FLATPACK - NO
LEAD
4222419/C 04/2021
NOTES: (continued) 6. Laser cutting apertures with trapezoidal
walls and rounded corners may offer better paste release. IPC-7525
may have alternate design recommendations.
SYMM
ALL AROUNDMETAL
SOLDER PASTE EXAMPLEBASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 17:
85% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGESCALE:25X
SYMM
1
4
5 8
9
12
1316
17
-
IMPORTANT NOTICE AND DISCLAIMERTI PROVIDES TECHNICAL AND
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(INCLUDING REFERENCEDESIGNS), APPLICATION OR OTHER DESIGN ADVICE,
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appropriateTI products for your application, (2) designing,
validating and testing your application, and (3) ensuring your
application meets applicablestandards, and any other safety,
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change without notice. TI grants youpermission to use these
resources only for development of an application that uses the TI
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NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303,
Dallas, Texas 75265Copyright © 2021, Texas Instruments
Incorporated
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FEATURESAPPLICATIONSDESCRIPTIONBLOCK DIAGRAMPACKAGEABSOLUTE
MAXIMUM RATINGSRECOMMENDED OPERATING CONDITIONSDC ELECTRICAL
CHARACTERISTICSAC ELECTRICAL CHARACTERISTICSDETAILED
DESCRIPTIONHIGH-SPEED DATA PATHBANDGAP VOLTAGE AND BIAS
GENERATIONHIGH-SPEED OUTPUT BUFFERLOSS OF SIGNAL DETECTION2-WIRE
INTERFACE AND CONTROL LOGIC
REGISTER MAPPINGAPPLICATION INFORMATIONTYPICAL
CHARACTERISTICS