Slide 4 Vixulychuong5

7/31/2019 Slide 4 Vixulychuong5

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BI GING K THUT VI X LNGNH IN T-VIN THNGI HC BCH KHOA NNGCA H VIT VIT, KHOA TVT

Ti liu tham kho

[1] K thut vi x l, Vn Th Minh, NXB Gio dc, 1997

[2] K thut vi x l v Lp trnh Assembly cho h vi xl, Xun Tin, NXB Khoa hc & k thut, 2001


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CHNG 5THIT K CC CNG I/O

5.1 I/O c phn vng nh v I/O tch bit- I/O c phn vng nh (Memory Mapped I/O)- I/O tch bit (Isolated I/O)

5.2 Cc chip MSI dng lm cng I/O- Cng ra- Cng vo

5.3 Chip 8255

- S chn, Skhichcnng- Cc mode hotng- Gii m ach- Lp trnh cho 8255


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5.1 CN PHN BIT 2 KIU THIT K

I/O c phn vng nh (Memory mapped I/O):- 1 cng c xem nh mt nh- 1 cng c a ch 20-bit

- c truy cp khi IO/M = 0- khng cn mch gii m a ch ring

I/O tch bit (isolated I/O)- 1 cng c xem ng l 1 cng- 1 cng c a ch 16-bit, 12-bit, 8-bit- c truy cp khi IO/M = 1- cn mch gii m a ch I/O ring


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5.2 CC CHIP MSI THNG DNG LM CNG I/O

74LS373

74LS374

74LS244 74LS245

Khi s lng cng t v c nh

Cch mc mch s quyt nh cho chip lcng ra hay cng vo v a ch ca n


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S DNG 74LS245 LM CNG RA

:

mov al, 55

mov dx, F000

out dx, al

:

8088Minimum

Mode

A18

A0

:

D7

D6

IOR

IOW

A19

D5

D4

D3

D2

D1

D0

74LS245

B0

B1

B2

B3

B4

B5B6

B7

A0

A1

A2

A3

A4

A5A6

A7

E DIR 5V

A

15

A

14

A

13

A

12

A

11

A

10

A

9A

8A

7A

6A

5A

4A

3A

2A

1A

0IOW


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S DNG 74LS373 LM CNG RA

:

mov al, 55

mov dx, F000

out dx, al

:

A

1

5

8088Minimum

Mode

A18

A0

:

D7

D6

IOR

IOW

A19

D5

D4

D3

D2D1

D0

A

1

4

A

1

3

A

1

2

A

1

1

A

1

0

A

9A

8A

7A

6A

5A

4A

3A

2A

1A

0IOW

74LS373

Q0

Q1

Q2

Q3

Q4

Q5Q6

Q7

D0

D1

D2

D3

D4

D5D6

D7

OELE


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S DNG 74LS245 LM CNG VO

:

mov dx, F000

in al, dx

:A

1

5

8088Minimum

Mode

A18

A0

:

D7

D6

IOR

IOW

A19

D5

D4

D3

D2D1

D0

A

1

4

A

1

3

A

1

2

A

1

1

A

1

0

A

9A

8A

7A

6A

5A

4A

3A

2A

1A

0IOR

5V

74LS245

B0

B1

B2

B3

B4

B5B6

B7

A0

A1

A2

A3

A4

A5A6

A7

E DIR


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CNG RA


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CNG VO


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5.3 CHIP LSI THNG DNG LM CNG I/O

PPI 8255

Khi s lng cng I/O nhiu v khng cnh

Cch mc mch s quyt nh a ch chocc cng cn vai tr ca cng s c quytnh bi phn mm


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8255 PPI


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S khi chc nng ca 8255


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CC MODE LM VIC

Mode 0- PA, PB, PCH (CU) v PCL (CL)- C th l Input hoc Output- Vic Nhp hoc Xut d liu l c lp

Mode 1

- PA, PB- C th l Input hoc Output- Vic Nhp hoc Xut d liu l ph thuc vo mt s btca PC (cc tn hiu handshaking)

Mode 2

- PA- PA va l Input va l Output- Vic Nhp/Xut d liu vi PA l ph thuc vo mt s btca PC (cc tn hiu handshaking)


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NHM LM VIC

Nhm A: PA v PCH

Nhm B: PB v PCL

nh cu hnh lm vic cho 1 chip 8255: Gi1 T iu khin nh cu hnhn thanh ghiiu khin ca chip

Lp/xo mt bit ca PC: Gi 1 T iu khinLp/Xobit n thanh ghi iu khin cachip


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T iu khin nh cu hnh lm vic cho mt chip 8255


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T iu khin lp/xo bit cho mt chip 8255


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Th 8255 P bl P i h l I t f


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The 8255 Programmable Peripheral Interface Intel has developed several peripheral controller chips designed to support the 80x86processor family. The intent is to provide a complete I/O interface in one chip. 8255 PPI provides three 8 bit input ports in one 40 pin package making it moreeconomical than 74LS373 and 74LS244

The chip interfaces directly to the data bus of the processor, allowing its functions to beprogrammed; that is in one application a port may appear as an output, but in another,by reprogramming it as an input. This is in contrast with the 74LS373 and 74LS244which are hard wired and fixed.8255 Pins PA0 - PA7: input, output, or bidirectional port PB0 - PB7: input or output PC0 - PC7: This 8 bit port can be all input or output. It can also be split into two parts,CU (PC4 - PC7) and CL (PC0 - PC3). Each can be used for input and output. RD or WR IOR and IOW of the system are connected to these two pins

RESET A0, A1, and CS CS selects the entire chip whereas A0 and A1 select the specific port (A, B, or C) orControl Register.


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Gii m a ch cho 8255

M d 0 Si l i t/ t t


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Mode 0 - Simple input/output Simple I/O mode: any of the ports A, B, CL, and CU can be programmed as input oroutput. Example: Configure port A as input, B as output, and all the bits of port C as outputassuming a base address of 50h

Control word should be 1001 0000b = 90hMOV AL, 90hOUT 53h,ALIN AL, 50hOUT 51h, ALOUT 52h, AL

Mode 1: I/O with Handshaking Capability Handshaking refers to the process of communicating back and forth between twointelligent devices Example. Process of communicating with a printer a byte of data is presented to the data bus of the printer the printer is informed of the presence of a byte of data to be printed by

activating its strobe signal whenever the printer receives the data it informs the sender byactivating an output signal called ACK the ACK signal initiates the process of providing another byte of data tothe printer 8255 in mode 1 is equipped with resources to handle handshaking

signals


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Mode 1 Strobed Output Signals OBFa (output buffer full for port A) indicates that the CPU has written a byte of data into port A must be connected to the STROBE of the receiving equipment ACKa (acknowledge for port A) through ACK, 8255 knows that data at port A has been picked up by the receiving

device 8255 then makes OBFa high to indicate that the data is old now. OBFa will not go lowuntil the CPU writes a new byte of data to port A. INTRa (interrupt request for port A) it is the rising edge of ACK that activates INTRa by making it high. INTRa is used toget the attention of the microprocessor.

it is important that INTRa is high only if INTEa, OBFa, ACKa are all high it is reset to zero when the CPU writes a byte to port A


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Mode 1 Input Ports with Handshaking Signals STB When an external peripheral device provides a byte of data to an input port, it informsthe 8255 through the STB pin. STB is of limited duration. IBF (Input Buffer Full) In response to STB, the 8255 latches into its internal registerthe data present at PA0-PA7 or PB0-PB7. Through IBF it indicates that it has latched the data but it has not been

read by the CPU yet. To get the attention of the CPU, it IBF activates INTR INTR Falling edge of RD makes INTR low The RD signal from the CPU is of limited duration and when it goes high the 8255 inturn makes IBF inactive by setting it low.

IBF in this way lets the peripheral know that the byte of data was latched by the 8255and read into the CPU as well.


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LP TRNH CHO 8255


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LI GII


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LP TRNH CHO 8255

B A

LI GII


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LI GII

TO CHUI XUNG BNG PHN MM


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TO CHUI XUNG BNG PHN MM

Slide 4 Vixulychuong5

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