Slide 3-1 Copyright © 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 3 3 Operating System Organization.

Operating Systems: A Modern Perspective, Chapter 3

Slide 3-1

Copyright © 2004 Pearson Education, Inc.

3Operating SystemOrganization


Slide 3-2


Purpose of an OS

The Abstractions

Create the Abstractions

Coordinate Useof the AbstractionsProcesses


Slide 3-3


Device Management

Device-IndependentPart

Device-IndependentPart

Device-DependentPart


Device …Device Device






Slide 3-4


Process, Thread, and Resource Management

…Processor

PrimaryMemory

AbstractResources

MultiprogrammingMultiprogramming

ThreadAbstraction

ThreadAbstraction

ProcessAbstraction

ProcessAbstraction Generic

ResourceManager

GenericResourceManager

OtherOther


Slide 3-5


Memory Management

PrimaryMemory

ProcessManager

ProcessManager

BlockAllocation

BlockAllocation

VirtualMemory

VirtualMemory

Isolation &Sharing

Isolation &Sharing

StorageDevices


Slide 3-6


Exclusive Access to a Resource

Process AProcess A

SupervisorProgram

SupervisorProgram

A’s ProtectedObject

A’s ProtectedObject

Processor

Process BProcess B


Slide 3-7


Kernels

• The part of the OS critical to correct operation (trusted software)

• Executes in supervisor mode

• The trap instruction is used to switch from user to supervisor mode, entering the OS


Slide 3-8


Supervisor and User Memory

UserSpace

UserSpace

SupervisorSpace

SupervisorSpace

UserProcess

UserProcess

SupervisorProcess

SupervisorProcess


Slide 3-9


Procedure Call and Message Passing Operating Systems

call(…);

trap

return;

send(…, A, …);receive(…, B, …);

receive(…A, …); …send(…, B, …);

send/receive


Slide 3-10


System Call Using the trap Instruction

…fork();…

fork() {…trap N_SYS_FORK()…}

sys_fork()

sys_fork() {/* system function */ … return;}

KernelTrap Table


Slide 3-11


A Thread Performing a System Call

User Space Kernel Space

fork();

sys_fork() {

}

Thread


Slide 3-12


Basic Operating System Organization

Processor(s) Main Memory Devices

Process, Thread &Resource Manager

MemoryManager

DeviceManager

FileManager


Slide 3-13


LibrariesLibraries CommandsCommands

Device DriverDevice Driver

The UNIX ArchitectureInteractive User

ApplicationPrograms

ApplicationPrograms

OS System Call Interface



Dri

ver

Inte

rfac

eD

rive

r In

terf

ace

…Monolithic Kernel Module•Process Management•Memory Management•File Management•Device Mgmt Infrastructure

Trap Table

…


Slide 3-14


Windows NT Organization

Processor(s) Main Memory Devices

LibrariesLibraries

ProcessProcess

ProcessProcess

ProcessProcess

SubsystemSubsystemUser

Supervisor

SubsystemSubsystem SubsystemSubsystem

Hardware Abstraction LayerHardware Abstraction LayerNT Kernel

NT ExecutiveI/O SubsystemI/O Subsystem

TT

TT

TT T T

T

Process ManagementMemory ManagementFile ManagementDevice Mgmt Infrastructure


Slide 3-15


4ComputerOrganization


Slide 3-16


Stored Program Computers and

Electronic Devices

Pattern

Fixed Electronic Device

Variable Program

Stored Program Device

Jacquard Loom


Slide 3-17


The von Neumann Architecture

Control Unit(CU)

Central Processing Unit (CPU)

DeviceDevice

Address BusData Bus

Arithmetical Logical Unit(ALU)

Primary Memory Unit(Executable

Memory)


Slide 3-18


The ALU

R1R2

Rn

. . .

Status RegistersFunctional Unit

Left Operand

Right Operand

Result

To/from Primary Memory

load R3,bload R4,cadd R3,R4store R3,a


Slide 3-19


Control Unit

3046305030543058

Primary Memory

Fetch UnitFetch Unit

Decode UnitDecode Unit

Execute UnitExecute Unit

PC

IR

Control Unit

load R3,bload R4,cadd R3,R4store R3,a

10111001001100…110111001010000…010100111001100…010111010001100…1load R4, c

3050


Slide 3-20


Control Unit Operation

PC = <machine start address>;IR = memory[PC];haltFlag = CLEAR;while(haltFlag not SET) { execute(IR); PC = PC + sizeof(INSTRUCT); IR = memory[PC]; // fetch phase};

• Fetch phase: Instruction retrieved from memory

• Execute phase: ALU op, memory data reference, I/O, etc.


Slide 3-21


Primary Memory Unit

MAR

MDR

Command

012

n-1

1234 98765Read Op:

1234

1. Load MAR with address

read

2. Load Command with “read”

98765

3. Data will then appear in the MDR

Address Register

Data Register


Slide 3-22


The Device-Controller-Software Relationship

Application Program

Device ControllerDevice Controller

DeviceDevice

Sof

twar

e in

the

CP

U

Abstract I/O Machine

•Device manager•Program to manage device controller•Supervisor mode software


Slide 3-23


Device Controller Interface

CommandCommand StatusStatusData 0Data 0

Data 1Data 1

Data n-1Data n-1LogicLogic

busy done Error code . . .. . .busy done 0 0 idle 0 1 finished 1 0 working 1 1 (undefined)


Slide 3-24


CPU-I/O Overlap

CPUCPU

DeviceDevice

…

Rea

dy P

roce

sses

CPUCPU

DeviceDevice

…

Rea

dy P

roce

sses

I/O Operation

CPUCPU

DeviceDevice

…

Rea

dy P

roce

sses

Uses CPU


Slide 3-25


Determining When I/O is Complete

CPUCPU

DeviceDevice DeviceDevice DeviceDevice

Interrupt Pending

• CPU incorporates an “interrupt pending” flag• When device.busy FALSE, interrupt pending flag is set• Hardware “tells” OS that the interrupt occurred• Interrupt handler part of the OS makes process ready to run


Slide 3-26


Control Unit with Interrupt (Hardware)

PC = <machine start address>;IR = memory[PC];haltFlag = CLEAR;while(haltFlag not SET) { execute(IR); PC = PC + sizeof(INSTRUCT); IR = memory[PC]; if(InterruptRequest) { memory[0] = PC; PC = memory[1]};

memory[1] contains the address of the interrupt handler


Slide 3-27


Interrupt Handler (Software)

interruptHandler() { saveProcessorState(); for(i=0; i<NumberOfDevices; i++) if(device[i].done) goto deviceHandler(i); /* something wrong if we get to here … */

deviceHandler(int i) { finishOperation(); returnToScheduler();}


Slide 3-28


A Race Condition

saveProcessorState() { for(i=0; i<NumberOfRegisters; i++) memory[K+i] = R[i]; for(i=0; i<NumberOfStatusRegisters; i++) memory[K+NumberOfRegisters+i] = StatusRegister[i];}

PC = <machine start address>;IR = memory[PC];haltFlag = CLEAR;while(haltFlag not SET) { execute(IR); PC = PC + sizeof(INSTRUCT); IR = memory[PC]; if(InterruptRequest && InterruptEnabled) { disableInterupts(); memory[0] = PC; PC = memory[1]};


Slide 3-29


Revisiting the trap Instruction (Hardware)

executeTrap(argument) { setMode(supervisor); switch(argument) { case 1: PC = memory[1001]; // Trap handler 1 case 2: PC = memory[1002]; // Trap handler 2 . . . case n: PC = memory[1000+n];// Trap handler n};

• The trap instruction dispatches a trap handler routine atomically

• Trap handler performs desired processing

• “A trap is a software interrupt”


Slide 3-30


Direct Memory Access

PrimaryMemory

CPU

Controller

Device

PrimaryMemory

CPU

Controller

Device


Slide 3-31


Addressing Devices

PrimaryMemory

Device 0

Device 1

Device n-1

PrimaryMemory

Device 0

Device 1

Device n-1

Dev

ice

Add

ress

esM

emor

y A

ddre

sses

Mem

ory

Add

ress

es


Slide 3-32


Polling I/O…// Start the device…While((busy == 1) || (done == 1)) wait();// Device I/O complete…done = 0;

…while((busy == 0) && (done == 1)) wait();// Do the I/O operationbusy = 1;…

busy done

Sof

twar

eH

ard

war

e


Slide 3-33


Detecting an Interrupt

CPUCPU

DeviceDevice DeviceDevice DeviceDevice

InterruptRequest flag


Slide 3-34


The Trap Instruction Operation

SMode

TrustedCode

trap

User Supervisor

Branch Table

2

3

1


Slide 3-35


Intel System Initialization

ROM

CMOS

RAM

Boot DevicePOSTPOST

BIOSBIOS

Boot ProgBoot Prog

LoaderLoader

OSOS

…Hardware Process

Data Flow

Power Up


Slide 3-36


Bootstrapping

Bootstrap loader (“boot sector”)

Primary Memory

Loader

OS

12

3

4. Initialize hardware5. Create user environment6. …

Fetch UnitFetch Unit

Decode UnitDecode Unit

Execute UnitExecute Unit

000A000000A000

……

PC

IR

BIOS loader 0x00001000x0001000

0x0008000

0x000A000

Slide 3-1 Copyright © 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 3 3 Operating System Organization.

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