Slide 1 7. Verilog: Combinational always statements. VHDL: Combinational Processes: To avoid (I.E. DO NOT What in your HDL code?) Cases that generate Synthesis.

Slide 1

7. Verilog: Combinational always statements. VHDL: Combinational

Processes:

To avoid(I.E. DO NOT What in your

HDL code?)Cases that generate Synthesis

Warnings

Slide 2

1. Make INCOMPLETE ASSIGNMENTS

2. Exclude based on the SENSITIVITY LIST

3. Make COMBINATIONAL LOOPS

• Why these are not treaten as an error by the synthesizer?

DO NOT:

Verilog for Synthesis: Combinational always statements

Slide 31. INCOMPLETE ASSIGNEMNTS in combinational always

statements

• Example

module NOT_GOOD(input A, input B,input SEL,output reg Q);

always @ (A or B or SEL)if (SEL) Q<=A;

endmodule• WHAT WILL BE THE VALUE OF Q WHEN SEL = 0?• The Synthesizer will not be able to determint the value of Q when

SEL = 0. Therefore:• WILL RETAIN THE VALUE OF Q! (by default will consider

else Q<=Q;)• THEREFORE: WILL INFER A TRANSPARENT LATCH!

Slide 41 INCOMPLETE ASSIGNEMNTS in combinational always

statements:

• Example:

module CORRECT1(input A, input B,input SEL,output reg Q);

always @ (A or B or SEL)Q <=B;if (SEL) Q<=A;

endmodule• SIGNALS ARE GETTING THEIR NEW VALUE AT THE END

OF THE ALWAYS STATEMEMNT! (Their value can be read only after the always statement is ended and relaunched)

• In tis case, XST CAN DETERMINE THE VALUE OF Q when SEL=0, so it will infer a multiplexer!

Slide 51. INCOMPLETE ASSIGNEMNTS in combinational always statements

• Same for the code below (the more known version)module CORRECT2(input A, input B,input SEL,output reg Q);

always @ (A or B or SEL)if (SEL) Q<=A;

else Q <= B;endmodule• So, if possible, for describing simple logic, use assign!• Less lines to write• In the case of an incomplete assignment the syntax

checker will generate an error: assign Q = (SEL==1) ? A;

Slide 61. INCOMPLETE ASSIGNEMNTS in combinational always statements

• Note: The following is also an incomplete assignment!

• Example:

module AND_2(input A, input B,output reg F);

always @ (A or B)if (A&&B) F<=1;

else F <= 1; //It should be 0! //This can be from a typo!endmodule• Keep in mind, that the Synthesizer MINIMIZES!

Slide 71. INCOMPLETE ASSIGNEMNTS in combinational always statements

• The synthesizer minimizes!• Generally:• For an input that is NOT READ, it means that is NOT USED.

The synthesizer generates a warning message such as:• WARNING:Xst:647 - Input <B> is never used.• Note A signal is read also in a condition, such as if (B)

…., or (B==1), not only …<= B;!• For an output which NEVER CHANGES during circuit

operation, the synthesizer generates a warning such as:• WARNING:Xst:xxxx – Output Q never changes during

circuit operation. Q is connected to VCC• Or:• WARNING:Xst:xxxx – Output Q is constant• Or, if Q changes during circuit operation ONLY ONCE:• WARNING:Xst:xxxx – The register/latch FDXX hinder

the constant Q cleaning in line XX

Slide 81. INCOMPLETE ASSIGNEMNTS in combinational always statements

• The synthesizer minimizes!• WARNING:Xst:xxxx – The register/latch FDXX hinder the

constant Q cleaning in line XX• This can happen when Q is initialized to a value and then in

the circuit is set to another CONSTANT value• Example:reg Q = 0;

always @ (posedge CLK) //even for sequential statements, //because Q will change only once!

Q <=1;• Q will be 0 at the beginning and then constantly 1!• Where is the greatest danger of making constant outputs?

Look carefully at the shift register code!:• Shift left: Q <= {Q[6:0], In} or Q <= {Q[7:1], In} ?• Shift right: Q<= {In, Q[7:1]} or Q <= {In, Q[6:0]} ?

Slide 91. INCOMPLETE ASSIGNEMNTS in combinational always statements

• The above examples are relatively simple and the mistake is visible

• But do you like to use nested if statements?• Example:always @ * beginif (A)

if (B) beginif (C) Q<=3’b010;

endelse Q <=3’b000; //else for which if?//it is else for if (B)//What if C = 0? It will infer a LATCHelse if (B) Q<=3’b111; //this else goes then to which if?//to if (A)

else if ….//and this one…? // to else if (B)! ALIGN “elses” to “ifs”!

• Better: Concat A, B, C into a bus and use assign or case• Sometimes, nested ifs can not be avoided. Example: Transform an 8-

bit counter to a 2-digit BCD counter (LAB exercise!)

Slide 101. INCOMPLETE ASSIGNEMNTS in combinational always statements

• Frequently appear in CASE statements• The “default” statement is not enough!

• Example: Logic describing transitions to a state machine: • StC represents the currents state, StN the next statealways @ * begincase (StC)Idle: if (In1) StN <= St1;

else StN <= Idle;St1: if (!In1) StN <=St2; //HERE IS NO ELSE! //THE SYNTHESIZER WILL INFER A

//LATCH FOR StN!St2: StN <= St3;St3: if (In2) StN <= St2;

else StN <= Idle;endcase

Slide 111 . INCOMPLETE ASSIGNEMNTS in combinational always statements

• Frequently appear in case statements• Solution that also allows for more compact

descriptionalways @ * beginStN <= StC; // by default, STAY IN THE CURRENT

//STATEcase (StC)Idle: if (In1) StN <= St1;St1: if (!In1) StN <=St2; St2: StN <= St3;St3: if (In2) StN <= St2; //here are two choices, we need else else StN <= Idle;default: StN <= Idle; //default DOES NOT TOTALLY SOLVE// INCOMPLETE ASSIGNMENTS, only for the CASE branches!// It also helps for safe implementation of a state machineendcase

Slide 121. . INCOMPLETE ASSIGNEMNTS in combinational always statements

• Why important to avoid?• Because can lead to inference of unwanted latches• One reason for simulation differences between

behavioral and post-translate• A latch is a memory element, it will not always act as a

combinational circuit!• The syntesizer generates a warning message:• WARNING:Xst:xxxx – Found x-bit latch for the signal

StN• LATCH este asynchronous. XST does not recommends

asynchronous circuits! • If the designer wants to intentionally generate

latches, the warning message can be ignored• Otherwise, review the code

Slide 13• Note: Incomplete assignments in Sequential always statements• Example:

always @ (posedge CLK)if (Reset) Q <= 0;else if (CE) Q<=Q+1;

• What happens with Q if Reset = 0 and CE = 0?• The counter will hold i.e. keeps its value

• No latch will be inferred, because anyway a register is inferred for the counter

• Incomplete assignments are allowed in sequential always statements• Used to describe the role of the “Clock Enable” types of

signals

Slide 14

1. Make INCOMPLETE ASSIGNMENTS

2. Exclude based on the SENSITIVITY LIST

3. Make COMBINATIONAL LOOPS

• Why these are not treaten as an error by the synthesizer?

DO NOT:

Verilog for Synthesis: Combinational always statements

Slide 15

DO NOT use the sensitivity list to exclude a signal!• Example: We want to read the value of a signal ONLY WHEN another signal changes (B will be read only when A changes)always @ (A or C) //The always statement will not be executed //by the simulator when B changes

Q<=(!C) | (A AND B);Behavioral Simulation Result:

B=0 but still Q=1

CAN BE PRACTICALLY MADE SUCH A CIRCUIT, WITHOUT USING A MEMORY ELEMENT (i.e. REGISTER)?

Excluding signals based on the SENSITIVITY LIST

Slide 16

DO NOT use the sensitivity list to exclude a signal!• Example: We want to read the value of a signal ONLY WHEN another signal changes (B will be read only when A changes)always @ (A or C) //The always statement will not be executed //by the simulator when B changes

Q<=(!C) | (A AND B);Synthesis result:

Post-Translate simulation result: Q changes no matter whether B changes or not

Excluding signals based on the SENSITIVITY LIST

Slide 17

DO NOT use the sensitivity list to exclude a signal!• Example: We want to read the value of a signal ONLY WHEN another signal changes (B will be read only when A changes)always @ (A or C) //The always statement will not be executed //by the simulator when B changes

Q<=(!C) | (A AND B);Synthesis result:

During synthesis:• WARNING:Xst:819 - c:/temp/test1/combinational.v line 21: The following signals are missing in the process sensitivity list:• RECOMMENDATION: INSERT IN THE SENSITIVITY LIST ALL OF THE SIGNALS READ IN THE ALWAYS STATEMENT! • This is a NECESARRY CONDITION for Behavioral and Post-Translate simulations to produce the same result!• Simplified solution: always @ *

Excluding signals based on the SENSITIVITY LIST

Slide 18

1. Make INCOMPLETE ASSIGNMENTS

2. Exclude based on the SENSITIVITY LIST

3. Make COMBINATIONAL LOOPS

• Why these are not treaten as an error by the synthesizer?

DO NOT:

Verilog for Synthesis: Combinational always statements

Slide 19• Example:

module Test(input [3:0] A, output reg [3:0] Q);always @ (A or Q)

Q<=Q + A; //Clearly a Combinational Loop

• From the simulator’s point of view: the always statement will run in an infinite loop (after finishes, Q changes, so the always statement is run again)

• If A is not 0, the Q immediately reaches its maximum value• The Behavioral simulator will hang or issue an error• But the circuit CAN BE SYNTHESIZED, EVEN WITHOUT A

WARNING!• The generated circuit is obviously useless (positive fedback – a latch?)• The Post-Translate and Post-Route simulators will not be able to

determine the value of Q, the output value will be always XXXX• AVOID COMBINATIONAL LOOPS!!!

Combinational Loops

Slide 20

• Everybody can avoid a combinational loop such as below:

Q<=Q + A; • HOWEVER: What about in a longer code?

always @ (A or B or C) begin … A<= B & … end …………. always @ (B or Q or C) begin … B<= Q | C |… end …………… always @ (Q or A or C) begin ….. if (A==…) Q<= end //A depends on B, B depends on Q and Q depends on A! It is a loop!

• What do you want to describe here?• Try to clear up first the combinational logic You want to

describe, then start writing the code!

Combinational Loops

Slide 21

• Note: Loops can be made in sequential always statements. In this case registers are inferred for keeping the value of Q:

always @ (posedge CLK) beginQ<=Q + A;

• Synthesis result:

• Behavioral and post-translate simulation result: Counter with increment of A

Combinational Loops