SLHC Meeting CERN, 21 May 2008 Presented by C.-E. Wulz C.-E. Wulz Global Triggers, Global Triggers, TCA Technology TCA Technology M. Stettler M. Stettler , M. Hansen (CERN) , M. Hansen (CERN) C. Foudas, G. Iles (Imperial College) C. Foudas, G. Iles (Imperial College) J. Jones (Princeton) J. Jones (Princeton) A. Taurok A. Taurok , H. Bergauer, C.-E. Wulz (Vienna) , H. Bergauer, C.-E. Wulz (Vienna)
Global Triggers, TCA Technology. M. Stettler , M. Hansen (CERN) C. Foudas, G. Iles (Imperial College) J. Jones (Princeton) A. Taurok , H. Bergauer, C.-E. Wulz (Vienna). Presented by C.-E. Wulz. SLHC Meeting CERN, 21 May 2008. COND ALGO. COND ALGO. Sync delay. PSB. REC. - PowerPoint PPT Presentation
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SLHC MeetingCERN, 21 May 2008
Presented by
C.-E. WulzC.-E. Wulz
Global Triggers,Global Triggers,TCA TechnologyTCA Technology
M. StettlerM. Stettler, M. Hansen (CERN) , M. Hansen (CERN) C. Foudas, G. Iles (Imperial College)C. Foudas, G. Iles (Imperial College)
J. Jones (Princeton)J. Jones (Princeton)A. TaurokA. Taurok, H. Bergauer, C.-E. Wulz (Vienna), H. Bergauer, C.-E. Wulz (Vienna)
C. - E. Wulz 2 SLHC Trigger Meeting, May 2008
Global Trigger Concepts for LHC and SLHC
FDL
GTL
GTL
128 Algo
GMT
PSBGCT
Syncdelay
Syncdelay
REC
COND ALGO
PSBSyncdelay
Technical Triggers
FDL chip
GTL
COND chip
GMTOptical links
GCT
Syncdelay
Syncdelay
SYNCSyncdelay
‘Conditions’
COND chip
nn Algo
(and,or,
not)
FPGA:Standard Conditions
- FPGA: DSPs (XC5V100T)
- FPOA: DSP array
TrackerTrigger
Syncdelay
Prescalers&
Trigger Counters
FinalOR
FinalOR
COND ALGO
LHC
SLHC
Tracker ‘Conditions’ Prescalers&
Trigger Counters
Totem, Castor, ZDC, BTPX, BSC, …
Totem, Castor, ZDC, BTPX, BSC, …
C. - E. Wulz 3 SLHC Trigger Meeting, May 2008
Global Trigger Concepts for LHC and SLHC
• Synchronize all Trigger Objects to arrive at the same time at the logic chip– 2008 Version: Muons: done by GMT; Calo_objects: done by PSB; Technical Triggers: done by PSB– SLHC Version: Muons: done by GMT; Calo_objects: done by GCT; TechTrig: done by SYNC chip
Tracker: done by Tracker_Trigger
• Send all Trigger Objects into one chip to be able to make any correlations between them• Use an FPGA to change trigger conditions as required by physics
– New trigger setup: -> configure FPGA with new trigger conditions– New parameter values for same setup:– 2008 Version: Load new ET and pT thresholds by software
– SLHC Version: Load all values by software ( Upgrade Version)
• Calculate physics trigger algorithms in parallel (FPGA branch)– 2008 Version: 128 Algorithms, limited by board layout, connectors and chip size
– SLHC Version: Extend to ‘nn’ Algorithms <- ‘Algo’ signals inside chip (chip size will be the only restriction)
• Final OR mask for all Algorithm bits; Prescaler & Counter for each Algorithm– SLHC: maybe more requirements
• SLHC Version: – Array of DSPs for complex physics triggers
• C++ code -> trigger program with constant latency(!)– Each trigger object is received twice, on 2 optical links
C. - E. Wulz 4 SLHC Trigger Meeting, May 2008
Input to Global Trigger
• Global Calorimeter Trigger (GCT): redefinition (reduction?) of trigger data• 4 e/, 4 isolatetd e/ 4 e/ with ISOLATION bit• 4 central jets, 4 forward jets n jets• 4 tau jets• total_ET, HT apply set of thresholds in GCT
and send resulting bits to FDL chip
• missing_ET
• “jet counts” (now towers above thr., ring ’s)• More than 4 objects per type: 5 or 6 (?) Simulation for SLHC
Trigger system design based on Telcom developments
C. - E. Wulz 9 SLHC Trigger Meeting, May 2008
ATCA standard
C. - E. Wulz 10 SLHC Trigger Meeting, May 2008
ATCA connectivity
C. - E. Wulz 11 SLHC Trigger Meeting, May 2008
TCA
C. - E. Wulz 12 SLHC Trigger Meeting, May 2008
TCA for GCT Quiet/ MIP Bits
• Data processing TCA module + custom active switching backplane
• Data processor card schematics have been designed (M. Stettler) and parts have been bought. The card is under layout at Los Alamos. Advanced PCB manufacturing techniques (e.g. micro-vias that penetrate several layers) are needed. Board stackup has been completed and verified with vendor.
• The Backplane has been designed (J. Jones + M. Stettler) but will be tested after the processor card.
• A TCA crate and a commercial backplane have been bought and are already at CERN.
• The first prototypes are expected to arrive at CERN in Summer 2008.
C. - E. Wulz 13 SLHC Trigger Meeting, May 2008
Main QM Data Processing Module
• Receives and transmits data via front panel optical links. • On board 72x72 Cross-Point Switch allows for dynamical routing of the data either to a V5 FPGA or directly to the uTCA backplane. • The module can exchange data with other modules either via the backplane or via the front panel optical links.
C. - E. Wulz 14 SLHC Trigger Meeting, May 2008
Custom TCA Backplane
• Instrumented with 144x144 cross-point switch for extra algorithm flexibility.• Allows dynamical or static routing of the data to different Data Processing Modules.
DSP48E Slices :add/subtract o = Z ± (X + Y +CIN)Accumulate o = o + A&B + C //concatenateAccumulate & shiftMultiply Accumulate(MACC)MUX, BarrelShifter, Counter, multiply, divide, square_root, square_root of sum of squares,Parallel FIR Filters,…
FPOA (..object arrays)1GHz clock256 ALU Arithmetic Logic Units 16 bit 64 MAC multiply&accumulate units 80 RF register set( 64 regs 16 bit) 2 fast serial IO links