SLAC uTCA review 4-5 June 2012

SLAC uTCA review4-5 June 2012

Anders J JohanssonLund University

Some slides from Zheqiao Geng and Tom Himel)

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Committee

• Alan Biocca LBNL• Brian Chase FNAL• Dmitry Teytelman Dimtel• Gunther Haller SLAC• Jim Sebek SLAC• John Carwardine ANL• Kay Rehlich DESY• Lawrence Doolittle LBNL• Richard Farnsworth ANL• Ryan Herbst, Chair SLAC

• Website: https://slacportal.slac.stanford.edu/sites/ad_public/events/mtca_llrf_jun_2012/Pages/default.aspx

LCLS-II: The New Upcoming Project

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• LCLS-II 4th generation light source underway• Injector approved for construction 2013-15• Linac, beamlines (2 undulators) 2014-17• MTCA.4 proposed, approved for Injector

A. Limited application to Injector RF, BPMsB. Broader future application to RF, Controls, Interlocks for

2-mile main linac (1/3 linac used by LCLS-I, LCLS-II and FACET high energy plasma wakefield experiment)

From Zheqiao Geng

New LLRF Architecture

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From Zheqiao Geng

RF 10 Ch RTM, ADC-FPGA-DAC

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IPMI ExtenderTo RF Chassis

Trig,RF RefIn

RTM Design – A. YoungRTM layout – C. YeeADC-DAC – Struck SIS8300

From Zheqiao Geng

New Stripline BPM Design – Motivation

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Pizza Boxes require large network plant, rack space

LCLS Stripline BPM System

From Zheqiao Geng

BPM µTCA Shelf Replaces Rack

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BPM

Crate

Analog Front End and Calibrator ADC IOC

(CPU)EVR

(Timing)

Channel Access Network

Calibrator Trigger

ADC Trigger

Timing Network

Crate Controller

(MCH)

ADC Clock

Utility Network (crate management)

Fast Feedback (coming later; to be connected to MCH or CPU or network

card)

Up to 9 BPM processors per crate

Most network cable interconnects move to shelf backplane, eliminating external cables

From Zheqiao Geng

Prototype Board Complete, Under Test

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Analog Front End RTM Struck 125 MHz digitizer

From Zheqiao Geng

BPM chassis• Each has:

– 4 signal cables (unavoidable)– A trigger at beam time cable– A calibration trigger cable– An ethernet port for channel access– An ethernet port used to pass raw data at 120 Hz to

a VME IOC for processing as the internal CPU is too slow

– A serial connection to a terminal server to allow viewing of the IOC console

– A power cable to an ethernet controlled power strip so power can be cycled to perform a remote reset.

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From Tom Himel

BPM chassis

• This was a design kludged together from available parts in 4 months when originally planned design for LCLS failed.

• Was then propagated to 10 linac sectors as didn’t have time to do a proper redesign and wanted its improved analog performance.

• It works! Physicists are quite happy. But REALLY don’t want to propagate this again! Needs a design using a crate e.g. µTCA.

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From Tom Himel

BPM in µTCA• Each module has:

– 4 signal cables (unavoidable)– A trigger at beam time cable– A calibration trigger cable– An ethernet port for channel access– An ethernet port used to pass raw data at 120 Hz to

a VME IOC for processing as the internal CPU is too slow

– A serial connection to a terminal server to allow viewing of the IOC console

– A power cable to an ethernet controlled power strip so power can be cycled to perform a remote reset.

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On backplane

On backplane

PCIe on backplane to CPU

PCIe on backplane to CPU

Only CPU has one

IPMI handles this

From Tom Himel

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Selection of Review Charges and Answers

• Is μTCA.4 the right standard for the future instrumentation and controls at SLAC? – UTCA.4 appears to be one of a number of suitable

options for future accelerator instrumentation and accelerator controls at SLAC. Given the proper institutional commitment, uTCA.4 will work well.

• Where else is it used? – DESY, KEK evaluating, SLAC ICD evaluating, ESS

evaluating.

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Selection of Review Charges and Answers (cntd.)

• Is it becoming a wider standard? – Unclear.

• Has Industry become more involved with developing this standard? – Yes.

• Has the SLAC team appropriately evaluated alternatives? – Maybe.

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Selection of Review Charges and Answers (cntd.)

• Are there specific advantages or disadvantages to be expected in the future?– There are clear advantages to upgrading the

system to include FPGA connected ADCs and DACs.

• Is the μTCA.4 LLRF system sufficiently mature to be adopted by the LCLS-II Project? – Yes

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Selection of Review Charges and Answers (cntd.)

• What are the risks and how can they be mitigated? – There is a risk in making a decision too early. Some

more tests and time are required. – Grounding, cross talk & cable pickup have also

been identified as risks. There is a risk in the BPM design concerning the availability of a 250Mhz digitizer if required.

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Selection of Review Charges and Answers (cntd.)

• Given that our current systems in use including VME are all obsolescent to varying degrees in architecture and performance, what is the preferred platform for new machines that will serve a wide range of I&C needs for the next 20 or more years? – UTCA.4 is not appropriate for a wide range of I&C

needs.• If not μTCA.4, what would you recommend?

– There is not a single solution for a wide range of I&C needs.

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Other points from the discussions• ”COTS” is not well defined• uTCA.4 longevity is dependent on installed

base• Need for redundancy?• Need for performance: backplane speed,

power to slots?• Alternatives have benefits: ATCA, PXI, Linux-

boxes, Pizza-boxes

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PICMG

• Standards organisation• uTCA.4 is defined by PICMG

– SLAC, DESY are members– I recommend that ESS should become a member if we intende to use uTCA.4

• Access to standards documents• Access to guides ”best practices”• Cost: 2500 USD/year