SKIROC2 Silicon Kalorimeter Integrated Read-Out Chip Stéphane CALLIER, Christophe DE LA TAILLE, Frédéric DULUCQ, Gisèle MARTIN-CHASSARD, Nathalie SEGUIN-MOREAU
Feb 04, 2016
SKIROC2Silicon Kalorimeter Integrated Read-Out Chip
Stéphane CALLIER, Christophe DE LA TAILLE, Frédéric DULUCQ, Gisèle MARTIN-CHASSARD, Nathalie SEGUIN-MOREAU
SKIROC2 Vienna TWEPP11 2011, Sept 27th 2
ROC chips for ILC prototypes
SPIROC2Analog HCAL (AHCAL)(SiPM)36 ch. 32mm²
June 07, June 08, March 10
HARDROC2 and MICROROCDigital HCAL (DHCAL)(RPC, µmegas or GEMs)64 ch. 16mm²
Sept 06, June 08, March 10
SKIROC2ECAL(Si PIN diode)64 ch. 70mm²
March 10
ROC chips for technological prototypes: to study the feasibility of large scale, industrializable modules (Eudet/Aida funded)
Requirements for electronics Large dynamic range (15 bits) Auto-trigger on ½ MIP On chip zero suppress 108 channels Front-end embedded in detector Ultra-low power : 25µW/ch
Microroc: Poster ID-44Microroc: Poster ID-44
SKIROC2 Vienna TWEPP11 2011, Sept 27th 3
EUDET/AIDA ECAL technological prototype• « Imaging » calorimetry for « particle flow algorithm »
=> 30%/√E jet resolution– High granularity and segmentation of the calorimeters
• ECAL: Si W Calorimeter Active medium: SILICON SENSORS (WAFERS)
325µm thick Silicon Wafers => 26000e-/MIP ie 1MIP=4.2 fC
High granularity : 5.5x5.5 mm2
High segmentation => 45 000 cells with embedded electronics for the
technological prototype
• Final ECAL: 30 layers, 100 M channels– SKIROC2 embedded inside the detector– No (few) external components
• “stitchable” motherboards (Active Sensor Units)– Minimize connections between boards
• Low cost and industrialization are the major goal
W layer
ASIC
256 P-I-N diodes0.25 cm2 each
18 x 18 cm2 total area
Si wafers
COMMON READOUT: TOKEN RING Mode
SKIROC2 Vienna TWEPP11 2011, Sept 27th 4
Readout architecture common to all calorimeters and minimization of data lines & power
Daisy chain using token ring mode Open collector, low voltage signals Low capacitance lines
Acquisition A/D conv. DAQ IDLE MODEChip 0
Chip 1 Acquisition A/D conv. DAQ IDLE MODEIDLE
Chip 2 Acquisition A/D conv. IDLE MODEIDLE
Chip 3 Acquisition A/D conv. IDLE MODEIDLE
Chip 4 Acquisition A/D conv. IDLE MODEIDLE DAQ
1ms (.5%) .5ms (.25%) .5ms (.25%)
1% duty cycle 99% duty cycle
199ms (99%)
S w itc h edC ap ac ito r
Ar r ay
R eg is te r s
1 0 0 1
0 1 1 1
0 1 0 1
S h if tR eg is te r
D AQ
An alo g to D ig ita l C o n v er te r
S lo w s h ap er s ig n a l
Ac q u is it io n C o n v er s io n
R ead - O u t
T o p M an ag er
T D C r am p s ig n a l
SCA SCA in SK2 and Spirocin SK2 and Spiroc
5 ev
ents
3 ev
ents
0 ev
ent
1 ev
ent
0 ev
ent
Chip 0 Chip 1 Chip 2 Chip 3 Chip 4
Data bus
DAQ: Poster ID-109DAQ: Poster ID-109
SKIROC : ECAL readout
• SKIROC2 : Silicon Kalorimeter Integrated Read-Out Chip– 64 channels, AMS SiGe 0.35 µm, 70 mm2
– Very large dynamic range: • HG for 0.5-150 MIP, LG for 150-2500 MIP
– Auto-trigger, Analog storage, Digitization & Token-ring ReadOut
– Testability at wafer level
• Front End boards crucial element– Collab with LLR (Palaiseau) and Korea
SKIROC2 Vienna TWEPP11 2011, Sept 27th 5
PCB – FRONT
PCB – BACK ASU (Active Sensor Unit)
C detector with PCB ≈ 20 pF
SKIROC2 Vienna TWEPP11 2011, Sept 27th 6
SKIROC2 features
• Very low noise (0.4 fC = 2 500 e-) and very large dynamic range (2fC up to 10 pC) charge preamplifier
• 180ns shaping time Slow Shapers for charge measurement
• 2-bit shaping time adjustable Fast Shaper (50 to 100ns)
• 10-bit DAC for discriminator threshold , With 4-bit adjustment on each channel
• Analogue Memory depth : up to 15 events can be stored
• Trigger Discriminator for autotrigger on ½ MIP
• 8-bit adjustable delay to position the Hold signal
• Digitization of either time and charge or of both charges
SKIROC2 Vienna TWEPP11 2011, Sept 27th 7
SKIROC2 Analogue core
SKIROC2 Vienna TWEPP11 2011, Sept 27th 8
SKIROC2 digital features
• Common features with Hardroc & Spiroc (compatibility with any CALICE DAQ system)– Open Collector token-ring ReadOut– Multiplexed Slow Control & Probe– Redundancy on Data Out & Transmit On
signal lines– 2 switchable StartReadOut Inputs &
EndReadOut Outputs : - to prevent chip failure
• Very Complex Digital Part (~10% of the Die)– Manage Acquisition, Conversion, 15 SCA
control, RAM, I/Os…
SKIROC2 Vienna TWEPP11 2011, Sept 27th 9
SKIROC2 overviewSilikonKalorimeterIntegratedReadOutChip
• 64 Channels– Difficult layout: 1Mip=4fC,
digital activity
• 250 pads– 17 for test purpose only
• AMS 0.35 µm SiGe• Die size = 65 mm2
– 7.5 mm x 8.7 mm
SKIROC2 Vienna TWEPP11 2011, Sept 27th 10
SKIROC2:DC PreAmp, Fast and Slow Shapers
1,92
1,93
1,94
1,95
1,96
1,97
1,98
1,99
2
2,01
2,02
0 10 20 30 40 50 60
DC
(V
)
Channel
DC PreAmplifier SKIROC2
1,199
1,2
1,201
1,202
1,203
1,204
1,205
1,206
1,207
1,208
0 10 20 30 40 50 60
DC
(V
)
Channel
DC Fast Shaper SKIROC2
<>=1.969 V rms=1.5 mV
<>=1.204 V rms=1.5 mV
Out_PA: uniformity of the DC level
Out_FS: uniformity of the DC level
1
1,001
1,002
1,003
1,004
1,005
1,006
0 10 20 30 40 50 60
DC
(V
)
Channel
DC Slow Shaper Gain10 SKIROC2
0,997
0,998
0,999
1
1,001
1,002
1,003
0 10 20 30 40 50 60
DC
(V
)
Channel
DC Slow Shaper Gain1 SKIROC2
<>=1.003 V rms=1.04 mV
<>=1.000 V rms=1.00 mV
Out_SS10: uniformity of the DC level
Out_SS1: uniformity of the DC level
SKIROC2 Vienna TWEPP11 2011, Sept 27th 11
DAC Threshold Linearity
Slope 2.2 mV/DAC Unit, DNL ±1LSB INL= ±1.7LSB
SKIROC2 Vienna TWEPP11 2011, Sept 27th 12
SKIROC2 Analogue Simulations/Measurements
Qinj = 10 MIP
OR 64 (probe)
Qinj = 40 fC (10 MIP)
SIMULATIONSSIMULATIONS MEASUREMENTSMEASUREMENTS
Out_SS1
Out_FS
Out_FS
Out_PA
Out_SS1
Out_SS10
SKIROC2 Vienna TWEPP11 2011, Sept 27th 1322 April 2023 13
SKIROC2: Fast Shaper noise
Fast Shaper̴6
50mV/Mip
Fast Shaper̴6
50mV/Mip
rms noise= 5.3 mV ie 1/10 MIPS/N=10rms noise= 5.3 mV ie 1/10 MIPS/N=10
10 Mip10 Mip Cdetector ≈ 30 pF
1 Mip1 Mip
SKIROC2 Vienna TWEPP11 2011, Sept 27th 1422 April 2023 14
Trigger efficiency (1)
Pedestal
Qinj=10fC=2.6Mip
Qinj=3fC=0.8Mip
<>=177.5 ±2 DACU
<>=183 ±1.5 DACU
<>=220 ±1 DACU
SKIROC2 Vienna TWEPP11 2011, Sept 27th 1522 April 2023 15
Trigger efficiency (2)
5σ Noise limit
1 MIP ≈ 4fC1 MIP ≈ 4fC
« Real » Pedestal=167 DAC Units1 Mip ≈4 fC = 20 DAC UnitsNoise= 2 DAC UnitsMinimum Threshold= 5 σ noise= 0.5 Mip
SKIROC2 Vienna TWEPP11 2011, Sept 27th 1616
Linearity of the Charge Preamp
SIMULATIONSIMULATION
SCOPE MEASUREMENTSSCOPE MEASUREMENTS
2000 Mip2000 Mip
SKIROC2 Vienna TWEPP11 2011, Sept 27th 1717
Linearity of the Low Gain Shaper
MEASUREMENTS using SCA and internal ADC
Autotrigger ModeWith 1 MIP (4 fC) thresholdAutotrigger ModeWith 1 MIP (4 fC) threshold
2000 Mip = 8 pC
SKIROC2 Vienna TWEPP11 2011, Sept 27th 1818
Linearity of High Gain Shaper
MEASUREMENTS using SCA and internal ADCAutotrigger mode1 MIP ( 4fC) threshold
Noise = 630 µV1 Mip gives 5.7 mVS/N=9
Noise = 630 µV1 Mip gives 5.7 mVS/N=9
ss10@20 MipRms =1.16 ADC U=600µVss10@20 MipRms =1.16 ADC U=600µV
POWER PULSING
SKIROC2 Vienna TWEPP11 2011, Sept 27th 19
Requirement: 25 µW/ch with 0.5% duty cycle 500 µA for the entire chip
4 Power pulsing lines : analog, conversion, dac, digital Each chip can be forced on/off by slow control
Power pulsing: Bandgap + ref Voltages + master I: switched ON/OFF Shut down bias currents with vdd always ON
SK2 power consumption measurement: 123 mA x 3.3V ≈ 40 mW => 0.6 mW/ch
Acquisition 88 mA , 290 mW Duty Cycle =0.5%, 1.45 mW
Conversion 27.3 mA, 90 mW Duty Cycle =0.25%, 0.225 mW
Readout 8.0 mA, 26.4 mW Duty Cycle =0.25%, 0.066 mW
Skiroc2 power consumption with Power pulsing: 1.7 mW ie 27 µW/chSkiroc2 power consumption with Power pulsing: 1.7 mW ie 27 µW/chSkiroc2 power consumption with Power pulsing: 1.7 mW ie 27 µW/chSkiroc2 power consumption with Power pulsing: 1.7 mW ie 27 µW/ch
MeasurementsMeasurements
• SPIROC2 : Si PM Readout Chip– SIMILAR to SKIROC2– similar dynamic range0.1 pe – 2000 p.e. (1 pe. = 160 fC)– All backend similar– But different preamplifer, 36 channels
(0.36m)2 Tiles + SiPM + SPIROC (144ch)
SPIROC2/SKIROC2
With external triggerWith external trigger
With internal (auto) triggerAnd internal ADC
SKIROC2 Vienna TWEPP11 2011, Sept 27th 20
550 mm
1510 mm
Composite Partwith metallic inserts
(15 mm thick)
182,1 × 7.3 mm
182,1 × 9.4 mm
Thickness : 1 mm
FEV5
550 mm
EUDET/AIDA ECAL technological prototype (1)
SKIROC2 Vienna TWEPP11 2011, Sept 27th 21
Next steps towards a LC detector 2/3 final module size (partially equipped) 9 cm sensors Mechanical housing
15 Tungsten plates wrapped into carbon fibre 7mm thick detector slab slided into the alveola
1 tungsten core, 2 layers of detector + electronics on PCB
SKIROC2 Vienna TWEPP11 2011, Sept 27th 22
Front End Board Thickness ~1.1mm
Front End Board Thickness ~1.1mm
In each alveola: 2 layers of 1 to 7 Active Sensors Units (ASU)
1 ASU 1 kapton (HV bias of the PIN diodes) + 1 layer of PIN diodes+ 1 PCB with embedded SKIROC2+ 1 thermal drain (copper)
@LLR(Palaiseau)@LLR(Palaiseau)
7 A.S.U.~1500mm total
Interconnection by ACF(“Adhesive conductive film”)
EUDET/AIDA ECAL technological prototype (2)
SKIROC2 Vienna TWEPP11 2011, Sept 27th 23
PCB with embedded Chip
Pile-upTop GND cover layerC2 GND + Input chip signalC3 horizontal routing + DVDD + GNDC4 AVDDC5 GND + vertical routingC6 GND (pads signal shielding)C7 pads routingC8 GND (pads shielding)BOT PADS
Front End Board
(FEV board)
5 drilling sequences :- Laser C8-C9 120µ filled- Laser C7-C8 120µ- Mechanical C2-C8 200µ- Mechanical C1-C8 200µ- Mechanical C1-C9 (for PCB fastening)
PCB Thickness 1100 µm
SKIROC2 Vienna TWEPP11 2011, Sept 27th 24
FEV board
Devices bonded inside cavities, with total thickness below 1.2 mm
Bonding @CERNBonding @CERNBonding @CERNBonding @CERN
No external components
SKIROC2 Vienna TWEPP11 2011, Sept 27th 25
CONCLUSION
• Good performance of SKIROC2:– 0.5 Mip (2 fC) up to 2000 Mip (8 pC)
dynamic range– 0.1Mip noise (0.4 fC ie 2500 electrons),
minimum threshold 0.5 Mip, autotrigger mode
• Many fine measurements to be continued
• Test with FEV and sensors to be done at system level (power pulsing, DAQ)
• 3rd generation of ROC chips to be done 2012-2013 within the AIDA program.
1m2 Micromegas detector@LAPP Annecy1m2 Micromegas detector@LAPP Annecy
DAQ: Poster ID-109DAQ: Poster ID-109
Microroc: Poster ID-44Microroc: Poster ID-44
1 m3 RPC detector, 40 layersHardroc2: 37 000 channels1 m3 RPC detector, 40 layersHardroc2: 37 000 channels
@IPNL Lyon@IPNL Lyon
BACKUP SLIDES
SCA
SKIROC2 Vienna TWEPP11 2011, Sept 27th 27
CHANNEL <i>
T& H_ S e lC olu m n 0
T& H_ S e lC olu m n 1 4
out_trigger_ch<i>
Slow Sh. G1T & H _ S e lC o lu m n < j>
T& H < i > _ Se l C o l um n < 1 4 :0 >
12-bit TDC R am p
T & H _ S e lC o lu m n < j> R E A D _ c o lu m n < j>
S lo w sh a p ers ig n a l
Depth=15
Depth=15
Depth=15
out_sca_t
out_sca_lg
500 fF
out_sca_hg
out_t_delayed_<i>
R E A D _ c o lu m n < j>
R E A D _ c o lu m n < 1 4 >
TD C r a m ps i g n a l
Slow Sh. G10
Skiroc2V3d ig ital ce ll
Clk40MHzStartAcq Raz_Colu mn<14:0>
Read_Column<14:0>
OR64_t_delayed Sel_Colu mn<14:0>
Track_Hold cell 14
Track_Hold cell 0
R E A D _ c o lu m n < 0 >
500 fF
8-bi t Dela y Box :100ns to 300ns
Power pulsing lines timing
SKIROC2 Vienna TWEPP11 2011, Sept 27th 28
Power On Digital Module: POD
LV D SR ec eiver
Enab le C lo c kfo r A c q uis itio n and
C o nvers io n
C lk O ut
P o w e rO nD ig ita l
S ta rtR e a dO ut
E ndR e a dO ut
S ta rtR e a dO utInt
S ta rtL V D S
C lk in
Enab le C lo c kfo r
R ead o utR s tb
C lk in
C lk O ut
P O D m o dule
E na ble
E na ble C lo c k
SKIROC2 Vienna TWEPP11 2011, Sept 27th 29
POD module (“Clock-gating”) to handle for the 2 LVDS receivers clock (40 MHz and 5 Mhz) and save power:
Starts and stops the Clocks, switches OFF LVDS receivers bias currents
2 others LVDS receivers (RazChn/NoTrig and ValEvt) active during PowerOnAnalog (during bunch crossing)
A c q uis itio n C o nvers io n R ead o ut (99% tim e)P has es
P o w erO nIntC hip 1
P o w erO nIntC hip 2
P o w erO nIntC hip N
Power On Digital Sequence
SKIROC2 Vienna TWEPP11 2011, Sept 27th 30
S ta r tC onv_ b
S ta r tA c qt
S ta r tR e a d-O ut
C hip_ S a t
E ndR e a d_ O ut
A c q u is it io n C o n v e rs io n R e ad -O u t
R e s e tb
P ow e rO nD igita l
Clo
ckSt
art
Clo
ckSt
art
C alib rate d(L V D S s tart t im e )
F ro m D A Q
F ro m d ais y c h ain
F ro m A S IC
G e ne ra te dS R O
F ro m P O D
Clo
ck S
topp
ed
Clo
ck S
topp
ed
• End of Conversion: clock stopped as not needed and LVDS receivers bias switched OFF• Readout: Start ReadOut signal generated by the POD and stands for a PwrOnD => starts
LVDS receivers and Clk.• End of the ReadOut: The chip generates a EndRout signal which will be used by the next
chip in the daisy chain to be read out.
SKIROC2 Vienna TWEPP11 2011, Sept 27th 31
SKIROC2 One channel block scheme
1MΩ
0 3pF
Preamp.Input
10MΩ
3pF
Calib.Input
10-bit dual DAC – common to 64 channels
Analog Memory
Depth = 15
Analog Memory
Depth = 15
12-b
it A
DC
(Wilk
inso
n)
Trigger out
ChargeMeas.
Gain selection
Slow shaper
Gain 10
Tp=180ns
Slow shaper
Gain 1
Tp=180ns
Amplifier
Gain 10
fast shaper
Gain XX
Tp=adj
4-bit DACadjustment
• SPIROC• SKIROC• HARDROC• PARISROC
• New…
MEMORY MAPPING of the ROC CHIPs
SKIROC2 Vienna TWEPP11 2011, Sept 27th 32
0
0
E ve ntn°1
634
2431
C hip ID (8 b it) B unc h C ros s ing ID (24 b it)C hn 48 (M S B ) to C hn 63 (L S B )C hn 32 (M S B ) to C hn 47 (L S B )C hn 16 (M S B ) to C hn 31 (L S B )C hn 0 (M S B ) to C hn 15 (L S B )E 0 E 1
5
C hip ID (8 b it) B unc h C ros s ing ID (24 b it)C hn 48 (M S B ) to C hn 63 (L S B )C hn 32 (M S B ) to C hn 47 (L S B )C hn 16 (M S B ) to C hn 31 (L S B )C hn 0 (M S B ) to C hn 15 (L S B )
E ve ntn°2
C hip ID (8 b it) B unc h C ros s ing ID (24 b it)C hn 48 (M S B ) to C hn 63 (L S B )C hn 32 (M S B ) to C hn 47 (L S B )C hn 16 (M S B ) to C hn 31 (L S B )C hn 0 (M S B ) to C hn 15 (L S B )
E ve ntn°127
630
E 0 E 1E 0 E 1E 0 E 1
E 0 E 1
E 0 E 1E 0 E 1E 0 E 1
E 0 E 1
E 0 E 1E 0 E 1E 0 E 1
E 0 E 1
E 0 E 1E 0 E 1E 0 E 1
E 0 E 1
E 0 E 1E 0 E 1E 0 E 1
E 0 E 1
E 0 E 1E 0 E 1E 0 E 1
• HARDROC2: 127 events on 2 bits for 64 channels. Maximum of stored data is 20320 bits
• No conversion• Readout worst case: 200 nsx20k=4 ms/ Full Chip (WORST case)
• SPIROC2: 16 events, 36 channels. 12 bits ADC for time and charge => max stored data= 18707 bits
• Conv.: max time (Full chip)= 16 SCA x 2 (HG or LG/Time) x103 µs=3.2ms
• RO: 3.8 ms/Full Chip (Worst case)
C hip ID (8 b it)B unc h C ros s ing ID (12 bit)B unc h C ros s ing ID (12 bit)
T im e m e a s ure C hn 0 (12 bit)
C ha rge m e a s ure C hn 0 (12 bit)
B unc h C ros s ing ID (12 bit)
T im e m e a s ure C hn 35 (12 bit)
C ha rge m e a s ure C hn 35 (12 bit)
0 0 0 00 0 0 0
0 0 0 00 0
0 00 0
0 0
HG
HGHG
HG
H it (1 b it)G a in (1 b it)
0
0715
16B C ID s
36T im e s
36C ha rge s
S C AC olum n 0
0 0
0 00 0
0 0
HG
HGHG
HG
36T im e s
36C ha rge s
S C AC olum n 15
T im e m e a s ure C hn 0 (12 bit)
C ha rge m e a s ure C hn 0 (12 bit)T im e m e a s ure C hn 35 (12 bit)
C ha rge m e a s ure C hn 35 (12 bit) 1168
• SKIROC2: 15 events, 64 channels. 12 bits ADC for time and charge => max stored data= 30976 bits
• Conv.: max time (Full chip)= 15 SCA x2 (HG or LG/Time) x103 µs= 3 ms
• ReadOut: 6 ms/Full Fhip (Worst case)
A c quis ition C onve rs ion R e a d-O ut A c quis ition
B unc h C ros s ing T ra in
T im e
D igita l P a r tP ha s e s
B unc h C ros s ing T ra in
Physics simulation: 2 or 3 SCA are enough
DAISY CHAIN: Main signals
SKIROC2 Vienna TWEPP11 2011, Sept 27th 33
COMMON to all the ROC chips StartAcq
Start acquisition, generated by DAQ
StartReadout: Generated by DAQ, start of the readout
EndReadout Generated by chip, End of the readout
ChipSat (Open Collector signal): Generated by chip, « 1 »: digital memory is full or acq is
finished
Dout: data out (OC signal)
TransmitOn (OC signal) Generated by chip, Data out are transmitted
Buffers integrated for OC signals
No conversion in Hardroc
34
• Reception of the Slow Control parameters from a PC and transmission to the ASICs, launch acquisition, perform analog/digital readout and send all the data received from ASICs to a PC.
• Communication – with other DIFs– with DAQ either by USB or by HDMI
• The DIF should be able to handle more than 100 ASICs theoretically. The max which has been tested is 48
• Regulators + Decoupling capacitors located on the DIFRegulators + Decoupling capacitors located on the DIF
INTERFACE DAQ-ROC= DIF board
@LAPP@LAPP
SKIROC2 Vienna TWEPP11 2011, Sept 27th
SKIROC2 Vienna TWEPP11 2011, Sept 27th 35
Technological prototype : ECAL module
• Front-end ASICs embedded in detector– Very high level of integration– Ultra-low power with pulsed mode– 0.35 µm SiGe technology
• All communications via edge– 4,000 ch/slab, minimal room, access, power– small data volume (~ few 100 kbyte/s/slab)
• « Stitchable motherboards »
Elementary motherboard ‘stitchable’ 24*24 cm ~500 ch. ~8 FE ASICS1 FEV= 4 wafers 9X9 cm2 = 4x4 chips skiroc2 64 ch => 1024 pads.