SIUE SAMPLE Final Examination Cover · PDF file · 2017-10-24SIUE SAMPLE Final Examination Cover Sheet MS Degree in Electrical Engineering Name ... Exam results Total score received

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SIUE SAMPLE Final Examination Cover Sheet MS Degree in Electrical Engineering

Name: ________________________________________________________________

ID Number: ___________________________________________________________

Contact information: __________________________________________________

_______________________________________________________________________

Indicate the two areas you select:

Subject area 1: _____________________________________

Subject area 2: _____________________________________

Exam results

Total score received: _______________out of 25 pts. Recommendation: PASS / FAIL (circled).

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TABLE OF CONTENTS Instructions For MS EE Final Written Examination................................................................................... 3

ECE Master’s Exit Exam Communications ........................................................................................... 4

ECE Master’s Exit Exam Computer Architecture ................................................................................. 7

ECE Master’s Exit Exam Computer Vision & Image Processing ....................................................... 10

ECE Master’s Exit Exam Control Systems ......................................................................................... 13

ECE Master’s Exit Exam Digital Signal Processing ........................................................................... 16

ECE Master’s Exit Exam Networking ................................................................................................. 19

ECE Master’s Exit Exam Power Systems ........................................................................................... 22

ECE Master’s Exit Exam Signal Theory & Stochastic Processes ....................................................... 25

ECE Master’s Exit Exam VLSI Design ............................................................................................... 28

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Instructions For MS EE Final Written Examination

This exam is composed of questions in the following subject areas:

1. Communications 2. Computer Architecture 3. Computer Vision and Image Processing (CVIP) 4. Control Systems 5. Digital Signal Processing (DSP)] 6. Networking 7. Power Systems 8. Signal Theory and Stochastic Processes 9. VLSI Design

Choose two subject areas from the list above. The choice of problems is restricted to only two

areas. Clearly indicate your selected subject areas by writing them in the appropriate place on the

cover sheet.

Solve 5 problems total. The problems must come from the two selected subject areas.

Do NOT work on back of pages, use extra pages if necessary, write the subject area, problem

number and your name at the top of each page

If any solutions require more than one page, number the pages for your answers, starting with

page ‘1’ for each problem.

This is an open books and notes exam

The exam is 1 hour and 50 minutes

After completed, put only the cover sheet and the problems you worked clipped together, put any

unused problems, etc, in the second stack of papers

o Grades will be based on written evidence in the submitted work.

o Full credit will be given for professional work only: clear, concise, simple, and as

complete as possible.

o Always show your work. Answers without sufficient supporting work will be awarded

zero score.

o If you provide multiple answers to a problem that has a unique solution, only one of your

solutions will be picked for grading: top-most or left-most, not necessarily the correct

one.

o Be sure to read the problems carefully, there will be no credit for solutions to misread

problems.

o Measurement units are considered an important part of the answer. Answers given with

incorrect units or unit prefixes may be considered wrong even if the numeric part is right.

o Every problem will be graded on a scale of 0-5 with 5 being the best. A score of 15 is

needed to pass the exam.

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ECE Master’s Exit Exam Communications

#1) A baseband OOK receiver uses a Gaussian Filter with a 3-dB bandwidth of 0.75MHz. The Signal-

to-Noise ratio at the output of the Gaussian filter is 2.2 dB lower than that of an ideal Matched Filter.

The signal input to the filter is a rectangular pulse with a pulse width of 1 s and an amplitude of 0.02 v.

The noise input to the filter is Additive White Gaussian Noise with a power spectral density of 10-10

w/Hz.

Find the bit error probability.

Gaussian

Filter

OOK Decision

Circuit

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#2). A transmitter uses only 4 transmitted code words as follows

01010101

10101010

11110000

00001111

(a)Find the maximum number of bit errors a decoder can correct.

(b)Find the maximum number of bit errors a decoder can detect.

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#3) The input signal to the filter is )t2cos()t(x .

The transfer function of the filter is 21

1)(H

Find the average power of the output y(t) of the filter.

Filter x(t) y(t)

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ECE Master’s Exit Exam Computer Architecture

#1) Before a pipeline is added, the propagation delay through the combinational logic to perform a task

was measured as tpd = 240 ns. There is a register before and a register after the combinational logic

block. The setup time of a register is 5 ns and the propagation delay through a register is also 5 ns.

a) What is the maximum frequency of the clock for the circuit described above?

b) A 3 segment pipeline is used where the delays through each of the segments are as follows: t1 = 80

ns, t2 = 100 ns, t3 = 60 ns. The registers used in the pipeline are the same as those used above. Sketch

the pipelined circuit.

c) What is the maximum frequency of the clock now?

d) What is the speedup factor, S, if 100 tasks are performed?

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#2) What is it about the nature of computer programs that make the implementation of virtual memory

concepts possible. Why do modern systems make use of the concept of virtual memory?

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#3) A finite-state machine has 2n possible states. At each clock pulse, it reads in a k-bit symbol, emits an

m-bit output symbol (including feedback bits), and switches to a new state. The symbol emitted and the

new state depend on the current state and the input symbol.

a) Draw a block diagram indicating how the machine can be implemented using a ROM. Explain your

diagram.

b) Determine how big the ROM must be. Explain.

c) A non-pipelined processor has a microcode-based controller implemented as a finite-state machine of

the sort indicated above. Explain what the states, the k-bit input symbol, and the m-bit output symbol

correspond to in this context. How is the instruction processing accomplished?

d) A given processor has an instruction set containing 16 instructions. The average CPI (clocks per

instruction) when the cache hit probability is 100%, is 5. Determine the required size of the ROM.

Explain how you arrived at your answer, and state any assumptions you have made.

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ECE Master’s Exit Exam Computer Vision & Image Processing

#1) Let the rows of the following matrix represent basis vectors.

a) Are they in sequency order? Why or why not?

b) Are they orthogonal? Why or why not?

c) Are they orthonormal? Why or why not?

d) What is the name of these basis vectors?

1 1 1 1

1 -1 -1 1

1 -1 1 -1

1 1 -1 -1

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#2) Given the following image and structuring element, perform an opening operation. Assume

the origin of the structuring element is in the center. Ignore cases where the structuring element

extends beyond the image.

STRUCTURING ELEMENT

010

111

010

IMAGE

1 1 1 1 1 1 1

1 1 0 1 1 1 1

1 1 1 1 1 1 1

0 0 0 0 0 0 0

1 1 0 0 1 1 1

0 1 0 0 0 0 0

1 1 1 1 1 1 1

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#3) An imaging system has a lens with a diameter of 50mm and a focal length of 10mm. The

system is setup so that objects at a distance of 3.0 meters are correctly focused. Quantitatively

and qualitatively describe how an object at 2.0 meters appears in the image. Assume that the

imaging device is a CCD with round pixel elements that have a 0.1mm diameter.

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ECE Master’s Exit Exam Control Systems

#1) Given a second-order control system

.2

)(22

2

nn

n

sssG

a. The closed-loop poles have a damping ration of 0.5 and the step response peak time of

.3

3 Determine the undamped natural frequency n .

b. Calculate the rise time, the settling time with 2% criterion, and the maximum overshoot.

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ECE Master’s Exit Exam Control Systems #2) Given the open-loop transfer function for a unity-feedback system as

.)1(

1)(

sssG

a. Draw the root locus plot of G(s).

b. Determine a value of a proportional controller K such that the damping ratio of the

dominant closed-loop poles is equal to .2/2

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ECE Master’s Exit Exam Control Systems #3) Given the following differential equation:

).()()(2)(2

2

tutytydt

dty

td

d

a. Assume the initial conditions are zero, i.e. y(0)=0, 0)0( y , write down the transfer

function G(s)=Y(s)/U(s).

b. If the input is a unit-step function, what is the output signal y(t) of this system?

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ECE Master’s Exit Exam Digital Signal Processing

#1) A causal, linear, time-invariant, discrete-time system H with input xn and output yn is

described by the difference equation:

yn = 0.9 yn-1 – 0.81 yn-2 + xn + xn-2

a) Determine the transfer function H(z) for this system.

b) Sketch the pole-zero diagram for this system.

c) Sketch the magnitude and the phase of the frequency response H(ejw

), for 0 < w < π

d) Determine the output sequence yn for the input sequence xn :

sn'other allfor

4 n if.

3 ,n if.

2 n if

0

810

90

1

xn

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#2) Let {s(nT), -∞ < n < ∞, n an integer} denote equi-spaced samples, taken once each T

seconds, of an analog signal s(t). This signal is not necessarily band-limited. Denote the Fourier

transform of this signal by S(f), where:

).()()( tdetsfS ft2j

a) Prove that if s(nT) = δ(nT) then:

k

1T

kfS

T

1.

Carefully state any assumptions that you make, and show all the details in your proof.

b) Prove the converse to part a). That is, prove that if

k

1T

kfS

T

1.

Then s(nT) = δ(nT).

c) Give an explicit example (via either an equation or a carefully labeled graph) of a signal s(t)

that is not band-limited and has a Fourier transform satisfying:

k

1T

kfS

T

1.

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#3) Give a clear but brief (1 to 3 sentence) answer to each of the following 10 questions.

1. What is the relationship, if any, between the discrete Fourier transform (DFT) and a fast

Fourier transform (FFT)?

2. What is the relationship between a discrete-time, linear system that is causal and the unit

circle in the complex z-plane associated with the z-transform of its unit-sample response?

3. Describe the region of convergence of the z-transform of the unit-sample response of a

discrete-time, linear system that is stable.

4. What does it mean to design a discrete-time filter to correspond to a continuous-time filter

when the principle of “impulse-invariance” is used?

5. State the Nyquist sampling theorem.

6. Describe the input-output characteristic of an ideal b-bit uniform quantizer.

7. What is Gibbs’ phenomenon?

8. What is the definition of a linear system?

9. What is aliasing?

10. Comment on general characteristics of Butterworth filters.

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ECE Master’s Exit Exam Networking

#1) a) For the following IP Address -Subnet Mask pair, what is the address class, subnet number,

and host number on that subnet.

IP Address: 146.163.137.66

Subnet Mask: 255.255.255.192

– Address class:

– Subnet number:

– Host number:

b) The output of a netstat -n command produces the following:

Local Address Remote Address Swind Send-Q Rwind Recv-Q State

146.163.130.29.111 146.163.130.54.659 8760 0 8760 0 ESTABLISHED

146.163.130.29.513 146.163.5.29.1020 8760 0 8760 0 CLOSE_WAIT

146.163.130.29.59119 128.174.5.14.21 16384 0 9216 0 ESTABLISHED

146.163.130.29.23 140.175.18.243.1026 7691 0 8760 0 ESTABLISHED

Identify the destination and well-known-port service name as well as the source and the

dynamically allocated port number for the 4 entries listed above.

c) The output of the netstat -rn command produces the following:

bnoble@cougar> netstat -rn

Routing Table:

Destination Gateway Flags Ref Use Interface

127.0.0.1 127.0.0.1 UH 0 776144 lo0

146.163.5.0 146.163.5.29 U 3 5640 hme0

224.0.0.0 146.163.5.29 U 3 0 hme0

default 146.163.5.254 UG 0 660546

– What gateway will this host use to talk to a host with IP 146.163.5.1?



– What gateway will this host use to talk to itself?

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#2) Suppose you are a network engineer of a moderately large network connected to the Internet

and all of the systems are running some variant of UNIX. You are sitting at your terminal when a

user comes to you complaining that his system doesn’t connect to anything anymore. This user

has root access on his system and from previous experience, you know that he likes to meddle

with the system configuration files. His system is attached to the 146.163.140.0/24 subnet. You

go to his system and type ’ifconfig -a’ and get:

ep0:flags=8863<UP,BROADCAST,NOTRAILERS,RUNNING,SIMPLEX,MULTICAST>

inet 146.163.200.86 netmask 0xfffffff0 broadcast 146.163.130.255

lo0: flags=8009<UP,LOOPBACK,MULTICAST>

inet 127.0.0.1 netmask 0xff000000

Based on this information, identify all the different ways this bozo has screwed up his system’s

network configuration. Be specific!

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#3) Modifications to the congestion avoidance algorithm were proposed in 1990. Before

describing the change, realize that TCP may generate an immediate acknowledgment (a

duplicate ACK) when an out-of-order segment is received. This duplicate ACK should not be

delayed. The purpose of this duplicate ACK is to let the other end know that a segment was

received out of order, and to tell it what sequence number is expected.

Since TCP does not know whether a duplicate ACK is caused by a lost segment or just a

reordering of segments, it waits for a small number of duplicate ACKs to be received. It is

assumed that if there is just a reordering of the segments, there will be only one or two duplicate

ACKs before the reordered segment is processed, which will then generate a new ACK. If three

or more duplicate ACKs are received in a row, it is a strong indication that a segment has been

lost. TCP then performs a retransmission of what appears to be the missing segment, without

waiting for a retransmission timer to expire.

Although it seems that timers aren’t needed anymore, give the most important reason

why this duplicate ACK mechanism doesn’t catch all lost packets; i.e., why does TCP still

require the use of timers.

22

ECE Master’s Exit Exam Power Systems

#1) Discuss a few advantages (at least three) of installing a capacitor bank in the electrical power

systems

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#2) a) Derive the approximate voltage drop equation [VD = I*(Rcos + Xsin)]

b) Explain how it is used in the power distribution network.

You can use a simple example to show how it works.

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#3) . The open- and short-circuit tests for a three-phase 13.2KV/440V, 800 KVA transformer

give the following data.

* OCT: P = 100W, I = 0.3 A, V = rated low-side voltage

* SCT: P = 2000W, V = 36 V, I = high-voltage side full load current

Determine the equivalent circuit of the transformer referred to the low voltage

side (Assume r1 = r2’ and x1 = x2’)

25

ECE Master’s Exit Exam Signal Theory & Stochastic Processes

#1) A nonstationary random process is defined as ],[][ nUanXn

where 0 < a < 1 and U[n] is

WGN with variance .2

U

a. Find the mean and covariance sequences of X[n].

b. Transform the X[n] random process to make it stationary?

26


#2) A “white” uniform random process is defined to be an IID random process with

3 ,3~][ UnX for all n. Determine the mean and covariance sequences for this random

process and compare them to those of the WGN random process.

27


#3) For the moving average random process defined as

]1[][2

1][ nUnUnX , n

determine P[[X] > 3] and compare it to P[U[n] > 3].

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ECE Master’s Exit Exam VLSI Design

#1) Increasing the width-to-length ratio of a FET will reduce the timing resistance of the

FET. One might incorrectly assume that this will always reduce propagation delay.

Explain under what set of circumstances this is true and under what conditions increasing

the width to length ratio is likely to do little to improve

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#2) Draw a 2-input NAND gate. All FETS should be minimum size

i.e. 0.36 microns wide and 0.25 microns long.

What is the propagation delay, tPHL, of the above circuit if

the timing resistance of a NFET is 2 K / W and the timing

resistance of a PFET is 5 K / W. Assume that the

capacitance at every node in the circuit is 25 fF. W is

the width of the transistor. The length is 0.25 microns.

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#3) Determine device for the FETs described below. Use the

agreed upon process parameters.

Vdd = 2.5 Volts

Vds,vsat = saturation voltage due to velocity saturation =

0.65 volts for NFETs and -3 volts for PFETs. (Assumes L =

0.25 m)

Length of all FETS is 0.25 m.

Threshold voltage of NFET is +0.5 Volts.

Threshold voltage of PFET is -0.5 Volts.

Transconductance parameter of NFET, KPN, is 230 A/V2

Transconductance parameter of PFET, KPP, is 50 A/V2

Neglect both channel length and bulk modulation effects

i.e. = 0 and = 0. Assume in each case the width of the

FET is 1 m.

a) What is Ids for a NFET whose gate voltage is 2.5 Volts,

drain voltage is 1.25 volts, and source voltage is 0

volts?

b) What is ISD for a PFET whose gate voltage is 2.5 Volts,

source voltage is 2.5 volts, and drain voltage is 1.5

volts?

SIUE SAMPLE Final Examination Cover · PDF file · 2017-10-24SIUE SAMPLE Final Examination Cover Sheet MS Degree in Electrical Engineering Name ... Exam results Total score received

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