(single-clock FIFO / 2-clock) FIFO. · It is _____ (possible / not possible) to have WP = 000001 (=1) and RP = 111111 (=63). It is _____ (possible / not possible) to have WP = 111111

May 9, 2015 12:05 am EE254L Final - Spring 2015 9 / 11 C Copyright 2015 Gandhi Puvvada

3 ( 6 + 6 + 12 + 8 + 8 = 40 points) 35 min. FIFO

3.1 We can use _____________ (n-bit / (n+1)-bit) pointers either in the single-clock FIFO or in the 2-clock FIFO where as we can use _______________ (n-bit / (n+1)-bit) pointers only in the _______________________ (single-clock FIFO / 2-clock) FIFO.

3.2 For a 32-location deep FIFO, when do you do mod-32 as shown in [(WP-RP)mod32] and when do you do mod-64 as shown in [(WP-RP)mod64]? ____________________________________ ________________________________________________________________________________________________________________________________________________________

3.3 A new EE254L TA, Mr. Bruin, simulated a FIFO design submitted by the student, Mr. Trojan, and captured the 6-bit RPSS (RP

double synchronized to Wclk) activity for a 32-location FIFO in a modelsim waveform along with the 6-bit WP and the Wclk, and displayed the values of WP and RPSS in decimal as shown above. Since the RPSS was jumping as shown below, he concluded that Mr. Trojan’s design is bad. Please educate Mr. Bruin. ___________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________

3.4 We need to add Data 1 (D1) produced by Producer P1 and Data 2 (D2) produced by Producer P2 and convey the Sum 3 (S3) to Consumer C3. The two producers and the single consumer work at their own individual clocks P1clk, P2clk, and C3clk. Also they are all busy with various other things. So we need 3 FIFOs, one to collect a series of D1 data, and another to collect a series of D2 data. We produce a series of sums S3 and leave in a third FIFO for the consumer C3 to consume from. Complete the design below by producing REN1, REN2, and WEN3 taking into consideration the Full and Empty signals as appropriate from the three FIFOs. If D1out is ready as indicated by (____________) and D2out is ready as indicated by (____________), and further S3in can be successfully deposited in the 3rd FIFO as indicated by (____________), then we activate all three control signals REN1, REN2, and WEN3. Draw the logic below. The adder circuit is a timing path in the ______ (P1clk/P2clk/C3clk) clock domain. _

6pts

6pts

WclkRPSSWP

59

22 23

195

12pts

8pts

8pts

D1inWEN1

Full1P1clk

D1outREN1

Empty1C3clkFIFO_1

D2inWEN2

Full2P2clk

D2outREN2

Empty2C3clkF

IFO_2

S3inWEN3

Full3

C3clk

S3outREN3

Empty3

FIFO_3D1

D2S3

Adder

May 9, 2015 12:05 am EE254L Final - Spring 2015 9 / 11 C Copyright 2015 Gandhi Puvvada

3 ( 6 + 6 + 12 + 8 + 8 = 40 points) 35 min. FIFO

3.1 We can use _____________ (n-bit / (n+1)-bit) pointers either in the single-clock FIFO or in the 2-clock FIFO where as we can use _______________ (n-bit / (n+1)-bit) pointers only in the _______________________ (single-clock FIFO / 2-clock) FIFO.

3.2 For a 32-location deep FIFO, when do you do mod-32 as shown in [(WP-RP)mod32] and when do you do mod-64 as shown in [(WP-RP)mod64]? ____________________________________ ________________________________________________________________________________________________________________________________________________________

3.3 A new EE254L TA, Mr. Bruin, simulated a FIFO design submitted by the student, Mr. Trojan, and captured the 6-bit RPSS (RP

double synchronized to Wclk) activity for a 32-location FIFO in a modelsim waveform along with the 6-bit WP and the Wclk, and displayed the values of WP and RPSS in decimal as shown above. Since the RPSS was jumping as shown below, he concluded that Mr. Trojan’s design is bad. Please educate Mr. Bruin. ___________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________

3.4 We need to add Data 1 (D1) produced by Producer P1 and Data 2 (D2) produced by Producer P2 and convey the Sum 3 (S3) to Consumer C3. The two producers and the single consumer work at their own individual clocks P1clk, P2clk, and C3clk. Also they are all busy with various other things. So we need 3 FIFOs, one to collect a series of D1 data, and another to collect a series of D2 data. We produce a series of sums S3 and leave in a third FIFO for the consumer C3 to consume from. Complete the design below by producing REN1, REN2, and WEN3 taking into consideration the Full and Empty signals as appropriate from the three FIFOs. If D1out is ready as indicated by (____________) and D2out is ready as indicated by (____________), and further S3in can be successfully deposited in the 3rd FIFO as indicated by (____________), then we activate all three control signals REN1, REN2, and WEN3. Draw the logic below. The adder circuit is a timing path in the ______ (P1clk/P2clk/C3clk) clock domain. _

6pts

6pts

WclkRPSSWP

59

22 23

195

12pts

8pts

8pts

D1inWEN1

Full1P1clk

D1outREN1

Empty1C3clkFIFO_1

D2inWEN2

Full2P2clk

D2outREN2

Empty2C3clkF

IFO_2

S3inWEN3

Full3

C3clk

S3outREN3

Empty3

FIFO_3D1

D2S3

Adder

EE354L_Final_Fall2015.fm

December 14, 2015 3:04 am EE354L Final - Fall 2015 6 / 9C Copyright 2015 Gandhi Puvvada

6 ( 39 points) 25 min. FIFOs

6.1 A change in depth of the FIFO ___________ (will / will not) cause a change in the pin-out of the FIFO because _____________________________________________________________________________________________________________________________________________

6.2 If WP = 5 and RP =1, the depth is ________ if the FIFO is a 16-location FIFO, and is ________ if the FIFO is a 64-location FIFO.If WP = 1 and RP =5, the depth is ________ if the FIFO is a 16-location FIFO, and is ________ if the FIFO is a 64-location FIFO.

6.3 Consider an 32-location 2-clock FIFO using 6-bit counters (in place of 5-bit counters) for the WP and RP pointers. If the producer is much faster, then the FIFO will be running FULL most of the time. So WP may be 100000 (=32) and RP may be 000000 (=0) for quite some time and then finally the consumer consumes one item and in no time, the producer replenishes (fills the FIFO). Then the WP will be 100001 (=33) and RP will be 000001 (=1) for some time. However sometimes the producer may be busy and it is possible that WP is 111110 (=62) and RP is 111101 (=61).It is _____________ (possible / not possible) to have WP = 000001 (=1) and RP = 111111 (=63).It is _____________ (possible / not possible) to have WP = 111111 (=63) and RP = 000001 (=1) .For each of the above 2, if you said "possible", state the depth and if you said "not possible" state your reason. Also state whether you do MOD_32 or MOD_64 subtraction here.____________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________

6.4 Never ever synchronize by sampling and holding (circle all applicable):(a) a single-bit data item(b) a multi-bit data item where multiple bits could be changing simultaneously(c) a multi-bit data item where one bit at most changes at any time(d) none of the above

6.5 It is ___________________ (necessary/not necessary) that the WP and RP are initialized to zero-zero only and nothing else. It ____________ (is / isn’t) fine if they are both initialized to say two-two.

6.6 Deadlock can be created if the FIFOs are _____________ (shallow / deep) and if the frequencies of the producer and consumer are ___________________________________ (nearly the same / orders of magnitude different) and used ____________________________________________ [n-bit pointers for 2n-location FIFO / (n+1)-bit pointers for 2n-location FIFO]. Deadlock will never occur irrespective of how deep is the FIFO, how different are the frequencies if we use __________________ [n-bit / (n+1)-bit] pointers for a 2n-location FIFO.

6.7 Gray code counters are wasteful but not harmful in _____________________________ (single-clock / two-clock / both / neither) FIFO. The 16-bit Gray code 1010_1010_0110_1110 represents an _______ (odd / even) decimal number. The 16-bit Binary code 1010_1010_0110_1110 represents an ______ (odd / even) decimal number.

3pts

6pts

10pts

4pts

4pts

8pts

4pts

EE354L_Final_Fall2015.fm

December 14, 2015 3:04 am EE354L Final - Fall 2015 6 / 9C Copyright 2015 Gandhi Puvvada

6 ( 39 points) 25 min. FIFOs

6.1 A change in depth of the FIFO ___________ (will / will not) cause a change in the pin-out of the FIFO because _____________________________________________________________________________________________________________________________________________

6.2 If WP = 5 and RP =1, the depth is ________ if the FIFO is a 16-location FIFO, and is ________ if the FIFO is a 64-location FIFO.If WP = 1 and RP =5, the depth is ________ if the FIFO is a 16-location FIFO, and is ________ if the FIFO is a 64-location FIFO.

6.3 Consider an 32-location 2-clock FIFO using 6-bit counters (in place of 5-bit counters) for the WP and RP pointers. If the producer is much faster, then the FIFO will be running FULL most of the time. So WP may be 100000 (=32) and RP may be 000000 (=0) for quite some time and then finally the consumer consumes one item and in no time, the producer replenishes (fills the FIFO). Then the WP will be 100001 (=33) and RP will be 000001 (=1) for some time. However sometimes the producer may be busy and it is possible that WP is 111110 (=62) and RP is 111101 (=61).It is _____________ (possible / not possible) to have WP = 000001 (=1) and RP = 111111 (=63).It is _____________ (possible / not possible) to have WP = 111111 (=63) and RP = 000001 (=1) .For each of the above 2, if you said "possible", state the depth and if you said "not possible" state your reason. Also state whether you do MOD_32 or MOD_64 subtraction here.____________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________

6.4 Never ever synchronize by sampling and holding (circle all applicable):(a) a single-bit data item(b) a multi-bit data item where multiple bits could be changing simultaneously(c) a multi-bit data item where one bit at most changes at any time(d) none of the above

6.5 It is ___________________ (necessary/not necessary) that the WP and RP are initialized to zero-zero only and nothing else. It ____________ (is / isn’t) fine if they are both initialized to say two-two.

6.6 Deadlock can be created if the FIFOs are _____________ (shallow / deep) and if the frequencies of the producer and consumer are ___________________________________ (nearly the same / orders of magnitude different) and used ____________________________________________ [n-bit pointers for 2n-location FIFO / (n+1)-bit pointers for 2n-location FIFO]. Deadlock will never occur irrespective of how deep is the FIFO, how different are the frequencies if we use __________________ [n-bit / (n+1)-bit] pointers for a 2n-location FIFO.

6.7 Gray code counters are wasteful but not harmful in _____________________________ (single-clock / two-clock / both / neither) FIFO. The 16-bit Gray code 1010_1010_0110_1110 represents an _______ (odd / even) decimal number. The 16-bit Binary code 1010_1010_0110_1110 represents an ______ (odd / even) decimal number.

3pts

6pts

10pts

4pts

4pts

8pts

4pts

EE354L_Final_Spring2016.fm

May 9, 2016 2:02 am EE354L Final - Spring 2016 5 / 6C Copyright 2016 Gandhi Puvvada

4 ( 4 + 16 + 8 + 8 + 8 + 4 = 48 points) 35 min. FIFOs

4.1 A change in width of the FIFO _______ (will / will not) cause a change in the pin-out of the FIFO.A change in depth of the FIFO _______ (will / will not) cause a change in the pin-out of the FIFO.

4.2 For an 8-location FIFO using 4-bit pointers for WP and RP some of the four situations (pairs of WP and RP) below namely ________ (#1, #2, #3, #4) is/are illegal. Among the remaining legal situations any one of them could be occurring before the other(s) as a FIFO is a circular buffer. T / F . Circle the populated locations for the legal situations and state the populated depth.

4.3 When we use (n+1)-bit pointers for WP[n:0] and RP[n:0] for a 2**n location FIFO, we use the ________ (lower/upper) n bits namely _____________ ([n-1:0]/[n:1]) to ________________________________ (index the array of locations/perform WP-RP to arrive at depth/both/neither).

4.4 For a 128-location deep FIFO, since populated depth can vary from completely empty to completely full, we have ________ (127/128/129) depth values and should be doing__ (a/b/c/d).(a) (WP-RP) mod-64 or (b) (WP-RP) mod-128 or (c) (WP-RP) mod-256 or (d) otherIf multiple choices are possible, state where you would use what ? ___________________________________________________________________________________________________

4.5 If you are using just 4-bit pointers for a 16-location FIFO, you need to set a lower threshold RAE and upper threshold RAF. Four of your junior engineers have set the thresholds as shown below. Comment/correct/prise them. ____________________________________________________________________________

4.6 Never ever synchronize by sampling and holding (circle all applicable):(a) a multi-bit data item where multiple bits could be changing simultaneously(b) a multi-bit data item where one bit at most changes at any time(c) none of the above

4pts

16pts

01

2

3

4

5

678

9

10

11

12

13

14

15

#3

RP WP

01

2

3

4

5

678

9

10

11

12

13

14

15

#4

01

2

3

4

5

678

9

10

11

12

13

14

15

#2WP

RPWP

01

2

3

4

5

678

9

10

11

12

13

14

15

#1WPRP

RP

Depth= _______ Depth= _______ Depth= _______ Depth= _______

8pts

8pts

8pts

4pts

EE354L_Final_Spring2016.fm

May 9, 2016 2:02 am EE354L Final - Spring 2016 5 / 6C Copyright 2016 Gandhi Puvvada

4 ( 4 + 16 + 8 + 8 + 8 + 4 = 48 points) 35 min. FIFOs

4.1 A change in width of the FIFO _______ (will / will not) cause a change in the pin-out of the FIFO.A change in depth of the FIFO _______ (will / will not) cause a change in the pin-out of the FIFO.

4.2 For an 8-location FIFO using 4-bit pointers for WP and RP some of the four situations (pairs of WP and RP) below namely ________ (#1, #2, #3, #4) is/are illegal. Among the remaining legal situations any one of them could be occurring before the other(s) as a FIFO is a circular buffer. T / F . Circle the populated locations for the legal situations and state the populated depth.

4.3 When we use (n+1)-bit pointers for WP[n:0] and RP[n:0] for a 2**n location FIFO, we use the ________ (lower/upper) n bits namely _____________ ([n-1:0]/[n:1]) to ________________________________ (index the array of locations/perform WP-RP to arrive at depth/both/neither).

4.4 For a 128-location deep FIFO, since populated depth can vary from completely empty to completely full, we have ________ (127/128/129) depth values and should be doing__ (a/b/c/d).(a) (WP-RP) mod-64 or (b) (WP-RP) mod-128 or (c) (WP-RP) mod-256 or (d) otherIf multiple choices are possible, state where you would use what ? ___________________________________________________________________________________________________

4.5 If you are using just 4-bit pointers for a 16-location FIFO, you need to set a lower threshold RAE and upper threshold RAF. Four of your junior engineers have set the thresholds as shown below. Comment/correct/prise them. ____________________________________________________________________________

4.6 Never ever synchronize by sampling and holding (circle all applicable):(a) a multi-bit data item where multiple bits could be changing simultaneously(b) a multi-bit data item where one bit at most changes at any time(c) none of the above

4pts

16pts

01

2

3

4

5

678

9

10

11

12

13

14

15

#3

RP WP

01

2

3

4

5

678

9

10

11

12

13

14

15

#4

01

2

3

4

5

678

9

10

11

12

13

14

15

#2WP

RPWP

01

2

3

4

5

678

9

10

11

12

13

14

15

#1WPRP

RP

Depth= _______ Depth= _______ Depth= _______ Depth= _______

8pts

8pts

8pts

4pts

5/4/18 EE354 Final - Spring 2018 9 / 12 C Copyright 2018 Gandhi Puvvada

4.4.3 Double-synchronization and clock domain crossing (CDC): Out of the four rows, cross off two and for the remaining two, complete the clock labels as appropriate using RCLK and WCLK. For our 32-location FIFO, we need to use ______ (4-bit/5-bit/6-bit) synchronization registers here.On the right, complete the labels and their sizes.

4.4.4 Producing depth in the two clock domains: You know that the depth is produced in a single-clock FIFO, depth is produced by doing WP-RP. Since subtraction in Gray is difficult, we do subtraction in binary. For our 32-location FIFO, complete the 4+4 = 8 items.

4.5 If you are conveying 8-bit binary counter changes from WP_bin[7:0] = 0111_ 1111 to WP_bin[7:0] = 1000_0000 (when the decimal value is changing from 127 to 128). The corresponding gray code values change from WP_gray[7:0] = 0100_ 0000 to WP_gray[7:0] = 1100_ 0000.If we try to convey these WP_bin[7:0] and WP_gray[7:0] to another clock domain through double synchronization, at worst case which all bits (Flip-Flops) go into metastable after the first synchronization and read wrong values after the second synchronization.

WP_bin[7:0]: ___________________________________________________

WP_gray[7:0]: __________________________________________________

14 pts

WP_Gray_S

__CLK

WP_Gray_SS

Gra

y to

Bin

ary

Con

verte

r WP_SS_BinWP_Gray

__CLK

WP_Bin_S

__CLK

WP_Bin_SS

Bin

ary

to G

ray

Con

verte

r WP_SS_GrayWP_Bin

__CLK

RP_Gray_S

__CLK

RP_Gray_SS

Gra

y to

Bin

ary

Con

verte

r RP_SS_BinRP_Gray

__CLK

RP_Bin_S

__CLK

RP_Bin_SSB

inar

yto

Gra

yC

onve

rter RP_SS_GrayRP_Bin

__CLK

D Q D Q

D Q D Q

D Q D Q

D Q D QRD

RP

WCLK

WD

WP

WENQ

REGARRY

WP______[ :0]

WD[3:0]

RD

[3:0

]

WCLKWENQ

32x4 Register Array for Storage

WP______[ :0]

12 pts

Bin SubtracterA B

AminusB

depth_wr

WP_ RP_

=________Label it asFULL or EMPTY

Bin SubtracterA B

AminusB

depth_rd

WP_ RP_

=________Label it asFULL or EMPTY

Depth in write clock domain

Depth in read clock domain

6 pts

5/4/18 EE354 Final - Spring 2018 9 / 12 C Copyright 2018 Gandhi Puvvada

4.4.3 Double-synchronization and clock domain crossing (CDC): Out of the four rows, cross off two and for the remaining two, complete the clock labels as appropriate using RCLK and WCLK. For our 32-location FIFO, we need to use ______ (4-bit/5-bit/6-bit) synchronization registers here.On the right, complete the labels and their sizes.

4.4.4 Producing depth in the two clock domains: You know that the depth is produced in a single-clock FIFO, depth is produced by doing WP-RP. Since subtraction in Gray is difficult, we do subtraction in binary. For our 32-location FIFO, complete the 4+4 = 8 items.

4.5 If you are conveying 8-bit binary counter changes from WP_bin[7:0] = 0111_ 1111 to WP_bin[7:0] = 1000_0000 (when the decimal value is changing from 127 to 128). The corresponding gray code values change from WP_gray[7:0] = 0100_ 0000 to WP_gray[7:0] = 1100_ 0000.If we try to convey these WP_bin[7:0] and WP_gray[7:0] to another clock domain through double synchronization, at worst case which all bits (Flip-Flops) go into metastable after the first synchronization and read wrong values after the second synchronization.

WP_bin[7:0]: ___________________________________________________

WP_gray[7:0]: __________________________________________________

14 pts

WP_Gray_S

__CLK

WP_Gray_SS

Gra

y to

Bin

ary

Con

verte

r WP_SS_BinWP_Gray

__CLK

WP_Bin_S

__CLK

WP_Bin_SS

Bin

ary

to G

ray

Con

verte

r WP_SS_GrayWP_Bin

__CLK

RP_Gray_S

__CLK

RP_Gray_SS

Gra

y to

Bin

ary

Con

verte

r RP_SS_BinRP_Gray

__CLK

RP_Bin_S

__CLK

RP_Bin_SSB

inar

yto

Gra

yC

onve

rter RP_SS_GrayRP_Bin

__CLK

D Q D Q

D Q D Q

D Q D Q

D Q D QRD

RP

WCLK

WD

WP

WENQ

REGARRY

WP______[ :0]

WD[3:0]

RD

[3:0

]

WCLKWENQ

32x4 Register Array for Storage

WP______[ :0]

12 pts

Bin SubtracterA B

AminusB

depth_wr

WP_ RP_

=________Label it asFULL or EMPTY

Bin SubtracterA B

AminusB

depth_rd

WP_ RP_

=________Label it asFULL or EMPTY

Depth in write clock domain

Depth in read clock domain

6 pts