simulink

848 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 2, FEBRUARY 2012

Analysis and Design of a Bidirectional IsolatedDC–DC Converter for Fuel Cells and

Supercapacitors Hybrid SystemZhe Zhang, Member, IEEE, Ziwei Ouyang, Student Member, IEEE, Ole C. Thomsen, Member, IEEE,

and Michael A. E. Andersen, Member, IEEE

Abstract—Electrical power systems in future uninterruptiblepower supplies or electrical vehicles may employ hybrid energysources, such as fuel cells and supercapacitors. It will be necessaryto efficiently draw the energy from these two sources as well asrecharge the energy storage elements by the dc bus. In this paper,a bidirectional isolated dc–dc converter controlled by phase-shiftangle and duty cycle for the fuel-cell hybrid energy system is ana-lyzed and designed. The proposed topology minimizes the numberof switches and their associated gate driver components by usingtwo high-frequency transformers that combine a half-bridge cir-cuit and a full-bridge circuit together on the primary side. Thevoltage doubler circuit is employed on the secondary side. Thecurrent-fed input can limit the input current ripple that is favor-able for fuel cells. The parasitic capacitance of the switches is usedfor zero voltage switching (ZVS). Moreover, a phase-shift and duty-cycle modulation method is utilized to control the bidirectionalpower flow flexibly and it also makes the converter operate undera quasi-optimal condition over a wide input voltage range. Thispaper describes the operation principle of the proposed converter,the ZVS conditions, and the quasi-optimal design in depth. The de-sign guidelines and considerations regarding the transformers andother key components are given. Finally, a 1-kW 30∼50-V-input400-V-output laboratory prototype operating at 100-kHz switch-ing frequency is built and tested to verify the effectiveness of thepresented converter.

Index Terms—Bidirectional dc–dc converter, current-fed, fuelcell (FC), phase shift, supercapacitor (SC).

I. INTRODUCTION

THE hybrid system based on fuel cells (FCs) and super-capacitors (SCs) as an environmentally renewable energy

system has been applied in many fields, such as hybrid electricvehicle, uninterruptible power supply (UPS), and so on [1]–[4].As an example, a block diagram of extended-run time battery-less double-conversion UPS system powered by FCs and SCs isillustrated in Fig. 1. Compared to diesel generators and batter-ies, FCs are electrochemical devices that convert the chemical

Manuscript received November 9, 2010; revised February 13, 2011 and April13, 2011; accepted May 29, 2011. Date of current version January 9, 2012.Recommended for publication by Associate Editor S. Choi.

The authors are with the Department of Electrical Engineering, TechnicalUniversity of Denmark, Kongens Lyngby DK-2800, Denmark (e-mail: [email protected]; [email protected]; [email protected]; [email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TPEL.2011.2159515

Fig. 1. Block diagram of a dual-conversion UPS system based on FC and SC.

potential of the hydrogen into electric power directly with con-sequent high conversion efficiency, so it has the possibility toobtain the extended runtime range with the combustible feedfrom the outside. But one of the main weak points of the FCis its slow dynamics because of the limited speed of hydrogendelivery system and the chemical reaction in the membraneswith a slow time constant [5]. Hence, during the warming-upstage or load transient, SCs [6], [7] are utilized as the auxiliarypower source for smoothing the output power. In addition, thefuel-cell output voltage is varied widely, almost 2:1, dependingon the load condition, and the terminal voltage of the SC bank isalso variable during charging and discharging periods. Thus, itis very important for the conversion system to be capable of har-vesting power from these two different power sources efficientlyin widely input voltage range and load conditions.

In recent years, many configurations of a hybrid dc powerconversion system relating to FCs and SCs have been proposed.Connecting FCs and SCs by two individual dc–dc convertersseparately to a mutual dc voltage bus is the most common config-uration [8], [9], which offers many advantages, especially, fasterand more stable system response. However, it increases the sys-tem cost and power losses. A multiple dc voltage bus, which con-nects FCs and SCs to different cascaded voltage buses throughconverters, is also a widely used configuration [10], [11], butthe disadvantages are high power losses and low reliability.

0885-8993/$26.00 © 2011 IEEE

ZHANG et al.: ANALYSIS AND DESIGN OF A BIDIRECTIONAL ISOLATED DC–DC CONVERTER 849

Fig. 2. Proposed hybrid bidirectional dc–dc converter topology.

Moreover, FCs and the SCs cannot keep the bus voltage con-stant except if they are oversized. The simplest configuration isto parallel FCs and SCs directly as one power source but theiroutput currents cannot be controlled independently. In addition,a multiport configuration was introduced [12], [13]. For the ap-plications where the galvanic isolation is required, an isolatedmultiport converter family was investigated in [14]. Based onthe traditional half-bridge topology, a novel four-port converterwith bidirectional ability was presented in [15] and [16]. A mul-tiport current-fed dc–dc converter based on the flux additivitywas proposed in [17]. The boost-type input port can limit thecurrent ripple and this characteristic is helpful to increase thelifetime of FCs, but the diode connected in series with eachMOSFETs makes reversible power flow impossible. To over-come this drawback, two current-fed dual-input bidirectionalconverters were proposed and investigated in [18] and [19]. Thesolutions based on the dual-active-bridge converter using mag-netic coupling transformer were presented in [20]–[23], wherethe bidirectional power can be regulated by phase-shift controlscheme. Converters using resonant tank or interleaved trans-former windings were reported in [24] and [25], respectively.However, the control strategy for the multiport type is not easyto implement [25].

Based on the boost-half-bridge (BHB) circuit [26], [27] andthe hybrid full-bridge structure [28], a novel hybrid bidirectionaldc–dc converter was derived and presented in [29]. In this paper,characteristics of the proposed converter in [29] will be analyzedin depth. As shown in Fig. 2, a fuel-cell bank as the main inputpower source is connected to the BHB circuit which can limitthe input current ripple; an SC bank as the auxiliary powersource can deliver power to the load through the full-bridgecircuit. The proposed converter can draw power from these twodifferent dc sources individually and simultaneously. Moreover,using the phase-shift plus duty-cycle control scheme [30], thebidirectional power flow can be regulated flexibly and the accurrent root-mean-square (RMS) value can be reduced over awide input voltage range.

This paper is organized as follows. Section I introduces theresearch background and the contribution of this study. SectionII gives the operation principles and the theoretical calculations.Section III presents the quasi-optimal design method. To verify

the validity of the theoretical analysis and the design approach,experimental results from the laboratory prototype are presentedin Section V. Finally, the conclusion is given in Section VI.

II. OPERATION PRINCIPLES OF THE HYBRID

BIDIRECTIONAL DC–DC CONVERTER

As shown in Fig. 2, a BHB structure locates on the primaryside of the transformer T1 and it associates with the switchesS1 and S2 that are operated at 50% duty cycle. The SC bankas an auxiliary energy source is connected to the variable low-voltage (LV) dc bus across the dividing capacitors, C1 and C2 .Bidirectional operation can be realized between the SC bankand the high-voltage (HV) dc bus. Switches S3 and S4 are con-trolled by the duty cycle to reduce the current stress and ac RMSvalue when input voltage VFC or VSC are variable over a widerange. The transformers T1 and T2 with independent primarywindings as well as series-connected secondary windings areemployed to realize galvanic isolation and boost a low inputvoltage to the HV dc bus. A dc blocking capacitor Cb is addedin series with the primary winding of T2 to avoid transformersaturation caused by asymmetrical operation in full-bridge cir-cuit. The voltage doubler circuit utilized on the secondary sideis to increase voltage conversion ratio further. The inductor L2on the secondary side is utilized as a power delivering interfaceelement between the LV side and the HV side. According tothe direction of power flow, the proposed converter has threeoperation modes that can be defined as boost mode, SC powermode, and SC recharge mode. In the boost mode, the power isdelivered from the FCs and SCs to the dc voltage bus. In the SCpower mode, only the SCs are connected to provide the requiredload power. When the dc bus charges the SCs, the power flowdirection is reversed which means the energy is transferred fromthe HV side to the LV side, and thereby the converter is operatedunder the SC recharge mode.

A. Boost Mode

In the boost mode, the timing diagram and typical waveformsare shown in Fig. 3, where n1 and n2 are the turn ratios of thetransformers. The current flowing in each power switch on theprimary side is presented, but the voltage and current resonantslopes during the switching transitions are not shown here forsimplicity. To analyze the operation principles clearly, the fol-lowing assumptions are given: 1) all the switches are ideal withantiparallel body diodes and parasitic capacitors; 2) the induc-tance L1 is large enough to be treated as a current source; 3) theoutput voltage is controlled well as a constant; 4) the leakageinductance of the transformers, parasitic inductance, and extrainductance can be lumped together as L2 on the secondary side.

The half switching cycle can be divided into eight intervalsand the corresponding equivalent circuits are shown in Fig. 4.

1) Stage 1 (t0–t1): It can be seen that at any time, the volt-age across L2 is always VT 1b + VT 2b − VCO , but VT 1b ,VT 2b , and VCO have different values in different oper-ating intervals. In (t0–t1), S1 , S4 , and S6 are gated, soVT 1b = n1VFC , VT 2b = 2n2VFC , and VCO = − Vo /2, andthereby iL 2 will increase linearly. Because iT 1a + iT 2a are


Fig. 3. Timing diagram and typical waveforms in the boost mode.

negative and IL 1 is positive, the current flows throughDS 1 , the body diode of switch S1 . The current paths dur-ing this interval are shown in Fig. 4(a).

2) Stage 2 (t1–t2): From t1 , the value of iT 1a + iT 2a startsto be positive, and thus S4 conducts to carry the current,but S1 may conduct until the value of IL 1 is smaller thanthat of iT 1a + iT 2a . The equivalent circuit is shown inFig. 4(b).

3) Stage 3 (t2–t3): At t2 , S6 is turned OFF. The inductor L2begins to resonate with the stray capacitors CS 5 and CS 6 .When the voltage across CS 5 reduces to zero, the bodydiode of S5 starts to conduct, so the voltage VCO equalsVo /2.

4) Stage 4 (t3–t4): At t3 , S5 is turned ON under zero-voltage switching (ZVS). The current paths are illustratedin Fig. 4(c).

5) Stage 5 (t4–t5): At t4 , S4 is turned OFF. The inductorL2 begins to resonate with the stray capacitors CS 3 andCS 4 . When the voltage across S3 reduces to zero, DS 3 is,therefore, forward biased. The voltage across the primarywinding of T2 is clamped to zero, i.e., VT 2b = 0. Hence,VL 2 equals VT 1b − VCO and the current paths are shownin Fig. 4(d).

6) Stage 6 (t5–t6): At t5 , S1 is turned OFF. The inductor L2begins to resonate with the stray capacitors of the switches,

CS 1 and CS 2 . CS 1 is charged from approximately 0 V,while CS 2 is discharged from 2VFC . The rate of changeon voltage depends on the magnitude iT 1a + iT 2a − IL 1 .At t5 , VCS2 attempts to overshoot the negative rail andthen DS 2 is forward biased. After that, S2 can be turnedON under ZVS.

7) Stage 7 (t6–t7): During this interval, VT 1b = − n1VFC ,VT 2b = − 2n2VFC , and VCO = Vo /2, so the primarycurrent decays. Until IL 1 is bigger than iT 1a + iT 2a , thecurrent starts to flow through the switch S2 , and thus theequivalent circuit is shown in Fig. 4(e).

8) Stage 8 (t7–t8): From t7 , both iT 1a and iT 2a are to benegative, which makes S3 and S5 conduct. The equivalentcircuit is shown in Fig. 4(f). After t8 , the second half cyclestarts.

The power delivered by this converter can be calculated, re-ferring to the typical waveforms shown in the Appendix, asfollows:

Po =⎧⎪⎪⎪⎨

⎪⎪⎪⎩

VLVH

(2πδ − 4δ2 + 2δd + πd − d2

)

2πωL2(0 ≤ |δ| ≤ d)

VLVH

(2πδ − 2δ2 − 2 |δ| d + πd + d2

)

2πωL2(d ≤ |δ| ≤ 0.5π)

(1)

where δ is the phase-shift angle; ω is the switching angularfrequency; VL = n1VFC and VH = Vo /2, respectively; the dutycycle d is defined as

d = 2π · TonS3

Ts= 2π · TonS4

Ts. (2)

When d = π, vT 1b + vT 2b will be the waveform with only twovoltage levels, and then (1) will be

Po =2 · VLVH

πωL2· δ (π − δ) . (3)

When δ = 0, the output power is calculated by

Po =VLVH

2πωL2· d (π − d) . (4)

In order to limit the reactive power in the converter, the phase-shift angle normally is smaller than π/4 and thereby the firstsubequation in (1) is more practical to analyze the averagepower. Based on that, the output power, which is with respectto the base VL VH /2πωL2 , is plotted in Fig. 5. It can be seenthat when the duty-cycle control is utilized together with thephase-shift control, at the same input and output voltages, theaverage power delivered is increased, because the duty-cyclecontrol can limit the required reactive power. But with the dutycycle reducing, the output power increasing is not significant.When the phase-shift angle is larger than 0.6, the delivered av-erage power is decreased, because in fact the duty-cycle controlreduces the average voltage across the secondary windings.

A close study reveals that because of the BHB configurationthe average current stress of S2 is much higher than that of S1 ,whereas the current stresses of S3 and S4 are kept the same.


Fig. 4. Equivalent circuits in each operating stage: (a) Stage 1, (b) Stage 2, (c) Stage 4, (d) Stage 5, (e) Stage 7, and (f) Stage 8.

Fig. 5. Relationship between the output power (p.u.) and phase-shift angle/duty cycle.

Referring to the definition in Fig. 3, the ON-time conductingcurrent of each main device is given by

iS1 ON(t) = iT 1a(t) + iT 2a(t) − iL1(t)

iS2 ON(t) = iL1(t) − iT 1a(t) − iT 2a(t)

iS3 ON(t) = iT 2a(t)

iS4 ON(t) = −iT 2a(t). (5)

From (5), obviously, S2 carries more current than S1 , so thatdevices with different current ratings can be chosen for S1 andS2 . Thus, the peak current values of the primary side switchesare

⎧⎪⎪⎪⎪⎪⎨

⎪⎪⎪⎪⎪⎩

IS1,peak =Po

ηVFC+ (n1 + n2) · Ipeak

IS2,peak =Po

ηVFC+ (n1 + n2) · Ipeak

IS3,peak = IS4,peak = n2 · Ipeak

(6)

where η is the efficiency of the converter and Ipeak = max(I1 ,I2 , I3), and I1 , I2 , and I3 are calculated as follows:

⎧⎪⎪⎪⎪⎪⎪⎪⎨

⎪⎪⎪⎪⎪⎪⎪⎩

I1 = iL2(t2) =πVH + (4δ − d − π) VL

2ωL2

I2 = iL2(t4) =(π + 2δ − 2d) VH + (3d − π)VL

2ωL2

I3 = iL2(t5) =(2δ − π)VH + (π + d) VL

2ωL2.

(7)


Fig. 6. Proposed converter in the SC power mode and the SC recharge mode.

The ZVS condition can be deduced on the precondition thatthe antiparallel diode of switch must conduct before the switchis triggered. Then, the soft-switching conditions for switchesS1 and S2 , switches S3 and S4 , and switches S5 and S6 arerelated to the magnitude of iT 1a + iT 2a − iL 1 , iT 2a , and iL 2 ,respectively, i.e., the main devices are turned OFF with a positivecurrent flowing and then the current diverts to the opposite diodewhich allows the incoming MOSFET to be switched on underzero voltage. Thus, in order to achieve ZVS turn ON, the currentsmust obey

⎧⎪⎪⎪⎪⎪⎪⎪⎪⎪⎨

⎪⎪⎪⎪⎪⎪⎪⎪⎪⎩

iT 1a(t0) + iT 2a(t0) − IL1 < 0; (for S1)

iT 2a(t0) < 0; (for S4)

iL2(t2) > 0; (for S5)

iT 1a(t5) + iT 2a(t5) − IL1 > 0; (for S2)

iT 2a(t5) > 0; (for S3)

iL2(t8) < 0; (for S6).

(8)

Hence, substituting (7) into (8), ZVS constraints with respectto circuit parameters and control variables are deduced as⎧⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎨

⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎩

Vo >2n1(n1 + n2)(π + d)VFC + 4IL1L2ω

(π − 2δ) (n1 + n2)(for S1)

Vo <2n1(n1 + n2)(π + d)VFC − 4IL1L2ω

(π − 2δ) (n1 + n2)(for S2)

Vo

VFC< 2n1

(π + d

π − 2δ

)

(for S3 , S4)

Vo

VFC> 2n1

(π + d − 4δ

π

)

(for S5 , S6).

(9)

B. SC Power Mode

For a short period of utility power failure in UPS system thatcan be handled by SCs or during the fuel-cell warming-up stage,the converter will be operated under the SC power mode andthe power flows from SC bank to the dc voltage bus as shown inFig. 6. The timing diagram and typical waveforms in this modeare illustrated in Fig. 7. It can be seen that the typical waveformsare similar with those in the boost mode, but because there is noiL 1 , the current stresses of S1 and S2 are completely the same.

Fig. 7. Timing diagram and typical waveforms under the SC power mode.

The peak current can be expressed by

IS1,peak = IS2,peak = (n1 + n2) · I2 . (10)

With the same method used in the boost mode, to achieveZVS turn-ON, the currents must obey

⎧⎪⎪⎪⎪⎪⎪⎪⎪⎪⎨

⎪⎪⎪⎪⎪⎪⎪⎪⎪⎩

iT 1a(t0) + iT 2a(t0) < 0; (for S1)

iT 2a(t0) < 0; (for S4)

iL2(t2) > 0; (for S5)

iT 1a(t5) + iT 2a(t5) > 0; (for S2)

iT 2a(t5) > 0; (for S3)

iL2(t8) < 0; (for S6).

(11)

Comparing to (8), the ZVS constraints for S1 and S2 aredifferent in this mode and thereby the ZVS condition can beexpressed as

⎧⎪⎪⎪⎨

⎪⎪⎪⎩

Vo

VFC< 2n1

(π + d

π − 2δ

)

(for S1–S4)

Vo

VFC> 2n1

(π + d − 4δ

π

)

(for S5 , S6).

(12)

C. SC Recharge Mode

As shown in Fig. 6, in the SC recharge mode, the SC will becharged by the HV dc bus which means that the power flowsfrom the HV side to the LV side. The timing diagram and typicalwaveforms are illustrated in Fig. 8, where the gate drive signalof S5 is leading to that of S1 due to the reversed power-flowdirection.

III. QUASI-OPTIMAL DESIGN METHOD

To increase the conversion efficiency, generally based on theprecise mathematic model of the power loss of each componentand the converter switching times, the phase-shift angle, andthe duty cycle can be calculated to control the converter andmake the total power losses minimal [31]. But this method hastwo critical limitations in practice: 1) performance will suffer


Fig. 8. Timing diagram and typical waveforms under the SC recharge mode.

when the loss models employed in the circuit and the switchingtimes are not available or not precise; and 2) the controller withthe needed phase-shift angle and duty cycle depending on thevariable input voltage and output power is complex to design.Hence, a quasi-optimal design is proposed here which includestwo design criteria.

1) Minimize the RMS value of iL 2 by the phase-shift andduty-cycle control to reduce the conduction losses.

2) Keep the ZVS operation for HV-side switches to reducethe switching losses.

The RMS current flowing through the secondary inductor iscalculated, as shown in (13), at the bottom of this page.

From (13), the secondary-side RMS current is plotted inFig. 9(a) according to phase-shift angles and duty cycles un-der the condition where the output power is 1 kW; the outputvoltage is 400 V; the interface inductance is 40 μH, and theswitching frequency is 100 kHz. When the input voltage or theduty cycle varies, the phase-shift angle may be recalculated by(1) to get the required output power or dc-bus voltage. It can beseen that based on the input voltage and the phase-shift anglefrom (1), adjusting the duty cycle value can reduce the currentRMS value effectively. Furthermore, using duty-cycle controlcan extend the soft-switching range for the HV-side switches,S5 and S6 , as shown in Fig. 9(b). The I1 curve (dashed line)is the approximate track which is followed by current I1 andthere is a margin between the I1 curve and boundary curve,which is related to the energy stored in the L2 for achievingcompletely resonance during the dead time of switch commuta-tion. From Fig. 9(a), an approximate relationship between inputvoltage and duty cycle can be derived as illustrated in Fig. 10,where the piecewise curve consisting of f1(vin ) and f2 (vin ) isplotted. Based on the values indicated, d1 = f1(vin ) = 10.676–0.251vin (30 ≤ vin < 35.8) and d2 = f2 (vin ) = 3.925–0.063vin(35.8 ≤ vin ≤ 50) are obtained. In practice, in order to monitorthe output state of FC for the overvoltage protection purpose,normally, the input voltage sensing is necessary, so that the dutycycle can be decided by f1(vin ) or f2 (vin ) without adding sys-

Fig. 9. Typical current values with phase shift plus duty-cycle control underthe boost mode: (a) secondary current RMS values, and (b) peak current valuesof iL 2 at time t2 .

Fig. 10. Relationship between the duty cycle and variable input voltage.

tem complexity, and it is easy to be completed by both analogand digital circuits. As stated in Section II, the average outputpower can be controlled by two independent control variables: δand d. The analysis conducted here revealed that there is a valuedoptimal that can minimize the ac RMS current and extend theZVS range to achieve quasi-optimal operation. Hence, variable δ

IL2,RMS =√

33

·√

(π − δ)I22 + [(π − d)I3 + (d − δ)I1 ]I2 + (π + δ − d)I2

3 − I1I3δ + I21 d

π. (13)


is used to control the required power transferred by the converterand variable d is chosen to increase the efficiency. The algorithmto decide δ and d is implemented by the following steps.

1) Find the value doptimal that minimizes RMS current byequating the first derivative of (13) to zero with respect tod for the input voltage VFC or VSC , the output voltage Vo

and the required output power Po .2) Determine δ, using (1). If δ < 0 or cannot find real root,

set δ = 0, and recalculate d by (4).3) Test the value of I1 . If I1 < 0, reduce d and then go back

to step 2 to recalculate δ.4) Using calculated δ and d, generate the driving signals for

the power switches.5) If one of the values of VFC , VSC , Vo , or Po changes, then

go back to step 1.In this paper, according to the variable input voltage and

the required output power, the quasi-optimal designed δ and dcan be calculated offline. During the hardware test, the onlinelook-up table is used in the digital signal processor to controlthe converter effectively.

IV. HARDWARE DESIGN AND TEST

The converter works with a variable input voltage 30–50 Vand a constant output voltage 400 V. The duty cycles of S1 andS2 are kept at 50%, so the voltage across C1 and C2 is doubleof the input voltage VFC . The bidirectional power flow can becontrolled by the phase-shift angle δ which is between S1 andS5 , and the duty cycle of S3 and S4 . It is worth noting thatalthough the amplitude of the voltage on T1 is half of that on T2due to T1 associates with half-bridge structure, the same powercan be delivered by each transformer since the turns ratios ofT1 and T2 have been chosen with the relationship: n1 = 2n2 , inthis paper.

A. Transformer Design

For the low-input-voltage converter, the conduction lossesare dominating in the total power losses. Hence, it is impor-tant to reduce the transformer winding losses. Winding lossesin transformers increase dramatically with the high switchingfrequency due to eddy and proximity current effects [32].

Based on Dowell’s assumptions and the general field solutionsfor the distribution of current density in a single layer of aninfinitely foil conductor, the expression for ac resistance of themth layer was derived in [32] and [33] as

Rac,m

Rdc,m=

ξ

2

[sinh ξ + sin ξ

cosh ξ − cos ξ+ (2m − 1)2 · sinh ξ − sin ξ

cosh ξ + cos ξ

]

(14)where m is defined as a ratio

m =F (h)

F (h) − F (0)(15)

where F (0) and F (h) are magnetomotive forces (MMF) at thelimits of a layer, shown in Fig. 11 where Pm (m = 1–4) andSn (n = 1–8) indicate the primary and secondary windings,respectively.

Fig. 11. Winding arrangements: (a) winding arrangement and MMF distribu-tion for half T1 in one of the outer legs, and (b) winding arrangement and MMFdistribution for half T2 in one of the outer legs.

The first term in (14) is to describe the skin effect, and thesecond term represents the proximity effect factor. The proxim-ity effect loss in a multilayer winding may strongly dominateover the skin effect loss depending on the value of m that isrelated to the winding arrangement. Interleaving transformerwindings can reduce the proximity loss significantly when theprimary and secondary currents are in phase. When the numberof primary turns for T1 and T2 are 4 and 8, respectively, Fig. 11shows the winding arrangements and MMF distributions alongthe vertical direction for both half of T1 and T2 . The value ofm in each layer equals 1 according to (15) which contributesto lower ac resistances. Not only ac resistances can be reduced,but also leakage inductances can be significantly decreased byinterleaving windings [33]. It is noted that because of fewer in-tersections between the primary and the secondary, interwind-ing capacitance in this interleaving structure is smaller than thefully interleaving without sacrificing any other behaviors, nei-ther leakage inductance nor ac resistance, thereby contributingto relative lower electromagnetic interference noises.

B. Input Inductor

The BHB structure with the storage inductor L1 in series withFCs, inherently, can reduce the input current ripple. Comparedto buck-derived topologies having large discontinuous input cur-rents, the proposed converter with boost-type input port requiresonly very small additional input capacitance Cin as input filter.According to the required ripple current ΔIL 1 of input currentIL 1 , the input inductance can be calculated by

L1 =VFC · Δt

ΔIL1=

πVFC

ω · ΔIL1(16)

where Δt is the ON-time of switch S2 during each switchingcycle.

Moreover, all the individual magnetic components, two trans-formers and one inductor, can be integrated into one planar E-I-Ecore to increases the power density further [34].


Fig. 12. Peak current of the secondary side under different input voltages.

TABLE IPARAMETERS AND COMPONENTS

C. Power Switches

Based on the analyzed results in Section II, it can be concludedthat at the full load, the peak current is I2 on the secondaryside. The different values of I2 under the phase-shift and duty-cycle control can be plotted in Fig. 12 and thus using duty-cyclecontrol oversized power devices can be avoided. On the LV side,the peak current flowing through the switches can be calculatedby (6) and the peak voltage across the switches on the primaryside is

Vpeak = 2VFC . (17)

On the HV side, the peak voltage for all the switches equals theoutput voltage, and the peak current of the voltage doubler isfour times smaller than that of S3 or S4 on the LV side.

The key parameters and components of the designed proto-type are listed in Table I and a photograph of the laboratoryprototype is shown in Fig. 13.

In the test, an LV- and high-current dc power supply (EA-PS 9060-48: 0∼60 V/0∼48 A) as the primary input powersource is used to simulate the FC. Twenty-four SCs (BCAP0350,2.5 V/350 F) connected in series are taken as the power storageunit connected on the LV dc bus.

Figs. 14–16 show the measured waveforms from the proto-type working under the phase-shift plus duty-cycle modulationin the condition where VFC = 30 V and input power is 750 W.It can be seen that the measured results match well with the

Fig. 13. Prototype of the proposed converter.

Fig. 14. Experimental waveforms in VFC = 30 VDC (input power 750 W)and d = π . vT 1b + vT 2b [Ch1: 250 V/div], vCO [Ch2: 350 V/div], iL 2 [Ch3:10 A/div], and iL 1 [Ch4: 20 A/div]. Time base: 5 μs/div.

Fig. 15. Experimental waveforms in VFC = 30 VDC (input power 750 W)and d = 0.65 π . vT 1b + vT 2b [Ch1: 250 V/div], vCO [Ch2: 350 V/div], iL 2[Ch3: 10 A/div], and iL 1 [Ch4: 20 A/div]. Time base: 5 μs/div.

theoretical analysis shown in Fig. 3. When d = π, Fig. 14 rep-resents the waveforms of the voltages on the secondary side(Ch1: vT 1b + vT 2b and Ch2: vCO ) and the currents flowing inL2 and L1 (Ch3: iL 2 and Ch2: iL 1), respectively. Since vT 1b

+ vT 2b ≈ vCO , the waveform of iL 2 is flat, which agrees withthe calculated results in (7). Fig. 15 shows the measured wave-forms when d = 0.65π. Compared to Fig. 14, vT 1b + vT 2b hasmultiple voltage levels because of the duty-cycle control, whilethe waveform of iL 1 is the same. Fig. 16 shows the plots of theprimary voltages (Ch1: vAN and Ch2: vAB ) and currents (Ch3:iT 1a and Ch4: iT 2a ) of T1 and T2 , when d = 0.65π. It is clearthat the vAB has a three-level voltage waveform.


Fig. 16. Experimental waveforms in VFC = 30 VDC (input power 750 W)and d = 0.65 π condition. vAN [Ch1: 100 V/div], vAB [Ch2: 100 V/div], iT 1a

[Ch3: 20 A/div], and iT 2a [Ch4: 20 A/div]. Time base: 5 μs/div.

Fig. 17. Drain–source voltage vds and gate drive signal vgs of the switchesin VFC = 30 VDC and input power 750 W. (a) S2 : vgs2 [Ch1: 10 V/div], andvds2 [Ch2: 50 V/div]. (b) S4 : vgs4 [Ch1: 10 V/div] and vds4 [Ch2: 50 V/div].(c) S6 : vgs6 [Ch1: 10 V/div] and vds6 [Ch2: 200 V/div]. Time base: 1 μs/div.

In Fig. 17, the gate drive signals and the drain–source voltagesof switches S2 , S4 , and S6 are presented, respectively. Thesewaveforms demonstrate that the voltage across switches hasdecreased to zero before the gate drive signal is given, whichverifies the turn-ON ZVS operation.

In Fig. 18, the experimental results under the SC power modeare given. Compared to the waveforms shown in Fig. 15, the onlydifference is that input current iL 1 is replaced by iSC , which is

Fig. 18. Experimental waveforms in the SC power mode with the conditionVSC = 60 V, input power 750 W. vT 1b + vT 2b [Ch1: 250 V/div], vCO [Ch2:350 V/div], iL 2 [Ch3: 10 A/div], and iSC [Ch4: 20 A/div]. Time base: 5 μs/div.

Fig. 19. Experimental waveforms when d = π in the SC recharge mode withthe condition Vo = 200 V, output power 100 W. vT 1b + vT 2b [Ch1: 250 V/div],vCO [Ch2: 200 V/div], iL 2 [Ch3: 2 A/div], and iSC [Ch4: 5 A/div]. Time base:5 μs/div.

Fig. 20. Experimental waveforms when d �= π in the SC recharge mode withthe condition Vo = 200 V, output power 100 W. vT 1b + vT 2b [Ch1: 100V/div],vCO [Ch2: 200 V/div], iL 2 [Ch3: 2 A/div], and iSC [Ch4: 5A/div]. Time base:5 μs/div.

the output current of SC bank, because load is powered by theSCs in this mode.

In the SC recharge mode with 200-V output voltage, Figs. 19and 20 show the experimental waveforms under the cases d =π and d �= π, respectively. The waveform of vCO is leading tothat of vT 1b + vT 2b , which means that the phase-shift angle isnegative in this case and iSC reverses to charge the SCs. Thesimilar quasi-optimal design method based on the phase-shiftcontrol and the duty-cycle control can also be derived in thismode.

Fig. 21 shows the efficiency curves of the converter oper-ating under the boost mode with the designed quasi-optimalphase-shift plus duty-cycle control when output power is900 W. By the quasi-optimal design method, the converter ef-ficiency is increased in the entire input voltage range as the


Fig. 21. Efficiency curves.

enveloping line of the efficiency curves shown in Fig. 21 be-cause using the duty-cycle control, one can find the maximalefficiency point with respect to the variable input voltage.

V. CONCLUSION

A novel hybrid bidirectional dc–dc converter consisting of acurrent-fed input port and a voltage-fed input port was proposedand studied. Using the steady-state analysis, the relationship be-tween the voltage gains of the proposed converter was presentedto analyze the power flows. The simple quasi-optimal designmethod was investigated to reduce the current ac RMS currentand extend the ZVS range. Experiments showed good agree-ment with the theoretical analysis and calculation. Additionally,the experimental results reveal that the duty-cycle control caneffectively eliminate the reactive power and increase the effi-ciency when input voltage is varied over a wide range. So, wecan conclude that the proposed converter is a promising candi-date circuit for the FC and SC applications. Due to the limitationof present experiments, energy management strategies to con-trol system power and achieve high overall efficiency of theproposed hybrid system will be studied in the future.

APPENDIX

In the boost mode, in order to calculate the key values andparameters of the proposed converter, the simplified typical op-erating waveforms are plotted in Fig. 22.

When 0 ≤ δ ≤ d, referring to the waveforms shown inFig. 22(a), the piecewise curve of transient current iL 2 can be

Fig. 22. Typical simplified operating waveforms in boost mode: (a) when 0 ≤δ ≤ d; (b) when 0 ≤ d ≤ δ.

expressed by the formula in each interval as

iL2(ωt) =

⎧⎪⎪⎪⎪⎪⎪⎨

⎪⎪⎪⎪⎪⎪⎩

−I3 · δ + (I1 + I3) · ωt

δ(0 ≤ ωt < δ)

I1 · d − I2 · δ + (I2 − I1) · ωt

d − δ(δ ≤ ωt < d)

−I2 · π + I3 · d + (I2 − I3) · ωt

−π + d(d ≤ ωt ≤ π)

(18)where I1 = iL 2(δ), I2 = iL 2(d), and I3 = iL 2(π).

Using Faraday’s law and voltage-second balance on the in-terface inductor L2 , we can obtain the relationships between thecurrent values and circuit parameters as

I1 + I3 =(2VL + VH )

ωL2· δ

I2 − I1 =(2VL − VH )

ωL2· (d − δ)

I2 − I3 =(VH − VL )

ωL2· (π − d) . (19)

Hence I1 , I2 , and I3 can be calculated by (19), respectively, andthe results are shown in (7).

If we ignore any loss of the circuit, the output average powercan be obtained as

PO =

∫ π

0 (vT 1b+T 2b(ωt) · iL2(ωt)) · dωt

π

=12π

· ((I1 − I3) · (δ − 0) · 2VL + (I1 + I2) · (d − δ)

· 2VL + (I2 + I3) · (π − d) · VL )

=VLVH (2πδ − 4δ2 + 2δd + πd − d2)

2πωL2. (20)

According to (18), the current RMS value of iL 2 is calculatedas shown in (21), at the bottom of this page.

IL2RMS =

√√√√ 1

π·[∫ δ

0

((I1 + I3) · ωt − I3δ

δ

)2

· d (ωt) +∫ d

δ

((I2 − I1) · ωt − I2δ + I1d

d − δ

)2

· d (ωt)

+∫ π

d

((I2 − I3) · ωt − I2π + I3d

d − π

)2

· d (ωt)

]

=√

33

·√

(π − δ) I22 + [(π − d) I3 + (d − δ) I1 ] I2 + (π + δ − d) I2

3 − I1I3δ + I21 d

π. (21)


When 0 ≤ d ≤ δ, as shown in Fig. 22(b), transient currentiL 2 can be expressed as

iL2 (ωt) =

⎧⎪⎪⎪⎪⎪⎪⎪⎨

⎪⎪⎪⎪⎪⎪⎪⎩

−I3 · d + (I1 + I3) · ωt

d(0 ≤ ωt < d)

I1 · δ − I2 · d + (I2 − I1) · ωt

δ − d(d ≤ ωt < δ)

I2 · π − I3 · δ + (I3 − I2) · ωt

π − δ(d ≤ ωt ≤ π)

(22)where I1 = iL 2(d), I2 = iL 2(δ), and I3 = iL 2(π).

Similar to (19), using Faraday’s law and voltage–second bal-ance on the interface inductor L2 , I1 , I2 , and I3 can be calculatedby

I1 =(π + 2d − 2δ) VH + (3d − π) VL

2ωL2

I2 =πVH + (2δ + d − π) VL

2ωL2

I3 =(2δ − π) VH + (d + π) VL

2ωL2. (23)

Hence, the output average power, in this case, can be obtainedas

PO =

∫ π

0 (vT 1b+T 2b(ωt) · iL2(ωt)) · dωt

π

=12π

· ((I1 − I3) · (d − 0) · 2VL + (I1 + I2) · (δ − d)

· VL + (I2 + I3) · (π − δ) · VL )

=VLVH (2πδ − 2δ2 − 2δd + πd + d2)

2πωL2. (24)

With the similar waveform analysis method and calculation pro-cedure, all the values in the SC power mode and the rechargemode, such as output power, current peak value, RMS value,etc., can be obtained as well.

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Zhe Zhang (S’07–M’11) received the B.S. and M.S.degrees in electrical engineering from Yanshan Uni-versity, Qinhuangdao, China, in 2002 and 2005, re-spectively, and the Ph.D. degree from the TechnicalUniversity of Denmark, Kongens Lyngby, Denmark,in 2010.

From 2005 to 2007, he was an Assistant Professorand Lecturer at Yanshan University. From June 2010to August 2010, he was with University of California,Irvine, CA, as a visiting scholar. After he finished hisPh.D., he was a Postdoctoral Researcher at Technical

University of Denmark from January 2011 to September 2011. He is currentlyan Assistant Professor of power electronics at Technical University of Denmark.His current research interests include dc/dc converters, multilevel inverters forfuel cell powered uninterruptible power supplies and hybrid electric vehicles.

Ziwei Ouyang (S’07) received the B.S. degree inelectrical engineering from the Naval University ofEngineering, Wuhan, China, in 2004, the M.S de-gree from Tianjin University of Technology, Tianjin,China, in 2007, and the Ph.D. degree from the Tech-nical University of Denmark, Kongens Lyngby, Den-mark, in 2011.

From May 2011 to August 2011, he was with Tech-nical University of Delft, Netherlands, as a VisitingScholar. He is currently in the Department of Electri-cal Engineering, Technical University of Denmark,

as a Postdoctoral Researcher. His current research interests include magneticsdesign, modeling and integration in power supplies, dc/dc converters, and digitalcontrol in high-power reversible converters.

Dr. Ouyang is a recipient of the Chinese Government Award for OutstandingStudents Abroad in 2010 and received the best paper award in 2010 from IPEC(ECCE-Asia).

Ole C. Thomsen (M’06) received the B.S.E.E. de-gree in electronics from the Engineering Academy ofDenmark, Kongens Lyngby, Denmark, in 1970.

He was as an RF R&D Engineer at SkandinaviskTeleindustri A/S from 1970 to 1976. From 1976 to1980, he was the Power Electronic Project Managerin the Space Department at Christian Rovsing A/S.In 1980, he founded Powerlab A/S, operating withinR&D and manufacturing of professional power elec-tronic, and served as General Manager until 2004.Since 2005, he has been with the Technical Univer-

sity of Denmark, Kongens Lyngby, where he is currently an Associate Professor.His main research interests include switch-mode power supplies, power factorcorrection, and electromagnetic compatibility.

Michael A. E. Andersen (M’88) received theM.Sc.E.E. and Ph.D. degrees in power electronicsfrom the Technical University of Denmark, KongensLyngby, Denmark, in 1987 and 1990, respectively.

He is currently a Professor of power electron-ics at the Technical University of Denmark. Since2009, he has been Deputy Director in the Depart-ment of Electrical Engineering. He is the author orcoauthor of more than 100 papers. His research in-terests include switch-mode power supplies, piezo-electric transformers, power factor correction, and

switch-mode audio power amplifiers.

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