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SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin
FRONT END PROCESSES - CLEANING, LITHOGRAPHY, OXIDATIONION IMPLANTATION, DIFFUSION, DEPOSITION AND ETCHING
• Cleaning belongs to front end processes and is an important part of fabrication.• Reference - ITRS Roadmap for Front End Processes (class website).
Chapter 4
Semiconductor ManufacturingClean Rooms, Wafer Cleaning and Gettering
Importance of Importance of unwanted unwanted impurities impurities increases with increases with shrinking shrinking geometries of geometries of devices. devices.
75% of the yield 75% of the yield loss is due to loss is due to defects caused defects caused by particles by particles (1/2 of the min (1/2 of the min feature size)feature size)
Crystal Crystal originated (45-originated (45-150nm) particles 150nm) particles (COP) (COP) ~1,000Å=void ~1,000Å=void with SiOwith SiOx x -> -> affect GOIaffect GOI
-> anneal in H-> anneal in H22 -> oxide -> oxide decomposes and decomposes and surface surface reconstructs! & reconstructs! & oxide oxide precipitates precipitates from deep depth from deep depth in Si.in Si.
Yield -> 90% at the end -> 99% @ each step
Historical Development and Basic Concepts
Contaminants and their role in devices (various elements, various films)
Na+, Ka+
XOX ~10nm QM≈ 6.5x1011cm-2, VTN=0.1V (equivalent to 6.7*1017 cm-3 or 10 ppm contaminations)
! !
!!Life time killers
Poly-Si, silicides
Particles cause defects
QM
SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin
• Air quality is measured by the “class” of the facility.
(Photo courtesy of Stanford Nanofabrication Facility.)
Factory environment is cleaned by: • Hepa filters and recirculation for the air, • “Bunny suits” for workers. • Filtration of chemicals and gases. • Manufacturing protocols.
Level 1 Contamination Reduction: Clean Factories
Class 1-100,000 mean number of particles, greater than 0.5 m, in a foot of air
Particles ---> people , machines, supplies
suits
Material filters
Chemicals, water (use DI)
Small particles remain in air (long) coagulate large ones precipitate quickly and deposit on surfaces by (small) Brownian motion and gravitational sedimentation (larger).
Level 3 Contamination Reduction: Gettering• Gettering is used to remove metal ions and alkali ions from device active regions.
• For the alkali ions, gettering generally uses dielectric layers on the topside (PSG or barrier Si3N4 layers).• For metal ions, gettering generally uses traps on the wafer backside or in the wafer bulk.• Backside = extrinsic gettering. Bulk = intrinsic gettering.
Gettering Concepts: contaminants freed diffuse become trapped
Fast Diffusion of Various Impurities
Metal contaminants will be trapped by dislocations and SF (decorate) and far away from ICs
PSG (for alkali ions Na+, K+ and metals) affects E fields (dipoles in PSG) and absorbs water leading to Al corrosion (negative effects)
or Si3N4
Closer to devices than to a backside layer -> high efficiency
metals
SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin
• “Trap” sites can be created by SiO2 precipitates (intrinsic gettering), or by backside damage (extrinsic gettering).
• In intrinsic gettering, CZ silicon is used and SiO2 precipitates are formed in the wafer bulk through temperature cycling at the start of the process.
SiO2 precipitates (white dots) in bulkof wafer.
Intrinsic Gettering Oxygen ~ 1018 cm-3; 15-20 ppm
Oi>20ppm -> too much precipitation-> strength decreases and warpage increases
Oi<10ppm -> no precipitation-> no gettering
denuded zone = oxygen free; thickness several tens of µm
50-100 µm in size
Slow ramp
1-3 nm min size of nuclei, concentrations ≈ 1011cm-3
>> Ddopants but D0<< Dmetals
Intrinsic Gettering Due to Oxide Precipitates
Precipitates (size) grow @ high T
Density of nucleation sites grow @ low T
The largest & the most dense defects -> the most efficient gettering
Measurement Methods
Clean factories = particle control. Detect concentrations < 10/wafer of particles smaller than 0.1 µm
Unpatterened wafers (blank)• Count particles in microscope• Laser scanning systems -> maps of particles down to ≈ 0.2 µm
Patterned wafers• Optical system compares a die with a “known good reference” die (adjacent die, chip design - its appearance) • Image processing identifies defects (SEM)• Test structure (not in high volume manufacturing)
Test Structures
Trapped charge
QT VTH change
Dielectric breakdown due to particles, metals etc.
Water – measure water resistivity Deionized Water =18.5 M
H2O H+ + OH-
Models relate type of defects (typical for processes) with yields
Monitoring the Wafer Cleaning Efficiency
Concentrations of impurities determined by surface analysis
Primary beam – e - good lateral resolution
Detected beam – e – good depth resolution and surface sensitivity
X-ray poor depth resolution and poor surface sensitivity
ions (SIMS) excellent
ions (RBS) good depth resolution, reasonable sensitivity (0.1 atomic%)
• ≈ 75% of yield loss in modern VLSI fabs is due to particle contamination.• Yield models depend on information about the distribution of particles. Yields
models use measured defect density N(dp) and size (dp)
• Particles on the order of 0.1 - 0.3 µm are the most troublesome: • larger particles precipitate easily • smaller ones coagulate into larger particles
• Yields are described by Poisson statistics in the simplest case.
where AC is the critical area and DO the defect density.
• This model assumes independent randomly distributed defects and often underpredicts yields.
Contamination Reduction
Particles 10nm-10 µm
N(dp)=K(dp)-3
Even very small particles leads to failure (pinhole in the oxide )
Models and Simulations
Computer Integrated Manufacturing (CIM) Goal:monitor and control machines, recipes to improve YIELDS
!!
SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin
Modeling Wafer Cleaning• Cleaning involves removing particles, organics (photoresist) and metals from wafer surfaces.• Particles are largely removed by ultrasonic agitation during cleaning.• Organics like photoresists are removed in an O2 plasma or in H2SO4/H2O2 solutions.• The “RCA clean” is used to remove metals and any remaining organics.• Metal cleaning can be understood in terms of the following chemistry.
(5)
(6)
• If we have a water solution with a Si wafer and metal atoms and ions, the stronger reaction will dominate.• Generally (6) is driven to the left and (5) to the right so that SiO2 is formed and M plates out on the wafer.• Good cleaning solutions drive (6) to the right since M+ is soluble and will be desorbed from the wafer surface.
Contamination Reduction: Wafer Cleaning
No models exist but good understanding of cleaning steps
Remove metals by oxidizing (=removing e -> ions) and dissolving in cleaning solutionsSi+2H2O <->SiO2 +4H++4e-
M <-> MZ+ Ze-
Ex. SiO2/Si Fe3+/Fe stronger potential Fe3+ -> Fe. Fe is plating on Si, Si is oxidizingAdd H2O2 stronger potential -> Takes e- from M -> ions soluble in aqueous sol.
Oxidizes SiLarger potential -> reaction to the left all others go to the right
Use OZONE
Manufacturing Methods and Equipment
Wafer Cleaning
High-pH Oxidizes organics -> water soluble compounds and complexes IB IIB and other metals Au, Ag, Cu, Ni, Zn etc.
Low-pHInsoluble in NH4OH
Gettering
All metal atoms mobile (DMi > DMs 10x)
(Fig. 4.8!) DM>> DDopantss
Sol. Sol MI>>MS (Cu, Ni)Sol.Sol. MI<<MS (Au, Pt)
Except of Ti, Mo, etc.
AuS+I Aui kick-out mechanismAus Aui+V dissociative or Frank-Turnbull mech.
I increase improves gettering of AuV increase hinders gettering
Ex. P diffusion, Ion Implant=damage, intrinsic gettering (=I )
“I ” are closer to wafer surface
Metal Diffusion to the Gettering Sites
Long time
Au diffuses to the wafer back side and is trapped
Gettering of Au - the Role of the Back Side Injection of Si-I
Metals diffuse much faster than I (silicon) DSi-I >> DDopants
I are generated at the back and diffuse -> Aui form, diffuse and get trapped
At high T I -> gettering more effective, not limited by the backside injection
Trapping the Metal Atoms at the Gettering SitesTrapped by: ion implantation, P diffusion, laser damage, poly-Si
films, mechanical damage, etc. But HOW?
*Physical damage -> metal trapped at defect sites; binding energy EB depends on
T; Fraction Bound=(1-K1exp-EB/kT)
*Segregation, related to solubility (of substitutional Au) in the silicon perfect crystal and in the gettering regionCAu,Si=NSiexp(-EA1/kT) CAu,G=NGexp(-EA2/kT) -> k0=(CAu,G+CAu,Si)/CAu,Si=1+K2exp-[(EA1-EA2)/kT] --> k0=1+NG/5x1022exp(0.82eV/kT)
*Enhances sol.sol by high dopant concentrations: in “n ” Au=acceptor, “p ” - Au=donorAu+e- Au-, Keq=[Au-]/([Au][e-])=constant, [Au-
i]/[Au]ni= [Au-n]/[Au]n or
[Au-n]/[Au-
i] = n/ni Au acceptor in “n+” Si (100x if N=7.14x1018 -> 1021cm-3
*Ion pairing model -> AuP less strain
* Coulombic attraction Au+P -> Au-P+
* Interaction with point defects V- in “n+” Aui+V- Aus at the trapped site
* Intrinsic gettering - trapping on dislocations and SF which surround precipitates. Dislocations have compressive and tensile stress - accommodate smaller and larger atoms
Limits and Future Trends in Technology and Modeling; Environment
Eliminate defects from wafers: particles, contaminants, clean room -> local=SMIF (standard mechanical interfaceWafer cleaning in future ICs-> less chemicals (liquids, vapors), more diluted (disposal)
New cleaning: •Use ozone• Dry and vapor phase, (Vapors, Plasmas) environment! Cluster tools• Low Energy Physical Processes (sputtering)•Photochemically enhanced clean
Gettering -> intrinsic (less extrinsic), control Oi, Cs, use low T processing, use modeling tool -> point defects engineering, release, diffuse, entrap. Watch for
surface roughness
SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin
• A three-tiered approach is used to minimize contamination in wafer processing.
• Particle control, wafer cleaning and gettering are some of the "nuts and bolts" of chip manufacturing.
• The economic success (i.e. chip yields) of companies manufacturing chips today depends on careful attention to these issues.
• Level 1 control - clean factories through air filtration and highly purified chemicals and gases.
• Level 2 control - wafer cleaning using basic chemistry to remove unwanted elements from wafer surfaces.
• Level 3 control - gettering to collect metal atoms in regions of the wafer far away from active devices.
• The bottom line is chip yield. Since "bad" die are manufactured alongside "good" die, increasing yield leads to better profitability in manufacturing chips.