Silicon Solutions for the Real World Robust Mixed-signal Design in Smart-power IC Processes R. Gillon AMI Semiconductors Belgium ISIE’05 SS8 : Power ICs.

Silicon Solutions for the Real WorldSilicon Solutions for the Real World

Robust Mixed-signal Design

in Smart-power IC Processes

Robust Mixed-signal Design

in Smart-power IC Processes

R. GillonAMI Semiconductors Belgium

ISIE’05 SS8 : Power ICs

2

Silicon Solutions for the Real World 2 / 19Silicon Solutions for the Real World 2 / 19

Smart-power IC’s ?Smart-power IC’s ?

On-board intelligence

Power handling

On-board intelligence : State-machine / logic

Micro-processor

Memory : ROM, RAM, EEPROM, OTP

Communication interfaces :Transmitters, receivers, protocol engines, …

Power handling :Drivers : transistors, diodes

Sensing & Control :Analogue and conversion circuitry

Protections :ESD, EMC, over-temperatures, …

S/H

Diag-nostics

DAC

ADCPGA

AM

UX

EEPROM(Flash+RAM)

OTP

Temp senseHV

BUF

Logic Control Block

RAM

ROM orFlash

JTAG

Timer

PWM

GPIO

Comm. Control

UnitHV

LINTransceiver

LINBSD

RS-232…Drivers :

MotorRelayLampHeat…

Sensor Int. :

HV / LVInductiveCapacitiveResistiveTemperature…

Analog Controland Signal Processing :

Voltage regulatorsAmplifiers, comparatorsADC, DACFilters (SC, GMC, RC) … Vbat to 5V

Regulator

ARM7R8051P

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ph

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Pe

rip

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ion

Digital Signal Processing and Control :

State Machine oruController based

S/H

Diag-nostics

DAC

ADCPGA

AM

UX

EEPROM(Flash+RAM)

OTP

Temp senseHVHVHVHVHV

BUF

Logic Control Block

RAM

ROM orFlash

JTAG

Timer

PWM

GPIO

Comm. Control

UnitHVHV

LINTransceiver

LINBSD

RS-232…Drivers :

MotorRelayLampHeat…

Sensor Int. :

HV / LVInductiveCapacitiveResistiveTemperature…

Analog Controland Signal Processing :

Voltage regulatorsAmplifiers, comparatorsADC, DACFilters (SC, GMC, RC) … Vbat to 5V

Regulator

ARM7R8051P

eri

ph

era

l Ex

ten

sio

n

Pe

rip

he

ral E

xte

ns

ion

Digital Signal Processing and Control :

State Machine oruController based

3


Smart-power IC !Smart-power IC !

Process :ComponentsIsolation schemesInterconnects

PDK :ModelsSymbolsPcellsVerification

IP blocksMemoriesDigital librariesAnalogue blocks

Dri

vers

Logic

Analog

IO's

4


Robust Mixed-signal DesignRobust Mixed-signal Design

Process :Components

Isolation schemes

Interconnects

PDK :Models

Symbols

Pcells

Verification

How to engineer the design-system to enable / favour robust design practices ?

How to engineer the design-system to enable / favour robust design practices ?

5


Robust Mixed-signal DesignRobust Mixed-signal Design

B. Gilbert in “Trade-offs in analog Circuit Design” :

…the art of anticipating, identifying and systematically nulling sensitivities of critical performance

specifications to variances in the manufacturing process and the circuit's environment

Sources of variability (chip-centric universe) :Intrinsic Variations : inherent to the chip fabrication, the selected architecture

Extrinsic Perturbations : interaction of the chip with a variable environment

6


Intrinsic variationsIntrinsic variations

Process variationsDie-to-die

Intra-die (process-induced gradients)

Component mismatch

NoiseIntrinsic noise (semiconductor physics)

Activity noise (induced ‘random’ signals)

Component aging

Electrical (over-)stress

Temperature gradients

Qualification level (process, components)

7


External PerturbationsExternal Perturbations

Better solved by other means …(than IC design)

Eg : moisture

Not quantifiable, but can be minimizedby appropriate measures during IC design

Eg : Mechanical stress degrading transistor matching

Can be quantified and designed forTemperature effectsEMC :

ESD eventsStandardised accidental pulses (eg automtive : Shaffner)Latch-up

8


Process Design Kit ? Process Design Kit ?

Netlist Schematics Layout

ModelsCDFCDFPar. Symbols

CDFCDFCDF PCells

Components Library

Analysis

Library

IP Blocks Library

Verification

CDFCDFProcess

DRC

CDFCDFCompon

CDFCDFOther

CDFCDFIP

LVS

CDFCDFIP

CDFCDF Comp.

CDFCDFConn.

Analysis scripts

FeaturesConnect.

Components

IP Blocks

Isolation

Interconnects

9


Overview of Robustness ToolsOverview of Robustness Tools(*) under development Isolation Interconnects Components

Process Variation LVS, XRC Models

Noise Models

Aging (*) Models

Electrical Stress DRC, LVS, Models LVS Schem., Models

Temp. Gradient (*) Schem., LVS, Models

Qual Level (*) LVS, Models

Ambiant Temp. LVS, Models Schem., LVS Models

ESD DRC, LVS Schem., LVS Schem., Models

Accidental Pulses

EME / EMS (*) XRC ? Schem.

Latch-up (*) DRC, LVS Schem., Models, Pcells,

Inte

rna

l Va

ria

tio

ns

Ex

t. P

ert

urb

atio

ns

10


Managing Electrical Stress RisksManaging Electrical Stress Risks

Introducing different voltage ratingsFor famillies of nets (through labelling)

For diffused pockets (tubs)

Formal management of connectivity of components, tubs, etc. according to ratings

DRC rules on nets and pins

Electrical rule check at schematics level

Safe-operating area flagging during simulationC1

C2 M1

H1 H3M4

80V80V

20V20V

3.3V3.3V

SUB1 SUB2 SUB1

C320V20V 20V

M3

20V20V

80V80V

20V20V

80V80V

Psubdiode?

80V80V

H280V80V

C4

80V80V

M220V20V

SYSTEM OF POCKET VOLTAGES :

HV pocketMV pocketLV pocket

H MC

HV devicesMV devicesLV device

FAILURES

H

M

H

11


Static approach or guard-bandingThe life-times under constant stress are extracted

Models issue safe-operating area messages according to selected target life-times

Covers most basic needs

Managing Component Aging RisksManaging Component Aging Risks

Forbidden region

1e4s

10s

25y

1y

1e4s1y

140h

1e6s

Forbidden region

1e4s

10s

25y

1y

1e4s1y

140h

1e6s

12


Static approach or guard-bandingThe life-times under constant stress are extracted

Models issue safe-operating area messages according to selected target life-times

Covers most basic needs

Computation of dynamic agingDetermination of aging rate

Computation of parameter shifts according to age

Managing Component Aging RisksManaging Component Aging Risks

n

n

AgeC

AgeC

P

P

2

1

0 1

i

it

D

subD

I

I

W

I

dt

Aged

13


Managing Process VariationsManaging Process Variations

Die-to-die variationsStudy distributions of key electrical parameters

Determine dominant modes of variations (correlations)DMOS

MOS

bipolars

capacitors

diode

resistors

DMOS

MOS

bipolars

capacitors

diode

resistors

correlation matrixspy plot

14


Managing Process VariationsManaging Process Variations

Die-to-die variationsStudy distributions of key electrical parameters

Determine dominant modes of variations (correlations)

Identify correlation groups

Build sets of corners for each correlation group

Alternatively provide process Monte-Carlo models

Modelling paradoxStatistical data is available in electrical parameters

ETest parameters are not model parameters

Either repeat extraction many times or build special mapping techniques

Id

Vd

Id

Vd

Id

Vd

VTHGMmaxIDsatRontox

vth0u0

vsatR

tox

VTHGmmaxIDsatRontox

NeuralNetwork

vth0u0

vsatR

tox

Measurements

Model Par. Vectors

E-Test Vectors Model Par. Vectors

Simulations

Typical Model

DOESensitivity Ranking

E-Test Vectors

Neural Network Training

Id

Vd

Id

Vd

Id

Vd

VTHGMmaxIDsatRontox

vth0u0

vsatR

tox

VTHGmmaxIDsatRontox

NeuralNetwork

vth0u0

vsatR

tox

Measurements

Model Par. Vectors


Simulations

Typical Model


E-Test Vectors


Id

Vd

Id

Vd

Id

Vd

Id

Vd

Id

Vd

Id

Vd

VTHGMmaxIDsatRontox

vth0u0

vsatR

tox

VTHGmmaxIDsatRontox

NeuralNetwork

vth0u0

vsatR

tox

Measurements

Model Par. Vectors


Simulations

Typical Model


E-Test Vectors


15


Managing External PerturbationsManaging External Perturbations

Electro-Magnetic CompatibilityStandards for Emission and Susceptibility simulations

Typically from low frequency till 1GHzDielectric transition frequencies of silicon substrate

Redistribution of current filaments in metals not properly modelled in most EM simulation tools (avoid to solve electric and magnetic fields in the conductors).

Need to assess realism of EMC simulations comparing impedance levels at tip of package lead

16


Managing External PerturbationsManaging External PerturbationsTesting ESD protection strategy

Smart-power IC’s can have very complex interfaceMany different supply levels

IO pins with different voltage ratings

Very large number of pins

Wide variety of ESD protection cells

Tool for testing topology of ESD protection schemeDrop-in replacement of all component models by simplified breakdown models

Forcing of static current in IO pins

Detection of current paths through simulation

Flagging of breakdowns outside of ESD protection cells

Extension to detect risks of dynamic failures

Completed by specific DRC check and generic LVS

17


Managing Learning ProcessesManaging Learning Processes

Road-map for Smart-power technologies

Progressive introduction of new features to meet the needs and timings of different markets

Consumer

Automotive, Aero, Military

Medical

Several nested feedback loops

Tools to support / channel feedbackHelpdesk systems

Tracking of qualification status at component level

Quality systems : Waivering systems for rule violations, …

18


ConclusionsConclusions

Stimulate robustness by constructionTackle risks as early as possible in the design process

Favor analytical approaches w.r.t. predefined push-button solution

Efficiency and flexibility of solutions is critical

Enabling robustness requires holistic approach to PDK engineering

ROBUSPIC projects is addressing key topics in enabling methodologies for robust design

19


AcknowledgementsAcknowledgements

6th framework program (IST) for funding of the ROBUSPIC program

Partners in ROBUSPIC :

Silicon Solutions for the Real World Robust Mixed-signal Design in Smart-power IC Processes R. Gillon AMI Semiconductors Belgium ISIE’05 SS8 : Power ICs.

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