Silicon Silicon Photomultiplier Photomultiplier Readout Electronics Readout Electronics for the GlueX for the GlueX Tagger Microscope Tagger Microscope Hall D Electronics Meeting, Newport News, Oct. 23-24, 2007 Richard Jones, Igor Senderovich and Brendan Krueger Richard Jones, Igor Senderovich and Brendan Krueger University of Connecticut University of Connecticut
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Silicon Photomultiplier Readout Electronics for the GlueX Tagger Microscope Hall D Electronics Meeting, Newport News, Oct. 23-24, 2007 Richard Jones, Igor.
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Hall D Electronics Meeting, Newport News, Oct. 23-24, 2007
Richard Jones, Igor Senderovich and Brendan KruegerRichard Jones, Igor Senderovich and Brendan KruegerUniversity of ConnecticutUniversity of Connecticut
Hall D Electronics Meeting, Newport News, Oct. 23-24, 2007Hall D Electronics Meeting, Newport News, Oct. 23-24, 2007 22
OutlineOutline
1.1. Detector overview and requirementsDetector overview and requirements
1.1. preamps mounted on the PCB together with the preamps mounted on the PCB together with the
SiPM – noise immunitySiPM – noise immunity
2.2. preamp transimpedence gain 3Kpreamp transimpedence gain 3K
3.3. rise time 1-2 ns, fall time 10-20 nsrise time 1-2 ns, fall time 10-20 ns
4.4. formation of individual and 5-way sum analog formation of individual and 5-way sum analog
signals driven into 50signals driven into 50
5.5. VVbiasbias programmable in steps of 0.1 V individually programmable in steps of 0.1 V individually
for each SiPMfor each SiPM
6.6. VVbias bias programmable range must coverprogrammable range must cover 0 V – enable selective enabling of rows of pixels 0 V – enable selective enabling of rows of pixels
20 V – Vbd of current preferred photonique SiPM20 V – Vbd of current preferred photonique SiPM
70 V – Vbd of attractive alternative Hamamatsu SiPM70 V – Vbd of attractive alternative Hamamatsu SiPM
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Conceptual design IConceptual design I
basic preamp design, recommended by Photonique
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Vbias readback using mulitplexed ADCVbias readback using mulitplexed ADC
temperature monitoring (for free)temperature monitoring (for free)
FPGA provides interfaceFPGA provides interface
Embedded ethernet Embedded ethernet technologytechnologyprovides cheap and flexibleprovides cheap and flexiblecommunications buscommunications bus
Hall D Electronics Meeting, Newport News, Oct. 23-24, 2007Hall D Electronics Meeting, Newport News, Oct. 23-24, 2007 1313
ImplementationImplementation
1.1. Xilinx FPGAXilinx FPGA
2.2. external components modeled in VHDLexternal components modeled in VHDL
3.3. detailed simulation during and after detailed simulation during and after design using Xilinx development toolsdesign using Xilinx development tools
4.4. robust set of test sequences to exercise robust set of test sequences to exercise major functionsmajor functions
5.5. ethernet complexity handled by ethernet ethernet complexity handled by ethernet controller – only host bus side simulatedcontroller – only host bus side simulated
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ImplementationImplementation
Example: Addressing and initialization schemeExample: Addressing and initialization scheme
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Project status and plansProject status and plans
1.1. Project started by 1 undergraduate student Project started by 1 undergraduate student
summer 2007summer 2007
2.2. Taken over fall 2007 by graduate student Taken over fall 2007 by graduate student
3.3. VHDL design of digital side 70% finishedVHDL design of digital side 70% finished
4.4. Single channel of preamp passed tests on benchSingle channel of preamp passed tests on bench