SHIKSHA PPT.pptx

OPTIMAL BODY BIASING FOR MINIMUM LEAKAGE POWER

IN STANDBY MODEPresented by:

Shiksha(3126019)

CONTENTS• Introduction• Leakage component in CMOS circuit• Effect of leakage power• Power minimizing system• Optimal body biasing technique in standby mode • Effect or body bias voltage on delay• Conclusion• References

INTRODUCTION

• New power minimizing method by optimizing supply voltage control and minimizing leakage in active and stanbymode.

• ACTIVE MODE: control system determines optimal trade off between supply voltage and forward body bias voltage.

• STANDBY MODE: optimal body bias technique to monitor leakage components.

LEAKAGE COMPONENT IN CMOS

LEAKAGE COMPONENT IN CMOS

• In off state main leakage componets are Isubstrate

Igidl

Igate

Ibtbt

• In on state Igate is main component.

• Vth = threshold voltage

• Vsb = source substrate voltage

• Cox = gate oxide capacitance• m = substrate swing constant

• Vt = thermal voltage• Fermi potential = • Perittvity of si =

EFFFECT OF LEAKAGE POWER LEAKAGE

• Power consumed in processor is • Power = dynamic power+ static leakage +short

circuit power• short circuit power occurs during signal

transition and is neglected if the circuit is carefully designed.

• P total =C ef f V^2 f + P leakage - - - - - - - -(1)

cont

• Pleakage = Pgate + Psubthreshold + Pbtbt

• optimal body bias voltage to minimize power dissipation is determined by the relationship between Isubthreshold and Ibtbt.

Isubth = As e^Bsvbody - - - - - - - - - -(2) Ibtbt =As e^Bbvbody - - - - - - - - - - - - - (3)

cont

• Ab ,Bb ,As ,Bs are technology dependent constant.

• Vbody = body bias voltage• Condition for minimum leakage power is given

by

POWER MINIMIZING SYSTEM

cont

• ACTIVE MODE : Step 1: monitor the delay of critical replica.Step 2: if the delay of replica is faster than required delay ,supply voltage control system start to decrease the voltage. Step 3: if the delay of replica is slower than required delay forward body bias system start to increase the voltage

cont

• STANDBY MODE:• Step 1: monitor each leakage component.• Step 2: subthreshold leakage current and band

to band leakage current are compared to each other.

• Step 3: if Isubth is greter than BTBT leakage , reverse body bias will increase.

• Step 4: if Isubth is smaller than btbt leakage forward body bias will increase.

cont

• Optimal leakage point in standby mode is the point where

Isubth = Ibtbt

OPTIMAL BODY BIASING TECHNIQUE IN STANDBY MODE

• Reverse body bias used to reduce leakage power of device.

• if reverse bias is too high leakage power can be increased due to contribution of Ibtbt.

• New system increased vth by adjusting body voltage in reverse bias direction to reduce subthreshold leakage current.

LEAKAGE MONITORING CIRCUIT

OPTIMAL BODY BIASED SYSTEM

RESULTS

• The delay of a gate is a function of both the power supply and the threshold voltage of transistors.

CONCLUSION

• In the active mode control system determines optimal trade-off between supply voltage and forward body bias voltage to satisfy the performance requirement.

• In standby mode new optimal body bias technique is used to reduce leakage current by applying optimal substrate bias voltage.

• Optimal body bias produces high energy reduction in nanoscale CMOS and feedback loop compensates variation in supply voltage and temperature.

REFERENCES[1] Kaushik Roy, et al., ”Leakage Current Mechanisms and Leakage Reduction Techniques in Deep-Submicrometer CMOS Circutis”,Proceeding of the IEEE, VOL.91, NO.2, Feb.2003.[2] Cassondra Neau, Kaushik Roy, ”Optimal Body Bias Selectin for Leakge Improvement and Process Compensation Over Different Technolog Generations”, ISLEP’03, pp.116-121, August 2003.[3] Kyung Ki Kim, Yong-Bin Kim, “Optimal Body Biasing for Minimum Leakage Power in Standby Mode”, IEEE International Symposium on Circuits and Systems, New Orleans, LA, May 27-30, 2007, pp.1161-1164.[4] Shih-Fen Huang Wann, C. Yu-Shyang Huang Chih-Yung Lin Schafbauer, T. Shui-Ming Cheng Yao-Ching Cheng Vietzke, D. Eller, M. Chuan Lin Quiyi Ye Rovedo, N. Biesemans,S. Nguyen, P. Dennard, R. Bomy Chen, “Scalability a strategy for CMOS with active well bias”, 2001 Symposium on Digest of Technical Papers VLSI Technology, pp107-108, June 12, 2001[5] Kyung Ki Kim, Yong-Bin Kim, Minsu Choi, Nohpill Park, “Leakage Minimization Technique For Nanoscale CMOS VLSI Based on Macro- Cell Modeling”, IEEE Design and Test of Computers, July-August, 2007, pp 322-330

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