SHARC Processors ADSP-21367/ADSP-21368/ADSP-21369€¦ · pm data bus dm data bus pm address bus 32 dm address bus 64 processing px register element (pey) timer instruction cache

SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.

SHARC ProcessorsADSP-21367/ADSP-21368/ADSP-21369

Rev. DInformation furnished by Analog Devices is believed to be accurate and reliable.However, no responsibility is assumed by Analog Devices for its use, nor for anyinfringements of patents or other rights of third parties that may result from its use.Specifications subject to change without notice. No license is granted by implicationor otherwise under any patent or patent rights of Analog Devices. Trademarks andregistered trademarks are the property of their respective companies.

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SUMMARYHigh performance 32-bit/40-bit floating-point processor

optimized for high performance audio processingSingle-instruction, multiple-data (SIMD) computational

architectureOn-chip memory—2M bits of on-chip SRAM and 6M bits of

on-chip mask programmable ROMCode compatible with all other members of the SHARC family

The ADSP-21367/ADSP-21368/ADSP-21369 are available with a 400 MHz core instruction rate with unique audiocen-tric peripherals such as the digital applications interface, S/PDIF transceiver, serial ports, 8-channel asynchronous sample rate converter, precision clock generators, and more. For complete ordering information, see Ordering Guide on Page 55.

Figure 1. Functional Block Diagram

SPI PORT (2)

TIMERS (3)

2-WIREINTERFACE

UART (2)

DP

I RO

UT

ING

UN

IT

DIGITAL PERIPHERAL INTERFACE

GPIO FLAGS/IRQ/TIMEXP

4SERIAL PORTS (8)

INPUT DATA PORT/PDAP

DA

I RO

UT

ING

UN

IT

SPDIF (Rx/Tx)

DIGITAL APPLICATIONS INTERFACE

IOD(32)

ADDR DATA

IOA(19)

4 BLOCKS OFON-CHIP MEMORY

PM DATA BUS

DM DATA BUS

32PM ADDRESS BUS

DM ADDRESS BUS

64

PX REGISTERPROCESSINGELEMENT

(PEY)

TIMERINSTRUCTION

CACHE32 48-BIT

DAG18 4 32

PROGRAMSEQUENCER

DMACONTROLLER34 CHANNELS

S

MEMORY-TO-MEMORY DMA (2)

IOP REGISTER (MEMORY MAPPED)CONTROL, STATUS, AND DATA BUFFERS

JTAG TEST & EMULATION

I/O PROCESSOR

DAI PINS DPI PINS

64

32

1420

SRC (8 CHANNELS)

PRECISION CLOCKGENERATORS (4)

24

18

SDRAMCONTROLLER

ADDRESS

CONTROL

3

7

ASYNCHRONOUSMEMORY INTERFACE

SHARED MEMORYINTERFACE

8

EXTERNAL PORT

CO

NT

RO

L P

INS

4 PWMs32

DATA

FLAGS0-15

CORE PROCESSOR

DAG28 4 32

PROCESSINGELEMENT

(PEX)

2M BIT RAM6M BIT ROM

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Rev. D | Page 2 of 56 | November 2008

ADSP-21367/ADSP-21368/ADSP-21369

KEY FEATURES—PROCESSOR COREAt 400 MHz (2.5 ns) core instruction rate, the processors per-

form 2.4 GFLOPS/800 MMACS2M bit on-chip SRAM (0.75M bit in blocks 0 and 1, and

0.25M bit in blocks 2 and 3) for simultaneous access by the core processor and DMA

6M bit on-chip, mask-programmable ROM (3M bit in block 0 and 3M bit in block 1)

Dual data address generators (DAGs) with modulo and bit-reverse addressing

Zero-overhead looping with single-cycle loop setup, provid-ing efficient program sequencing

Single-instruction, multiple-data (SIMD) architecture providesTwo computational processing elementsConcurrent executionCode compatibility with other SHARC family members at

the assembly levelParallelism in buses and computational units allows:

single-cycle executions (with or without SIMD) of a mul-tiply operation, an ALU operation, a dual memory read or write, and an instruction fetch

Transfers between memory and core at a sustained 6.4 Gbps bandwidth at 400 MHz core instruction rate

INPUT/OUTPUT FEATURESDMA controller supports

34 zero-overhead DMA channels for transfers between internal memory and a variety of peripherals

32-bit DMA transfers at peripheral clock speed, in parallel with full-speed processor execution

32-bit wide external port provides glueless connection to both synchronous (SDRAM) and asynchronous memory devices

Programmable wait state options: 2 SCLK to 31 SCLK cyclesDelay-line DMA engine maintains circular buffers in exter-

nal memory with tap-/offset-based readsSDRAM accesses at 166 MHz and asynchronous accesses at

55 MHzShared-memory support (ADSP-21368 only) allows multi-

ple DSPs to automatically arbitrate for the bus and gluelessly access a common memory device

Shared memory interface (ADSP-21368 only) support pro-vides Glueless connection for scalable DSP multiprocessing architecture

Distributed on-chip bus arbitration for parallel busConnect of up to four ADSP-21368 processors and global memory

Four memory select lines allow multiple external memory devices

Digital applications interface (DAI) includes eight serial ports, four precision clock generators, an input data port, an S/PDIF transceiver, an 8-channel asynchronous sample rate converter, and a signal routing unit

Digital peripheral interface (DPI) includes three timers, two UARTs, two SPI ports, and a 2-wire interface port

Outputs of PCGs C and D can be driven on to DPI pins8 dual data line serial ports that operate at up to

50 Mbps on each data line—each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair

TDM support for telecommunications interfaces including 128 TDM channel support for newer telephony interfaces such as H.100/H.110

Up to 16 TDM stream support, each with 128 channels per frame

Companding selection on a per channel basis in TDM modeInput data port, configurable as eight channels of serial data

or seven channels of serial data and up to a 20-bit wide parallel data channel

Signal routing unit provides configurable and flexible con-nections between all DAI/DPI components

2 muxed flag/IRQ lines1 muxed flag/timer expired line /MS pin1 muxed flag/IRQ /MS pin

DEDICATED AUDIO COMPONENTSS/PDIF-compatible digital audio receiver/transmitter sup-

ports EIAJ CP-340 (CP-1201), IEC-958, AES/EBU standards,left-justified, I2S, or right-justified serial data input with 16-, 18-, 20- or 24-bit word widths (transmitter)

4 independent asynchronous sample rate converters (SRC). Each converter has separate serial input and output ports, a de-emphasis filter providing up to –140 dB SNR perfor-mance, stereo sample rate converter, and supports left-justified, I2S, TDM, and right-justified modes and 24-, 20-, 18-, and 16-audio data word lengths

Pulse-width modulation provides16 PWM outputs configured as four groups of four outputs supports center-aligned or edge-aligned PWM waveforms

ROM-based security features includeJTAG access to memory permitted with a 64-bit keyProtected memory regions that can be assigned to limit

access under program control to sensitive codePLL has a wide variety of software and hardware multi-

plier/divider ratiosDual voltage: 3.3 V I/O, 1.2 V or 1.3 V coreAvailable in 256-ball BGA_ED and 208-lead LQFP_EP pack-

ages (see Ordering Guide on Page 55)

ADSP-21367/ADSP-21368/ADSP-21369


TABLE OF CONTENTS

Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Key Features—Processor Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Input/Output Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Dedicated Audio Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Table Of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

SHARC Family Core Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4Memory Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5External Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5I/O Processor Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7System Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Development Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Additional Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Pin Function Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Data Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15Boot Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15Core Instruction Rate to CLKIN Ratio Modes . . . . . . . . . . . . . 15

Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17ESD Caution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17Output Drive Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45Capacitive Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

256-Ball BGA_ED Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48208-Lead LQFP_EP Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Surface-Mount Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53Automotive Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

REVISION HISTORY11/08—Rev. C to Rev. DCorrected all outstanding document errata.Changed digital audio interface to digital applications interface throughout this document. This change is a naming convention change only and does not effect the operation or specification of this product in any way.Corrected Functional Block Diagram 1Revised specification in Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Revised tDDTE, tSCLK, tSCLKW specifications in Serial Ports . . . . .32 Revised tIDPCLK, tIDPCLKW specifications in Input Data Port . .36 Revised tPDCLK, tPDCLKW specifications in Parallel Data Acquisi-tion Port (PDAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Revised tSRCCLK, tSRCCLKW specifications in Sample Rate Con-verter—Serial Input Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Sample Rate Converter—Serial Input Port . . . . . . . . . . . . . . . . . . . . .38Added 350 MHz models. See Operating Conditions on Page 16, Clock Input on Page 20, SDRAM Interface Timing (166 MHz SDCLK) on Page 26, and Ordering Guide . . . . . . . . . . . . . . . . . . . . .55Added Automotive Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55


ADSP-21367/ADSP-21368/ADSP-21369

GENERAL DESCRIPTIONThe ADSP-21367/ADSP-21368/ADSP-21369 SHARC® proces-sors are members of the SIMD SHARC family of DSPs that feature Analog Devices’ Super Harvard Architecture. These pro-cessors are source code-compatible with the ADSP-2126x and ADSP-2116x DSPs as well as with first generation ADSP-2106x SHARC processors in SISD (single-instruction, single-data) mode. The processors are 32-bit/40-bit floating-point proces-sors optimized for high performance automotive audio applications with its large on-chip SRAM, mask programmable ROM, multiple internal buses to eliminate I/O bottlenecks, and an innovative digital applications interface (DAI).As shown in the functional block diagram on Page 1, the processors use two computational units to deliver a significant performance increase over the previous SHARC processors on a range of DSP algorithms. Fabricated in a state-of-the-art, high speed, CMOS process, the ADSP-21367/ADSP-21368/ADSP-21369 processors achieve an instruction cycle time of up to 2.5 ns at 400 MHz. With its SIMD computational hardware, the processors can perform 2.4 GFLOPS running at 400 MHz. Table 1 shows performance benchmarks for these devices.

The ADSP-21367/ADSP-21368/ADSP-21369 processors con-tinue SHARC’s industry-leading standards of integration for DSPs, combining a high performance 32-bit DSP core with inte-grated, on-chip system features. The block diagram of the ADSP-21368 on Page 1 illustrates the following architectural features:

• Two processing elements, each of which comprises an ALU, multiplier, shifter, and data register file

• Data address generators (DAG1, DAG2)• Program sequencer with instruction cache• PM and DM buses capable of supporting four 32-bit data

transfers between memory and the core at every core pro-cessor cycle

• Three programmable interval timers with PWM genera-tion, PWM capture/pulse width measurement, and external event counter capabilities

• On-chip SRAM (2M bit)• On-chip mask-programmable ROM (6M bit)• JTAG test access port

The block diagram of the ADSP-21368 on Page 1 also illustrates the following architectural features:

• DMA controller• Eight full-duplex serial ports• Digital applications interface that includes four precision

clock generators (PCG), an input data port (IDP), an S/PDIF receiver/transmitter, eight channels asynchronous sample rate converters, eight serial ports, a 16-bit parallel input port (PDAP), a flexible signal routing unit (DAI SRU).

• Digital peripheral interface that includes three timers, a 2-wire interface, two UARTs, two serial peripheral interfaces (SPI), and a flexible signal routing unit (DPI SRU).

SHARC FAMILY CORE ARCHITECTUREThe ADSP-21367/ADSP-21368/ADSP-21369 are code compati-ble at the assembly level with the ADSP-2126x, ADSP-21160, and ADSP-21161, and with the first generation ADSP-2106x SHARC processors. The ADSP-21367/ADSP-21368/ADSP-21369 processors share architectural features with the ADSP-2126x and ADSP-2116x SIMD SHARC processors, as detailed in the following sections.

SIMD Computational Engine

The processors contain two computational processing elements that operate as a single-instruction, multiple-data (SIMD) engine. The processing elements are referred to as PEX and PEY and each contains an ALU, multiplier, shifter, and register file. PEX is always active, and PEY may be enabled by setting the PEYEN mode bit in the MODE1 register. When this mode is enabled, the same instruction is executed in both processing ele-ments, but each processing element operates on different data. This architecture is efficient at executing math intensive DSP algorithms.Entering SIMD mode also has an effect on the way data is trans-ferred between memory and the processing elements. When in SIMD mode, twice the data bandwidth is required to sustain computational operation in the processing elements. Because of this requirement, entering SIMD mode also doubles the band-width between memory and the processing elements. When using the DAGs to transfer data in SIMD mode, two data values are transferred with each access of memory or the register file.

Independent, Parallel Computation Units

Within each processing element is a set of computational units. The computational units consist of an arithmetic/logic unit (ALU), multiplier, and shifter. These units perform all opera-tions in a single cycle. The three units within each processing element are arranged in parallel, maximizing computational throughput. Single multifunction instructions execute parallel

Table 1. Processor Benchmarks (at 400 MHz)

Benchmark AlgorithmSpeed (at 400 MHz)

1024 Point Complex FFT (Radix 4, with reversal) 23.2 μsFIR Filter (per tap)1

1 Assumes two files in multichannel SIMD mode.

1.25 ns IIR Filter (per biquad)1 5.0 ns Matrix Multiply (pipelined)

[3×3] × [3×1][4×4] × [4×1]

11.25 ns20.0 ns

Divide (y/x) 8.75 ns Inverse Square Root 13.5 ns

ADSP-21367/ADSP-21368/ADSP-21369


ALU and multiplier operations. In SIMD mode, the parallel ALU and multiplier operations occur in both processing elements. These computation units support IEEE 32-bit single-precision floating-point, 40-bit extended precision floating-point, and 32-bit fixed-point data formats.

Data Register File

A general-purpose data register file is contained in each pro-cessing element. The register files transfer data between the computation units and the data buses, and store intermediate results. These 10-port, 32-register (16 primary, 16 secondary) register files, combined with the ADSP-2136x enhanced Har-vard architecture, allow unconstrained data flow between computation units and internal memory. The registers in PEX are referred to as R0–R15 and in PEY as S0–S15.

Single-Cycle Fetch of Instruction and Four Operands

The ADSP-21367/ADSP-21368/ADSP-21369 feature an enhanced Harvard architecture in which the data memory (DM) bus transfers data and the program memory (PM) bus transfers both instructions and data (see Figure 1 on Page 1). With separate program and data memory buses and on-chip instruction cache, the processors can simultaneously fetch four operands (two over each data bus) and one instruction (from the cache), all in a single cycle.

Instruction Cache

The processors include an on-chip instruction cache that enables three-bus operation for fetching an instruction and four data values. The cache is selective—only the instructions whose fetches conflict with PM bus data accesses are cached. This cache allows full-speed execution of core, looped operations such as digital filter multiply-accumulates, and FFT butterfly processing.

Data Address Generators with Zero-Overhead Hardware Circular Buffer Support

The ADSP-21367/ADSP-21368/ADSP-21369 have two data address generators (DAGs). The DAGs are used for indirect addressing and implementing circular data buffers in hardware. Circular buffers allow efficient programming of delay lines and other data structures required in digital signal processing, and are commonly used in digital filters and Fourier transforms. The two DAGs contain sufficient registers to allow the creation of up to 32 circular buffers (16 primary register sets, 16 second-ary). The DAGs automatically handle address pointer wraparound, reduce overhead, increase performance, and sim-plify implementation. Circular buffers can start and end at any memory location.

Flexible Instruction Set

The 48-bit instruction word accommodates a variety of parallel operations for concise programming. For example, the ADSP-21367/ADSP-21368/ADSP-21369 can conditionally exe-cute a multiply, an add, and a subtract in both processing elements while branching and fetching up to four 32-bit values from memory—all in a single instruction.

MEMORY ARCHITECTUREThe ADSP-21367/ADSP-21368/ADSP-21369 processors add the following architectural features to the SIMD SHARC family core.

On-Chip Memory

The processors contain two megabits of internal RAM and six megabits of internal mask-programmable ROM. Each block can be configured for different combinations of code and data stor-age (see Table 2 on Page 6). Each memory block supports single-cycle, independent accesses by the core processor and I/O processor. The memory architecture, in combination with its separate on-chip buses, allows two data transfers from the core and one from the I/O processor, in a single cycle.The SRAM can be configured as a maximum of 64k words of 32-bit data, 128k words of 16-bit data, 42k words of 48-bit instructions (or 40-bit data), or combinations of different word sizes up to two megabits. All of the memory can be accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit floating-point storage format is supported that effectively doubles the amount of data that can be stored on-chip. Conversion between the 32-bit floating-point and 16-bit floating-point formats is per-formed in a single instruction. While each memory block can store combinations of code and data, accesses are most efficient when one block stores data using the DM bus for transfers, and the other block stores instructions and data using the PM bus for transfers.Using the DM bus and PM buses, with one bus dedicated to each memory block, assures single-cycle execution with two data transfers. In this case, the instruction must be available in the cache.

EXTERNAL MEMORY The external port provides a high performance, glueless inter-face to a wide variety of industry-standard memory devices. The 32-bit wide bus can be used to interface to synchronous and/or asynchronous memory devices through the use of its separate internal memory controllers. The first is an SDRAM controller for connection of industry-standard synchronous DRAM devices and DIMMs (dual inline memory module), while the second is an asynchronous memory controller intended to interface to a variety of memory devices. Four memory select pins enable up to four separate devices to coexist, supporting any desired combination of synchronous and asynchronous device types. Non-SDRAM external memory address space is shown in Table 3.

SDRAM Controller

The SDRAM controller provides an interface of up to four sepa-rate banks of industry-standard SDRAM devices or DIMMs, at speeds up to fSCLK. Fully compliant with the SDRAM standard, each bank has its own memory select line (MS0–MS3), and can be configured to contain between 16M bytes and 128M bytes of memory. SDRAM external memory address space is shown in Table 4.


ADSP-21367/ADSP-21368/ADSP-21369

A set of programmable timing parameters is available to config-ure the SDRAM banks to support slower memory devices. The memory banks can be configured as either 32 bits wide for max-imum performance and bandwidth or 16 bits wide for minimum device count and lower system cost. The SDRAM controller address, data, clock, and control pins can drive loads up to distributed 30 pF loads. For larger memory systems, the SDRAM controller external buffer timing should be selected and external buffering should be provided so that the load on the SDRAM controller pins does not exceed 30 pF.

Asynchronous Controller

The asynchronous memory controller provides a configurable interface for up to four separate banks of memory or I/O devices. Each bank can be independently programmed with dif-ferent timing parameters, enabling connection to a wide variety of memory devices including SRAM, ROM, flash, and EPROM, as well as I/O devices that interface with standard memory con-trol lines. Bank 0 occupies a 14M word window and Banks 1, 2, and 3 occupy a 16M word window in the processor’s address space but, if not fully populated, these windows are not made contiguous by the memory controller logic. The banks can also be configured as 8-bit, 16-bit, or 32-bit wide buses for ease of interfacing to a range of memories and I/O devices tailored either to high performance or to low cost and power.

Table 2. Internal Memory Space 1

IOP Registers 0x0000 0000–0x0003 FFFF

Long Word (64 Bits)Extended Precision Normal or Instruction Word (48 Bits) Normal Word (32 Bits) Short Word (16 Bits)

Block 0 ROM (Reserved)0x0004 0000–0x0004 BFFF

Block 0 ROM (Reserved)0x0008 0000–0x0008 FFFF

Block 0 ROM (Reserved)0x0008 0000–0x0009 7FFF


Reserved0x0004 F000–0x0004 FFFF

Reserved 0x0009 4000–0x0009 FFFF

Reserved0x0009 E000–0x0009 FFFF

Reserved0x0013 C000–0x0013 FFFF

Block 0 SRAM0x0004 C000–0x0004 EFFF

Block 0 SRAM0x0009 0000–0x0009 3FFF

Block 0 SRAM0x0009 8000–0x0009 DFFF

Block 0 SRAM0x0013 0000–0x0013 BFFF

Block 1 ROM (Reserved)0x0005 0000–0x0005 BFFF

Block 1 ROM (Reserved)0x000A 0000–0x000A FFFF

Block 1 ROM (Reserved)0x000A 0000–0x000B 7FFF


Reserved0x0005 F000–0x0005 FFFF

Reserved 0x000B 4000–0x000B FFFF

Reserved0x000B E000–0x000B FFFF

Reserved0x0017 C000–0x0017 FFFF

Block 1 SRAM0x0005 C000–0x0005 EFFF

Block 1 SRAM0x000B 0000–0x000B 3FFF

Block 1 SRAM0x000B 8000–0x000B DFFF

Block 1 SRAM0x0017 0000–0x0017 BFFF


Block 2 SRAM0x000C 0000–0x000C 1554

Block 2 SRAM0x000C 0000–0x000C 1FFF


Reserved0x0006 1000– 0x0006 FFFF

Reserved0x000C 1555–0x000C 3FFF

Reserved0x000C 2000–0x000D FFFF

Reserved0x0018 4000–0x001B FFFF


Block 3 SRAM0x000E 0000–0x000E 1554

Block 3 SRAM0x000E 0000–0x000E 1FFF

Block 3 SRAM0x001C 0000–0x001C 3FFF

Reserved0x0007 1000–0x0007 FFFF

Reserved 0x000E 1555–0x000F FFFF

Reserved0x000E 2000–0x000F FFFF

Reserved0x001C 4000–0x001F FFFF

1 The ADSP-21368 and ADSP-21369 processors include a customer-definable ROM block. Please contact your Analog Devices sales representative for additional details.

Table 3. External Memory for Non-SDRAM Addresses

BankSize in Words Address Range

Bank 0 14M 0x0020 0000–0x00FF FFFF

Bank 1 16M 0x0400 0000–0x04FF FFFF

Bank 2 16M 0x0800 0000–0x08FF FFFF

Bank 3 16M 0x0C00 0000–0x0CFF FFFF

Table 4. External Memory for SDRAM Addresses

BankSize in Words Address Range

Bank 0 62M 0x0020 0000–0x03FF FFFF

Bank 1 64M 0x0400 0000–0x07FF FFFF

Bank 2 64M 0x0800 0000–0x0BFF FFFF

Bank 3 64M 0x0C00 0000–0x0FFF FFFF

ADSP-21367/ADSP-21368/ADSP-21369


The asynchronous memory controller is capable of a maximum throughput of 220 Mbps using a 55 MHz external bus speed. Other features include 8-bit to 32-bit and 16-bit to 32-bit pack-ing and unpacking, booting from Bank Select 1, and support for delay line DMA.

Shared External Memory

The ADSP-21368 processor supports connecting to common shared external memory with other ADSP-21368 processors to create shared external bus processor systems. This support includes:

• Distributed, on-chip arbitration for the shared external bus• Fixed and rotating priority bus arbitration• Bus time-out logic• Bus lock

Multiple processors can share the external bus with no addi-tional arbitration logic. Arbitration logic is included on-chip to allow the connection of up to four processors. Bus arbitration is accomplished through the BR1-4 signals and the priority scheme for bus arbitration is determined by the set-ting of the RPBA pin. Table 5 on Page 12 provides descriptions of the pins used in multiprocessor systems.

I/O PROCESSOR FEATURESThe I/O processor provides 34 channels of DMA, as well as an extensive set of peripherals. These include a 20-pin digital appli-cations interface which controls:

• Eight serial ports• S/PDIF receiver/transmitter• Four precision clock generators• Four stereo sample rate converters• Input data port/parallel data acquisition port

The processors also contain a 14-pin digital peripheral interface which controls:

• Three general-purpose timers• Two serial peripheral interfaces• Two universal asynchronous receiver/transmitters

(UARTs)• A 2-wire interface (TWI, I2C-compatible)

DMA Controller

The processor’s on-chip DMA controller allows data transfers without processor intervention. The DMA controller operates independently and invisibly to the processor core, allowing DMA operations to occur while the core is simultaneously exe-cuting its program instructions. DMA transfers can occur between the processor’s internal memory and its serial ports, the SPI-compatible (serial peripheral interface) ports, the IDP (input data port), the parallel data acquisition port (PDAP), or the UART. Thirty-four channels of DMA are available on the processors—16 via the serial ports, eight via the input data port, four for the UARTs, two for the SPI interface, two for the exter-

nal port, and two for memory-to-memory transfers. Programs can be downloaded to the processors using DMA transfers. Other DMA features include interrupt generation upon com-pletion of DMA transfers, and DMA chaining for automatic linked DMA transfers.

Delay Line DMAThe ADSP-21367/ADSP-21368/ADSP-21369 processors pro-vide delay line DMA functionality. This allows processor reads and writes to external delay line buffers (in external memory, SRAM, or SDRAM) with limited core interaction.

Digital Applications and Digital Peripheral Interfaces (DAI/DPI)

The digital applications and digital peripheral interfaces (DAI and DPI) provide the ability to connect various peripherals to any of the DSP’s DAI or DPI pins (DAI_P20–1 and DPI_P14–1).Programs make these connections using the signal routing units (SRU1 and SRU2), shown in Figure 1.The SRUs are matrix routing units (or group of multiplexers) that enable the peripherals provided by the DAI and DPI to be interconnected under software control. This allows easy use of the associated peripherals for a much wider variety of applica-tions by using a larger set of algorithms than is possible with nonconfigurable signal paths.The DAI and DPI also include eight serial ports, an S/PDIF receiver/transmitter, four precision clock generators (PCG), eight channels of synchronous sample rate converters, and an input data port (IDP). The IDP provides an additional input path to the processor core, configurable as either eight channels of I2S serial data or as seven channels plus a single 20-bit wide synchronous parallel data acquisition port. Each data channel has its own DMA channel that is independent from the proces-sor’s serial ports.For complete information on using the DAI and DPI, see the ADSP-21368 SHARC Processor Hardware Reference.

Serial Ports

The processors feature eight synchronous serial ports (SPORTs) that provide an inexpensive interface to a wide variety of digital and mixed-signal peripheral devices such as Analog Devices’ AD183x family of audio codecs, ADCs, and DACs. The serial ports are made up of two data lines, a clock, and frame sync. The data lines can be programmed to either transmit or receive and each data line has a dedicated DMA channel.Serial ports are enabled via 16 programmable and simultaneous receive or transmit pins that support up to 32 transmit or 32 receive channels of audio data when all eight SPORTs are enabled, or eight full duplex TDM streams of 128 channels per frame.The serial ports operate at a maximum data rate of 50 Mbps. Serial port data can be automatically transferred to and from on-chip memory via dedicated DMA channels. Each of the serial ports can work in conjunction with another serial port to


ADSP-21367/ADSP-21368/ADSP-21369

provide TDM support. One SPORT provides two transmit sig-nals while the other SPORT provides the two receive signals. The frame sync and clock are shared.Serial ports operate in five modes:

• Standard DSP serial mode• Multichannel (TDM) mode with support for packed I2S

mode• I2S mode• Packed I2S mode• Left-justified sample pair mode

Left-justified sample pair mode is a mode where in each frame sync cycle two samples of data are transmitted/received—one sample on the high segment of the frame sync, the other on the low segment of the frame sync. Programs have control over var-ious attributes of this mode. Each of the serial ports supports the left-justified sample pair and I2S protocols (I2S is an industry-standard interface com-monly used by audio codecs, ADCs, and DACs such as the Analog Devices AD183x family), with two data pins, allowing four left-justified sample pair or I2S channels (using two stereo devices) per serial port, with a maximum of up to 32 I2S chan-nels. The serial ports permit little-endian or big-endian transmission formats and word lengths selectable from 3 bits to 32 bits. For the left-justified sample pair and I2S modes, data-word lengths are selectable between 8 bits and 32 bits. Serial ports offer selectable synchronization and transmit modes as well as optional μ-law or A-law companding selection on a per channel basis. Serial port clocks and frame syncs can be inter-nally or externally generated.The serial ports also contain frame sync error detection logic where the serial ports detect frame syncs that arrive early (for example, frame syncs that arrive while the transmission/recep-tion of the previous word is occurring). All the serial ports also share one dedicated error interrupt.

S/PDIF-Compatible Digital Audio Receiver/Transmitter and Synchronous/Asynchronous Sample Rate Converter

The S/PDIF receiver/transmitter has no separate DMA chan-nels. It receives audio data in serial format and converts it into a biphase encoded signal. The serial data input to the receiver/transmitter can be formatted as left-justified, I2S, or right-justified with word widths of 16, 18, 20, or 24 bits.The serial data, clock, and frame sync inputs to the S/PDIF receiver/transmitter are routed through the signal routing unit (SRU). They can come from a variety of sources such as the SPORTs, external pins, the precision clock generators (PCGs), or the sample rate converters (SRC) and are controlled by the SRU control registers.The sample rate converter (SRC) contains four SRC blocks and is the same core as that used in the AD1896 192 kHz stereo asynchronous sample rate converter and provides up to 128 dB SNR. The SRC block is used to perform synchronous or asyn-chronous sample rate conversion across independent stereo channels, without using internal processor resources. The four

SRC blocks can also be configured to operate together to con-vert multichannel audio data without phase mismatches. Finally, the SRC can be used to clean up audio data from jittery clock sources such as the S/PDIF receiver.

Digital Peripheral Interface (DPI)

The digital peripheral interface provides connections to two serial peripheral interface ports (SPI), two universal asynchro-nous receiver-transmitters (UARTs), a 2-wire interface (TWI), 12 flags, and three general-purpose timers.

Serial Peripheral (Compatible) Interface

The processors contain two serial peripheral interface ports (SPIs). The SPI is an industry-standard synchronous serial link, enabling the SPI-compatible port to communicate with other SPI-compatible devices. The SPI consists of two data pins, one device select pin, and one clock pin. It is a full-duplex synchro-nous serial interface, supporting both master and slave modes. The SPI port can operate in a multimaster environment by interfacing with up to four other SPI-compatible devices, either acting as a master or slave device. The ADSP-21367/ADSP-21368/ADSP-21369 SPI-compatible peripheral imple-mentation also features programmable baud rate and clock phase and polarities. The SPI-compatible port uses open-drain drivers to support a multimaster configuration and to avoid data contention.

UART Port

The processors provide a full-duplex universal asynchronous receiver/transmitter (UART) port, which is fully compatible with PC-standard UARTs. The UART port provides a simpli-fied UART interface to other peripherals or hosts, supporting full-duplex, DMA-supported, asynchronous transfers of serial data. The UART also has multiprocessor communication capa-bility using 9-bit address detection. This allows it to be used in multidrop networks through the RS-485 data interface standard. The UART port also includes support for five data bits to eight data bits, one stop bit or two stop bits, and none, even, or odd parity. The UART port supports two modes of operation:

• PIO (programmed I/O) – The processor sends or receives data by writing or reading I/O-mapped UART registers. The data is double-buffered on both transmit and receive.

• DMA (direct memory access) – The DMA controller trans-fers both transmit and receive data. This reduces the number and frequency of interrupts required to transfer data to and from memory. The UART has two dedicated DMA channels, one for transmit and one for receive. These DMA channels have lower default priority than most DMA channels because of their relatively low service rates.

The UART port’s baud rate, serial data format, error code gen-eration and status, and interrupts are programmable:

• Supporting bit rates ranging from (fSCLK/1,048,576) to (fSCLK/16) bits per second.

• Supporting data formats from 7 bits to 12 bits per frame.

ADSP-21367/ADSP-21368/ADSP-21369


• Both transmit and receive operations can be configured to generate maskable interrupts to the processor.

Where the 16-bit UART_Divisor comes from the DLH register (most significant eight bits) and DLL register (least significant eight bits).In conjunction with the general-purpose timer functions, auto-baud detection is supported.

Timers

The ADSP-21367/ADSP-21368/ADSP-21369 have a total of four timers: a core timer that can generate periodic software interrupts and three general-purpose timers that can generate periodic interrupts and be independently set to operate in one of three modes:

• Pulse waveform generation mode• Pulse width count/capture mode• External event watchdog mode

The core timer can be configured to use FLAG3 as a timer expired signal, and each general-purpose timer has one bidirec-tional pin and four registers that implement its mode of operation: a 6-bit configuration register, a 32-bit count register, a 32-bit period register, and a 32-bit pulse width register. A sin-gle control and status register enables or disables all three general-purpose timers independently.

2-Wire Interface Port (TWI)

The TWI is a bidirectional 2-wire serial bus used to move 8-bit data while maintaining compliance with the I2C bus protocol. The TWI master incorporates the following features:

• Simultaneous master and slave operation on multiple device systems with support for multimaster data arbitration

• Digital filtering and timed event processing• 7-bit and 10-bit addressing• 100 kbps and 400 kbps data rates• Low interrupt rate

Pulse-Width Modulation

The PWM module is a flexible, programmable, PWM waveform generator that can be programmed to generate the required switching patterns for various applications related to motor and engine control or audio power control. The PWM generator can generate either center-aligned or edge-aligned PWM wave-forms. In addition, it can generate complementary signals on two outputs in paired mode or independent signals in non-paired mode (applicable to a single group of four PWM waveforms). The entire PWM module has four groups of four PWM outputs each. Therefore, this module generates 16 PWM outputs in total. Each PWM group produces two pairs of PWM signals on the four PWM outputs. The PWM generator is capable of operating in two distinct modes while generating center-aligned PWM waveforms: single update mode or double update mode. In single update mode,

the duty cycle values are programmable only once per PWM period. This results in PWM patterns that are symmetrical about the midpoint of the PWM period. In double update mode, a second updating of the PWM registers is implemented at the midpoint of the PWM period. In this mode, it is possible to produce asymmetrical PWM patterns that produce lower harmonic distortion in 3-phase PWM inverters.

ROM-Based Security

The ADSP-21367/ADSP-21368/ADSP-21369 have a ROM secu-rity feature that provides hardware support for securing user software code by preventing unauthorized reading from the internal code when enabled. When using this feature, the pro-cessor does not boot-load any external code, executing exclusively from internal SRAM/ROM. Additionally, the pro-cessor is not freely accessible via the JTAG port. Instead, a unique 64-bit key, which must be scanned in through the JTAG or test access port will be assigned to each customer. The device will ignore a wrong key. Emulation features and external boot modes are only available after the correct key is scanned.

SYSTEM DESIGNThe following sections provide an introduction to system design options and power supply issues.

Program Booting

The internal memory of the processors can be booted up at sys-tem power-up from an 8-bit EPROM via the external port, an SPI master or slave, or an internal boot. Booting is determined by the boot configuration (BOOT_CFG1–0) pins (see Table 7 on Page 15). Selection of the boot source is controlled via the SPI as either a master or slave device, or it can immediately begin executing from ROM.

Power Supplies

The processors have separate power supply connections for the internal (VDDINT), external (VDDEXT), and analog (AVDD/AVSS) power supplies. The internal and analog supplies must meet the 1.3 V requirement for the 400 MHz device and 1.2 V for the 333 MHz and 266 MHz devices. The external supply must meet the 3.3 V requirement. All external supply pins must be con-nected to the same power supply.Note that the analog supply pin (AVDD) powers the processor’s internal clock generator PLL. To produce a stable clock, it is rec-ommended that PCB designs use an external filter circuit for the AVDD pin. Place the filter components as close as possible to the AVDD/AVSS pins. For an example circuit, see Figure 2. (A recom-mended ferrite chip is the muRata BLM18AG102SN1D). To reduce noise coupling, the PCB should use a parallel pair of power and ground planes for VDDINT and GND. Use wide traces to connect the bypass capacitors to the analog power (AVDD) and ground (AVSS) pins. Note that the AVDD and AVSS pins specified in Figure 2 are inputs to the processor and not the analog ground plane on the board—the AVSS pin should connect directly to dig-ital ground (GND) at the chip.


ADSP-21367/ADSP-21368/ADSP-21369

Target Board JTAG Emulator Connector

Analog Devices DSP Tools product line of JTAG emulators uses the IEEE 1149.1 JTAG test access port of the ADSP-21367/ADSP-21368/ADSP-21369 processors to monitor and control the target board processor during emulation. Analog Devices DSP Tools product line of JTAG emulators provides emulation at full processor speed, allowing inspection and modification of memory, registers, and processor stacks. The processor’s JTAG interface ensures that the emulator will not affect target system loading or timing.For complete information on Analog Devices’ SHARC DSP Tools product line of JTAG emulator operation, see the appro-priate “Emulator Hardware User’s Guide.”

DEVELOPMENT TOOLSThe processors are supported with a complete set of CROSS-CORE® software and hardware development tools, including Analog Devices emulators and VisualDSP++® development environment. The same emulator hardware that supports other SHARC processors also fully emulates the ADSP-21367/ADSP-21368/ADSP-21369.The VisualDSP++ project management environment lets pro-grammers develop and debug an application. This environment includes an easy to use assembler (which is based on an alge-braic syntax), an archiver (librarian/library builder), a linker, a loader, a cycle-accurate instruction-level simulator, a C/C++ compiler, and a C/C++ runtime library that includes DSP and mathematical functions. A key point for these tools is C/C++ code efficiency. The compiler has been developed for efficient translation of C/C++ code to DSP assembly. The SHARC has architectural features that improve the efficiency of compiled C/C++ code.The VisualDSP++ debugger has a number of important fea-tures. Data visualization is enhanced by a plotting package that offers a significant level of flexibility. This graphical representa-tion of user data enables the programmer to quickly determine the performance of an algorithm. As algorithms grow in com-plexity, this capability can have increasing significance on the designer’s development schedule, increasing productivity. Sta-tistical profiling enables the programmer to nonintrusively poll the processor as it is running the program. This feature, unique to VisualDSP++, enables the software developer to passively gather important code execution metrics without interrupting the real-time characteristics of the program. Essentially, the

developer can identify bottlenecks in software quickly and effi-ciently. By using the profiler, the programmer can focus on those areas in the program that impact performance and take corrective action.Debugging both C/C++ and assembly programs with the VisualDSP++ debugger, programmers can:

• View mixed C/C++ and assembly code (interleaved source and object information)

• Insert breakpoints• Set conditional breakpoints on registers, memory,

and stacks• Perform linear or statistical profiling of program execution• Fill, dump, and graphically plot the contents of memory• Perform source level debugging• Create custom debugger windows

The VisualDSP++ IDDE lets programmers define and manage DSP software development. Its dialog boxes and property pages let programmers configure and manage all of the SHARC devel-opment tools, including the color syntax highlighting in the VisualDSP++ editor. This capability permits programmers to:

• Control how the development tools process inputs and generate outputs

• Maintain a one-to-one correspondence with the tool’s command line switches

The VisualDSP++ Kernel (VDK) incorporates scheduling and resource management tailored specifically to address the mem-ory and timing constraints of DSP programming. These capabilities enable engineers to develop code more effectively, eliminating the need to start from the very beginning, when developing new application code. The VDK features include threads, critical and unscheduled regions, semaphores, events, and device flags. The VDK also supports priority-based, pre-emptive, cooperative, and time-sliced scheduling approaches. In addition, the VDK was designed to be scalable. If the application does not use a specific feature, the support code for that feature is excluded from the target system.Because the VDK is a library, a developer can decide whether to use it or not. The VDK is integrated into the VisualDSP++ development environment, but can also be used via standard command line tools. When the VDK is used, the development environment assists the developer with many error-prone tasks and assists in managing system resources, automating the gen-eration of various VDK-based objects, and visualizing the system state, when debugging an application that uses the VDK.VisualDSP++ Component Software Engineering (VCSE) is Analog Devices’ technology for creating, using, and reusing software components (independent modules of substantial functionality) to quickly and reliably assemble software applications. The user can download components from the Web, drop them into the application, and publish component archives from within VisualDSP++. VCSE supports component implementation in C/C++ or assembly language.

Figure 2. Analog Power (AVDD) Filter Circuit

HI-Z FERRITEBEAD CHIP

LOCATE ALL COMPONENTSCLOSE TO AVDD AND AVSS PINS

AVDD

AVSS

100nF 10nF 1nFADSP-213xx

VDDINT

ADSP-21367/ADSP-21368/ADSP-21369


Use the Expert Linker to visually manipulate the placement of code and data on the embedded system. View memory utiliza-tion in a color-coded graphical form, easily move code and data to different areas of the processor or external memory with a drag of the mouse and examine runtime stack and heap usage. The expert linker is fully compatible with the existing linker def-inition file (LDF), allowing the developer to move between the graphical and textual environments.In addition to the software and hardware development tools available from Analog Devices, third parties provide a wide range of tools supporting the SHARC processor family. Hard-ware tools include SHARC processor PC plug-in cards. Third-party software tools include DSP libraries, real-time operating systems, and block diagram design tools.

Designing an Emulator-Compatible DSP Board (Target)

The Analog Devices family of emulators are tools that every DSP developer needs to test and debug hardware and software systems. Analog Devices has supplied an IEEE 1149.1 JTAG test access port (TAP) on each JTAG DSP. Nonintrusive in-circuit emulation is assured by the use of the processor’s JTAG inter-face—the emulator does not affect target system loading or timing. The emulator uses the TAP to access the internal fea-tures of the processor, allowing the developer to load code, set breakpoints, observe variables, observe memory, and examine registers. The processor must be halted to send data and com-mands, but once an operation has been completed by the emulator, the DSP system is set running at full speed with no impact on system timing.To use these emulators, the target board must include a header that connects the DSP’s JTAG port to the emulator.For details on target board design issues including mechanical layout, single processor connections, signal buffering, signal ter-mination, and emulator pod logic, see the EE-68: Analog Devices JTAG Emulation Technical Reference on the Analog Devices website (www.analog.com)—use site search on “EE-68.” This document is updated regularly to keep pace with improvements to emulator support.

Evaluation Kit

Analog Devices offers a range of EZ-KIT Lite® evaluation plat-forms to use as a cost-effective method to learn more about developing or prototyping applications with Analog Devices processors, platforms, and software tools. Each EZ-KIT Lite includes an evaluation board along with an evaluation suite of the VisualDSP++ development and debugging environment with the C/C++ compiler, assembler, and linker. Also included are sample application programs, power supply, and a USB cable. All evaluation versions of the software tools are limited for use only with the EZ-KIT Lite product.The USB controller on the EZ-KIT Lite board connects the board to the USB port of the user’s PC, enabling the VisualDSP++ evaluation suite to emulate the on-board proces-sor in-circuit. This permits the customer to download, execute, and debug programs for the EZ-KIT Lite system. It also allows

in-circuit programming of the on-board flash device to store user-specific boot code, enabling the board to run as a stand-alone unit without being connected to the PC.With a full version of VisualDSP++ installed (sold separately), engineers can develop software for the EZ-KIT Lite or any custom-defined system. Connecting one of Analog Devices JTAG emulators to the EZ-KIT Lite board enables high speed, nonintrusive emulation.

ADDITIONAL INFORMATIONThis data sheet provides a general overview of the ADSP-21367/ADSP-21368/ADSP-21369 architecture and func-tionality. For detailed information on the ADSP-2136x family core architecture and instruction set, refer to the ADSP-21368 SHARC Processor Hardware Reference and the ADSP-2136x/ADSP-2137x SHARC Processor Programming Reference.

http://www.analog.com


ADSP-21367/ADSP-21368/ADSP-21369

PIN FUNCTION DESCRIPTIONSThe following symbols appear in the Type column of Table 5: A = asynchronous, G = ground, I = input, O = output, O/T = output three-state, P = power supply, S = synchronous, (A/D) = active drive, (O/D) = open-drain, (pd) = pull-down resistor, (pu) = pull-up resistor.

The ADSP-21367/ADSP-21368/ADSP-21369 SHARC proces-sors use extensive pin multiplexing to achieve a lower pin count. For complete information on the multiplexing scheme, see the ADSP-21368 SHARC Processor Hardware Reference, “System Design” chapter.

Table 5. Pin List

Name Type

State During/ After Reset (ID = 00x) Description

ADDR23–0 O/T (pu)1 Pulled high/driven low

External Address. The processors output addresses for external memory and peripherals on these pins.

DATA31–0 I/O (pu)1 Pulled high/pulled high

External Data. Data pins can be multiplexed to support external memory interface data (I/O), the PDAP (I), FLAGS (I/O), and PWM (O). After reset, all DATA pins are in EMIF mode and FLAG(0-3) pins are in FLAGS mode (default). When configured using the IDP_PDAP_CTL register, IDP Channel 0 scans the DATA31–8 pins for parallel input data.

DAI _P20–1 I/O with programmable pu2

Pulled high/ pulled high

Digital Applications Interface. These pins provide the physical interface to the DAI SRU. The DAI SRU configuration registers define the combination of on-chip audiocentric peripheral inputs or outputs connected to the pin, and to the pin’s output enable. The configuration registers then determines the exact behavior of the pin. Any input or output signal present in the DAI SRU may be routed to any of these pins. The DAI SRU provides the connection from the serial ports (8), the SRC module, the S/PDIF module, input data ports (2), and the precision clock generators (4), to the DAI_P20–1 pins. Pull-ups can be disabled via the DAI_PIN_PULLUP register.

DPI _P14–1 I/O with programmable pu2

Pulled high/ pulled high

Digital Peripheral Interface. These pins provide the physical interface to the DPI SRU. The DPI SRU configuration registers define the combination of on-chip peripheral inputs or outputs connected to the pin and to the pin’s output enable. The configuration registers of these peripherals then determines the exact behavior of the pin. Any input or output signal present in the DPI SRU may be routed to any of these pins. The DPI SRU provides the connection from the timers (3), SPIs (2), UARTs (2), flags (12) TWI (1), and general-purpose I/O (9) to the DPI_P14–1 pins. The TWI output is an open-drain output—so the pins used for I2C data and clock should be connected to logic level 0. Pull-ups can be disabled via the DPI_PIN_PULLUP register.

ACK I (pu)1 Memory Acknowledge. External devices can deassert ACK (low) to add wait states to an external memory access. ACK is used by I/O devices, memory con-trollers, or other peripherals to hold off completion of an external memory access.

RD O/T (pu)1 Pulled high/ driven high

External Port Read Enable. RD is asserted whenever the processors read a word from external memory.

WR O/T (pu)1 Pulled high/ driven high

External Port Write Enable. WR is asserted when the processors write a word to external memory.

SDRAS O/T (pu)1 Pulled high/ driven high

SDRAM Row Address Strobe. Connect to SDRAM’s RAS pin. In conjunction with other SDRAM command pins, defines the operation for the SDRAM to perform.

SDCAS O/T (pu)1 Pulled high/ driven high

SDRAM Column Address Select. Connect to SDRAM’s CAS pin. In conjunction with other SDRAM command pins, defines the operation for the SDRAM to perform.

ADSP-21367/ADSP-21368/ADSP-21369


SDWE O/T (pu)1 Pulled high/ driven high

SDRAM Write Enable. Connect to SDRAM’s WE or W buffer pin.

SDCKE O/T (pu)1 Pulled high/ driven high

SDRAM Clock Enable. Connect to SDRAM’s CKE pin. Enables and disables the CLK signal. For details, see the data sheet supplied with the SDRAM device.

SDA10 O/T (pu)1 Pulled high/ driven low

SDRAM A10 Pin. Enables applications to refresh an SDRAM in parallel with non-SDRAM accesses. This pin replaces the DSP’s A10 pin only during SDRAM accesses.

SDCLK0 O/T High-Z/driving SDRAM Clock Output 0. Clock driver for this pin differs from all other clock drivers. See Figure 38 on Page 46.

SDCLK1 O/T SDRAM Clock Output 1. Additional clock for SDRAM devices. For systems with multiple SDRAM devices, handles the increased clock load requirements, elimi-nating need of off-chip clock buffers. Either SDCLK1 or both SDCLKx pins can be three-stated. Clock driver for this pin differs from all other clock drivers. See Figure 38 on Page 46. The SDCLK1 signal is only available on the SBGA package. SDCLK1 is not available on the LQFP_EP package.

MS0–1 O/T (pu)1 Pulled high/ driven high

Memory Select Lines 0–1. These lines are asserted (low) as chip selects for the corresponding banks of external memory. The MS3-0 lines are decoded memory address lines that change at the same time as the other address lines. When no external memory access is occurring, the MS3-0 lines are inactive; they are active, however, when a conditional memory access instruction is executed, whether or not the condition is true. The MS1 pin can be used in EPORT/FLASH boot mode. See the hardware reference for more information.

FLAG[0]/IRQ0 I/O High-Z/high-Z FLAG0/Interrupt Request 0.

FLAG[1]/IRQ1 I/O High-Z/high-Z FLAG1/Interrupt Request 1.

FLAG[2]/IRQ2/MS2

I/O with programmable pu (for MS mode)

High-Z/high-Z FLAG2/Interrupt Request 2/Memory Select 2.

FLAG[3]/TIMEXP/MS3

I/O with programmable pu (for MS mode)

High-Z/high-Z FLAG3/Timer Expired/Memory Select 3.

TDI I (pu) Test Data Input (JTAG). Provides serial data for the boundary scan logic.

TDO O/T Test Data Output (JTAG). Serial scan output of the boundary scan path.

TMS I (pu) Test Mode Select (JTAG). Used to control the test state machine.

TCK I Test Clock (JTAG). Provides a clock for JTAG boundary scan. TCK must be asserted (pulsed low) after power-up, or held low for proper operation of the processor

TRST I (pu) Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low) after power-up or held low for proper operation of the processor.

EMU O/T (pu) Emulation Status. Must be connected to the ADSP-21367/ADSP-21368/ADSP-21369 Analog Devices DSP Tools product line of JTAG emulator target board connectors only.

Table 5. Pin List

Name Type



ADSP-21367/ADSP-21368/ADSP-21369

CLK_CFG1–0 I Core/CLKIN Ratio Control. These pins set the start-up clock frequency. See Table 8 for a description of the clock configuration modes. Note that the operating frequency can be changed by programming the PLL multiplier and divider in the PMCTL register at any time after the core comes out of reset.

BOOT_CFG1–0 I Boot Configuration Select. These pins select the boot mode for the processor. The BOOT_CFG pins must be valid before reset is asserted. See Table 7 for a description of the boot modes.

RESET I Processor Reset. Resets the processor to a known state. Upon deassertion, there is a 4096 CLKIN cycle latency for the PLL to lock. After this time, the core begins program execution from the hardware reset vector address. The RESET input must be asserted (low) at power-up.

XTAL O Crystal Oscillator Terminal. Used in conjunction with CLKIN to drive an external crystal.

CLKIN I Local Clock In. Used with XTAL. CLKIN is the processor’s clock input. It configures the processors to use either its internal clock generator or an external clock source. Connecting the necessary components to CLKIN and XTAL enables the internal clock generator. Connecting the external clock to CLKIN while leaving XTAL unconnected configures the processor to use an external clock such as an external clock oscillator. CLKIN may not be halted, changed, or operated below the specified frequency.

RESETOUT/CLKOUT

O/T Driven low/driven high

Reset Out/Local Clock Out. Reset out provides a 4096 cycle delay that allows the PLL to lock. This pin can also be configured as a CLKOUT signal to clock synchronous peripherals and memory. The functionality can be switched between the PLL output clock and reset out by setting Bit 12 of the PMCTL register. The default is reset out.

BR4–1 I/O (pu)1 Pulled high/pulled high

External Bus Request. Used by the ADSP-21368 processor to arbitrate for bus mastership. A processor only drives its own BRx line (corresponding to the value of its ID2-0 inputs) and monitors all others. In a system with less than four pro-cessors, the unused BRx pins should be tied high; the processor’s own BRx line must not be tied high or low because it is an output.

ID2–0 I (pd) Processor ID. Determines which bus request (BR4–1) is used by the ADSP-21368 processor. ID = 001 corresponds to BR1, ID = 010 corresponds to BR2, and so on. Use ID = 000 or 001 in single-processor systems. These lines are a system configura-tion selection that should be hardwired or only changed at reset. ID = 101,110, and 111 are reserved.

RPBA I (pu)1 Rotating Priority Bus Arbitration Select. When RPBA is high, rotating priority for the ADSP-21368 external bus arbitration is selected. When RPBA is low, fixed priority is selected. This signal is a system configuration selection which must be set to the same value on every processor in the system.

1 The pull-up is always enabled on the ADSP-21367 and ADSP-21369 processors. The pull-up on the ADSP-21368 processor is only enabled on the processor with ID2–0 = 00x2 Pull-up can be enabled/disabled, value of pull-up cannot be programmed.

Table 5. Pin List

Name Type


ADSP-21367/ADSP-21368/ADSP-21369


DATA MODESThe upper 32 data pins of the external memory interface are muxed (using bits in the SYSCTL register) to support the exter-nal memory interface data (input/output), the PDAP (input only), the FLAGS (input/output), and the PWM channels (out-put). Table 6 provides the pin settings.

BOOT MODES

CORE INSTRUCTION RATE TO CLKIN RATIO MODESFor details on processor timing, see Timing Specifications and Figure 4 on Page 18.

Table 6. Function of Data Pins

Data Pin Mode DATA31–16 DATA15–8 DATA7–0000 EPDATA32–0001 FLAGS/PWM15–01 EPDATA15–0010 FLAGS/PWM15–01 FLAGS15–8 EPDATA7–0011 FLAGS/PWM15–01 FLAGS15–0100 PDAP (DATA + CTRL) EPDATA7–0101 PDAP (DATA + CTRL) FLAGS7–0110 Reserved111 Three-state all pins

1 These signals can be FLAGS or PWM or a mix of both. However, they can be selected only in groups of four. Their function is determined by the control signals FLAGS/PWM_SEL. For more information, see the ADSP-21368 SHARC Processor Hardware Reference.

Table 7. Boot Mode Selection

BOOT_CFG1–0 Booting Mode00 SPI Slave Boot01 SPI Master Boot10 EPROM/FLASH Boot11 Reserved

Table 8. Core Instruction Rate/CLKIN Ratio Selection

CLK_CFG1–0 Core to CLKIN Ratio00 6:101 32:110 16:111 Reserved


ADSP-21367/ADSP-21368/ADSP-21369

SPECIFICATIONSOPERATING CONDITIONS

ELECTRICAL CHARACTERISTICS

Parameter1

1 Specifications subject to change without notice.

Description

400 MHz 350 MHz 333 MHz 266 MHz

Min Max Min Max Min Max Min Max UnitVDDINT Internal (Core) Supply Voltage 1.25 1.35 1.235 1.365 1.14 1.26 1.14 1.26 VAVDD Analog (PLL) Supply Voltage 1.25 1.35 1.235 1.365 1.14 1.26 1.14 1.26 VVDDEXT External (I/O) Supply Voltage 3.13 3.47 3.13 3.47 3.13 3.47 3.13 3.47 VVIH

2

2 Applies to input and bidirectional pins: DATAx, ACK, RPBA, BRx, IDx, FLAGx, DAI_Px, DPI_Px, BOOT_CFGx, CLK_CFGx, RESET, TCK, TMS, TDI, TRST.

High Level Input Voltage @ VDDEXT = Max 2.0 VDDEXT + 0.5 2.0 VDDEXT + 0.5 2.0 VDDEXT + 0.5 2.0 VDDEXT + 0.5 VVIL

2 Low Level Input Voltage @ VDDEXT = Min –0.5 +0.8 –0.5 +0.8 –0.5 +0.8 –0.5 +0.8 VVIH_CLKIN

3

3 Applies to input pin CLKIN.

High Level Input Voltage @ VDDEXT = Max 1.74 VDDEXT + 0.5 1.74 VDDEXT + 0.5 1.74 VDDEXT + 0.5 1.74 VDDEXT + 0.5 VVIL_CLKIN

3 Low Level Input Voltage @ VDDEXT = Min –0.5 +1.1 –0.5 +1.1 –0.5 +1.1 –0.5 +1.1 VTJ Junction Temperature 208-Lead

LQFP_EP @ TAMBIENT 0°C to 70°C N/A N/A 0 110 0 110 0 110 °CTJ Junction Temperature 208-Lead

LQFP_EP @ TAMBIENT –40°C to +85°C N/A N/A N/A N/A –40 +120 –40 +120 °CTJ Junction Temperature 256-Ball BGA_ED

@ TAMBIENT 0°C to 70°C 0 95 N/A N/A 0 105 N/A N/A °CTJ Junction Temperature 256-Ball BGA_ED

@ TAMBIENT –40°C to +85°C N/A N/A N/A N/A 0 105 N/A N/A °C

Parameter Description Test Conditions Min Typ Max UnitVOH

1 High Level Output Voltage @ VDDEXT = Min, IOH = –1.0 mA2 2.4 VVOL

1 Low Level Output Voltage @ VDDEXT = Min, IOL = 1.0 mA2 0.4 VIIH

3, 4 High Level Input Current @ VDDEXT = Max, VIN = VDDEXT Max 10 μAIIL

3, 5, 6 Low Level Input Current @ VDDEXT = Max, VIN = 0 V 10 μAIIHPD

5 High Level Input Current Pull-Down @ VDDEXT = Max, VIN = 0 V 250 μAIILPU

4 Low Level Input Current Pull-Up @ VDDEXT = Max, VIN = 0 V 200 μAIOZH

7, 8 Three-State Leakage Current @ VDDEXT = Max, VIN = VDDEXT Max 10 μAIOZL

7, 9 Three-State Leakage Current @ VDDEXT = Max, VIN = 0 V 10 μAIOZLPU

8 Three-State Leakage Current Pull-Up @ VDDEXT = Max, VIN = 0 V 200 μAIDD-INTYP

10 Supply Current (Internal) tCCLK = 3.75 ns, VDDINT = 1.2 V, 25°CtCCLK = 3.00 ns, VDDINT = 1.2 V, 25°CtCCLK = 2.85 ns, VDDINT = 1.3 V, 25°CtCCLK = 2.50 ns, VDDINT = 1.3 V, 25°C

70090010501100

mAmAmAmA

AIDD11 Supply Current (Analog) AVDD = Max 11 mA

CIN12, 13 Input Capacitance fIN = 1 MHz, TCASE = 25°C, VIN = 1.3 V 4.7 pF

1 Applies to output and bidirectional pins: ADDRx, DATAx, RD, WR, MSx, BRx, FLAGx, DAI_Px, DPI_Px, SDRAS, SDCAS, SDWE, SDCKE, SDA10, SDCLKx, EMU, TDO, CLKOUT.

2 See Output Drive Currents on Page 46 for typical drive current capabilities.3 Applies to input pins without internal pull-ups: BOOT_CFGx, CLK_CFGx, CLKIN, RESET, TCK.4 Applies to input pins with internal pull-ups: ACK, RPBA, TMS, TDI, TRST.5 Applies to input pins with internal pull-downs: IDx.6 Applies to input pins with internal pull-ups disabled: ACK, RPBA.7 Applies to three-statable pins without internal pull-ups: FLAGx, SDCLKx, TDO.8 Applies to three-statable pins with internal pull-ups: ADDRx, DATAx, RD, WR, MSx, BRx, DAI_Px, DPI_Px, SDRAS, SDCAS, SDWE, SDCKE, SDA10, EMU.9 Applies to three-statable pins with internal pull-ups disabled: ADDRx, DATAx, RD, WR, MSx, BRx, DAI_Px, DPI_Px, SDRAS, SDCAS, SDWE, SDCKE, SDA1010See Estimating Power Dissipation for ADSP-21368 SHARC Processors (EE-299) for further information. 11Characterized, but not tested.12Applies to all signal pins.13Guaranteed, but not tested.

ADSP-21367/ADSP-21368/ADSP-21369


PACKAGE INFORMATIONThe information presented in Figure 3 provides details about the package branding for the ADSP-21367/ADSP-21368/ADSP-21369 processors. For a complete listing of product avail-ability, see Ordering Guide on Page 55.

ESD CAUTION

MAXIMUM POWER DISSIPATIONSee Estimating Power Dissipation for ADSP-21368 SHARC Pro-cessors (EE-299) for detailed thermal and power information regarding maximum power dissipation. For information on package thermal specifications, see Thermal Characteristics on Page 48.

ABSOLUTE MAXIMUM RATINGSStresses greater than those listed in Table 10 may cause perma-nent damage to the device. These are stress ratings only; functional operation of the device at these or any other condi-tions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

TIMING SPECIFICATIONSThe processor’s internal clock (a multiple of CLKIN) provides the clock signal for timing internal memory, processor core, and serial ports. During reset, program the ratio between the proces-sor’s internal clock frequency and external (CLKIN) clock frequency with the CLK_CFG1–0 pins (see Table 8 on Page 15). To determine switching frequencies for the serial ports, divide down the internal clock, using the programmable divider con-trol of each port (DIVx for the serial ports).The processor’s internal clock switches at higher frequencies than the system input clock (CLKIN). To generate the internal clock, the processor uses an internal phase-locked loop (PLL). This PLL-based clocking minimizes the skew between the sys-tem clock (CLKIN) signal and the processor’s internal clock.Note the definitions of various clock periods that are a function of CLKIN and the appropriate ratio control shown in Table 11 and Table 12. In Table 11, CCLK is defined as: fCCLK = (2 × PLLM × fINPUT) ÷ (2 × PLLN) where:fCCLK = CCLK frequencyPLLM = Multiplier value programmedPLLN = Divider value programmed

Note the definitions of various clock periods shown in Table 12 which are a function of CLKIN and the appropriate ratio con-trol shown in Table 11.

Figure 3. Typical Package Brand

Table 9. Package Brand Information

Brand Key Field Descriptiont Temperature Rangepp Package TypeZ RoHS Compliant Option cc See Ordering Guidevvvvvv.x Assembly Lot Coden.n Silicon Revision# RoHS Compliant Designationyyww Date Code

vvvvvv.x n.n

tppZ-cc

S

ADSP-2136x

a

#yyww country_of_origin

ESD (electrostatic discharge) sensitive device.Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality.

Table 10. Absolute Maximum Ratings

Parameter RatingInternal (Core) Supply Voltage (VDDINT) –0.3 V to +1.5 VAnalog (PLL) Supply Voltage (AVDD) –0.3 V to +1.5 VExternal (I/O) Supply Voltage (VDDEXT) –0.3 V to +4.6 VInput Voltage –0.5 V to +3.8 VOutput Voltage Swing –0.5 V to VDDEXT + 0.5 VLoad Capacitance 200 pFStorage Temperature Range –65°C to +150°CJunction Temperature Under Bias 125°C

Table 11. ADSP-21368 Clock Generation Operation

Timing Requirements Description CalculationCLKIN Input Clock 1/tCK CCLK Core Clock 1/tCCLK


ADSP-21367/ADSP-21368/ADSP-21369

Figure 4 shows core to CLKIN relationships with external oscil-lator or crystal. The shaded divider/multiplier blocks denote where clock ratios can be set through hardware or software using the power management control register (PMCTL). For more information, see the ADSP-21368 SHARC Processor Hard-ware Reference and Managing the Core PLL on Third-Generation SHARC Processors (EE-290).Use the exact timing information given. Do not attempt to derive parameters from the addition or subtraction of others. While addition or subtraction would yield meaningful results for an individual device, the values given in this data sheet

reflect statistical variations and worst cases. Consequently, it is not meaningful to add parameters to derive longer times. See Figure 39 on Page 46 under Test Conditions for voltage refer-ence levels.Note that in the user application, the PLL multiplier value should be selected in such a way that the VCO frequency never exceeds fVCO specified in Table 14. The VCO frequency is calcu-lated as follows:

fVCO = 2 × PLLM × fINPUT

where:fVCO is the VCO frequencyPLLM is the multiplier value programmedfINPUT is the input frequency to the PLL in MHz.fINPUT = CLKIN when the input divider is disabledfINPUT = CLKIN ÷ 2 when the input divider is enabledSwitching Characteristics specify how the processor changes its signals. Circuitry external to the processor must be designed for compatibility with these signal characteristics. Switching char-acteristics describe what the processor will do in a given circumstance. Use switching characteristics to ensure that any timing requirement of a device connected to the processor (such as memory) is satisfied.Timing Requirements apply to signals that are controlled by cir-cuitry external to the processor, such as the data input for a read operation. Timing requirements guarantee that the processor operates correctly with other devices.

Table 12. Clock Periods

Timing Requirements Description1

tCK CLKIN Clock Period tCCLK (Processor) Core Clock PeriodtPCLK (Peripheral) Clock Period = 2 × tCCLK

tSCLK Serial Port Clock Period = (tCCLK) × SRtSDCLK SDRAM Clock Period = (tCCLK) × SDRtSPICLK SPI Clock Period = (tCCLK) × SPIR

1 where: SR = serial port-to-core clock ratio (wide range, determined by SPORT CLKDIV bits in DIVx register)SPIR = SPI-to-core clock ratio (wide range, determined by SPIBAUD register setting)SPICLK = SPI clockSDR = SDRAM-to-core clock ratio (values determined by Bits 20–18 of the PMCTL register)

Figure 4. Core Clock and System Clock Relationship to CLKIN

LOOPFILTER

CLKIN

PCLK

SDCLK

SDRAMDIVIDER

CLK_CFGx/PMCTL

BY

PA

SS

MU

X

DIVIDEBY 2

PMCTL

CCLKB

YP

AS

SM

UX

PLL

XTAL

CLKINDIVIDER

RESETOUT/CLKOUTRESET

PLLMULTIPLIER

BUF

VCO

BUF

PLLICLK

PMCTL

PLLDIVIDER

CLK_CFGx/PMCTL

PIN

MU

X

RESETOUT

CLKOUT

DELAY OF4096 CLKIN

CYCLES

CORERST

PMCTLCCLK

PCLK

CLK_CFGx/PMCTL

ADSP-21367/ADSP-21368/ADSP-21369


Power-Up Sequencing

The timing requirements for processor start-up are given in Table 13. Note that during power-up, a leakage current of approximately 200μA may be observed on the RESET pin if it is

driven low before power up is complete. This leakage current results from the weak internal pull-up resistor on this pin being enabled during power-up.

Table 13. Power-Up Sequencing Timing Requirements (Processor Start-up)

Parameter Min Max UnitTiming RequirementstRSTVDD RESET Low Before VDDINT/VDDEXT On 0 nstIVDDEVDD VDDINT On Before VDDEXT –50 +200 mstCLKVDD

1 CLKIN Valid After VDDINT/VDDEXT Valid 0 200 mstCLKRST CLKIN Valid Before RESET Deasserted 102 μstPLLRST PLL Control Setup Before RESET Deasserted 20 μsSwitching CharacteristictCORERST Core Reset Deasserted After RESET Deasserted 4096tCK + 2 tCCLK 3, 4

1 Valid VDDINT/VDDEXT assumes that the supplies are fully ramped to their 1.2 V rails and 3.3 V rails. Voltage ramp rates can vary from microseconds to hundreds of milliseconds depending on the design of the power supply subsystem.

2 Assumes a stable CLKIN signal, after meeting worst-case start-up timing of crystal oscillators. Refer to your crystal oscillator manufacturer’s data sheet for start-up time. Assume a 25 ms maximum oscillator start-up time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal.

3 Applies after the power-up sequence is complete. Subsequent resets require RESET to be held low a minimum of four CLKIN cycles in order to properly initialize and propagate default states at all I/O pins.

4 The 4096 cycle count depends on tsrst specification in Table 15. If setup time is not met, 1 additional CLKIN cycle may be added to the core reset time, resulting in 4097 cycles maximum.

Figure 5. Power-Up Sequencing

CLKIN

RESET

tRSTVDD

RESETOUT(MULTIPLEXED WITH CLKOUT)

VDDEXT

VDDINT

tPLLRST

tCLKRST

tCLKVDD

tIVDDEVDD

CLK_CFG1-0

tCORERST


ADSP-21367/ADSP-21368/ADSP-21369

Clock Input

Clock Signals

The processors can use an external clock or a crystal. See the CLKIN pin description in Table 5 on Page 12. Programs can configure the processor to use its internal clock generator by connecting the necessary components to CLKIN and XTAL. Figure 7 shows the component connections used for a crystal operating in fundamental mode.Note that the clock rate is achieved using a 25 MHz crystal and a PLL multiplier ratio 16:1 (CCLK:CLKIN achieves a clock speed of 400 MHz). To achieve the full core clock rate, programs need to configure the multiplier bits in the PMCTL register.

Table 14. Clock Input

Parameter400 MHz1

1 Applies to all 400 MHz models. See Ordering Guide on Page 55.

350 MHz2


333 MHz3


266 MHz4


UnitMin Max Min Max Min Max Min MaxTiming RequirementstCK CLKIN Period 155

5 Applies only for CLK_CFG1–0 = 00 and default values for PLL control bits in PMCTL.

100 17.145 100 185 100 22.55 100 nstCKL CLKIN Width Low 7.51 45 8.51 45 91 45 11.251 45 nstCKH CLKIN Width High 7.51 45 8.51 45 91 45 11.251 45 nstCKRF CLKIN Rise/Fall (0.4 V to 2.0 V) 3 3 3 3 nstCCLK

6

6 Any changes to PLL control bits in the PMCTL register must meet core clock timing specification tCCLK.

CCLK Period 2.55 10 2.855 10 3.05 10 3.755 10 nsfVCO

7

7 See Figure 4 on Page 18 for VCO diagram.

VCO Frequency 100 800 100 800 100 800 100 600 MHztCKJ

8, 9

8 Actual input jitter should be combined with ac specifications for accurate timing analysis.9 Jitter specification is maximum peak-to-peak time interval error (TIE) jitter.

CLKIN Jitter Tolerance –250 +250 –250 +250 –250 +250 –250 +250 ps

Figure 6. Clock Input

CLKIN

tCK

tCKH

tCKL

tCKJ

Figure 7. 400 MHz Operation (Fundamental Mode Crystal)

C122pF Y1

R11M�*

XTALCLKIN

C222pF

25.00 MHz

R247�*

ADSP-2136x

R2 SHOULD BE CHOSEN TO LIMIT CRYSTALDRIVE POWER. REFER TO CRYSTALMANUFACTURER’S SPECIFICATIONS

*TYPICAL VALUES

ADSP-21367/ADSP-21368/ADSP-21369


Reset

Interrupts

The following timing specification applies to the FLAG0, FLAG1, and FLAG2 pins when they are configured as IRQ0, IRQ1, and IRQ2 interrupts.

Table 15. Reset

Parameter Min Max UnitTiming RequirementstWRST

1 RESET Pulse Width Low 4tCK nstSRST RESET Setup Before CLKIN Low 8 ns

1 Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 μs while RESET is low, assuming stable VDD and CLKIN (not including start-up time of external clock oscillator).

Figure 8. Reset

CLKIN

RESET

tWRST tSRST

Table 16. Interrupts

Parameter Min Max UnitTiming RequirementtIPW IRQx Pulse Width 2 × tPCLK +2 ns

Figure 9. Interrupts

DAI_P20-1DPI_14-1FLAG2-0(IRQ2-0) tIPW


ADSP-21367/ADSP-21368/ADSP-21369

Core Timer

The following timing specification applies to FLAG3 when it is configured as the core timer (CTIMER).

Timer PWM_OUT Cycle Timing

The following timing specification applies to Timer0, Timer1, and Timer2 in PWM_OUT (pulse-width modulation) mode. Timer signals are routed to the DPI_P14–1 pins through the DPI SRU. Therefore, the timing specifications provided below are valid at the DPI_P14–1 pins.

Table 17. Core Timer

Parameter Min Max UnitSwitching CharacteristictWCTIM CTIMER Pulse Width 4 × tPCLK – 1 ns

Figure 10. Core Timer

FLAG3(CTIMER)

tWCTIM

Table 18. Timer PWM_OUT Timing

Parameter Min Max UnitSwitching CharacteristictPWMO Timer Pulse Width Output 2 × tPCLK – 1.2 2 × (231 – 1) × tPCLK ns

Figure 11. Timer PWM_OUT Timing

DPI_P14-1(TIMER2-0)

tPWMO

ADSP-21367/ADSP-21368/ADSP-21369


Timer WDTH_CAP Timing

The following specification applies to Timer0, Timer1, and Timer2 in WDTH_CAP (pulse width count and capture) mode. Timer signals are routed to the DPI_P14–1 pins through the DPI SRU. Therefore, the specification provided in Table 19 is valid at the DPI_P14–1 pins.

Pin to Pin Direct Routing (DAI and DPI)

For direct pin connections only (for example, DAI_PB01_I to DAI_PB02_O).

Table 19. Timer Width Capture Timing

Parameter Min Max UnitSwitching CharacteristictPWI Timer Pulse Width 2 × tPCLK 2 × (231 – 1) × tPCLK ns

Figure 12. Timer Width Capture Timing

DPI_P14-1(TIMER2-0)

tPWI

Table 20. DAI Pin to Pin Routing

Parameter Min Max UnitTiming RequirementtDPIO Delay DAI Pin Input Valid to DAI Output Valid 1.5 12 ns

Figure 13. DAI Pin to Pin Direct Routing

DAI_PnDPI_Pn

tDPIO

DAI_PmDPI_Pm


ADSP-21367/ADSP-21368/ADSP-21369

Precision Clock Generator (Direct Pin Routing)

This timing is only valid when the SRU is configured such that the precision clock generator (PCG) takes its inputs directly from the DAI pins (via pin buffers) and sends its outputs directly to the DAI pins. For the other cases, where the PCG’s

inputs and outputs are not directly routed to/from DAI pins (via pin buffers) there is no timing data available. All timing param-eters and switching characteristics apply to external DAI pins (DAI_P01–20).

Table 21. Precision Clock Generator (Direct Pin Routing)

Parameter Min Max UnitTiming RequirementstPCGIP Input Clock Period tCCLK × 8 nstSTRIG PCG Trigger Setup Before Falling

Edge of PCG Input Clock4.5 ns

tHTRIG PCG Trigger Hold After Falling Edge of PCG Input Clock

3 ns

Switching CharacteristicstDPCGIO PCG Output Clock and Frame Sync Active Edge

Delay After PCG Input Clock2.5 10 ns

tDTRIGCLK PCG Output Clock Delay After PCG Trigger 2.5 + (2.5 × tPCGIP) 10 + (2.5 × tPCGIP) nstDTRIGFS PCG Frame Sync Delay After PCG Trigger 2.5 + ((2.5 + D – PH) × tPCGIP) 10 + ((2.5 + D – PH) × tPCGIP) nstPCGOW

1 Output Clock Period 2 × tPCGIP – 1 nsD = FSxDIV, and PH = FSxPHASE. For more information, see the ADSP-2136x SHARC Processor Hardware Reference for the ADSP-21368 Processor, “Precision Clock Generators” chapter.

1 In normal mode.

Figure 14. Precision Clock Generator (Direct Pin Routing)

DAI_PnDPI_Pn

PCG_TRIGx_I

tSTRIG

DAI_PmDPI_Pm

PCG_EXTx_I(CLKIN)

DAI_PyDPI_Py

PCG_CLKx_O

DAI_PzDPI_Pz

PCG_FSx_O

tHTRIG

tDPCGIO

tDTRIGFS

tPCGIP

tPCGOWtDTRIGCLK tDPCGIO

ADSP-21367/ADSP-21368/ADSP-21369


Flags

The timing specifications provided below apply to the FLAG3–0 and DPI_P14–1 pins, and the serial peripheral interface (SPI). See Table 5 on Page 12 for more information on flag use.

Table 22. Flags

Parameter Min Max UnitTiming RequirementtFIPW FLAG3–0 IN Pulse Width 2 × tPCLK + 3 nsSwitching CharacteristictFOPW FLAG3–0 OUT Pulse Width 2 × tPCLK – 1.5 ns

Figure 15. Flags

DPI_P14-1(FLAG3-0IN)

(DATA31-0)tFIPW

DPI_P14-1(FLAG3-0OUT)

(DATA31-0)tFOPW


ADSP-21367/ADSP-21368/ADSP-21369

SDRAM Interface Timing (166 MHz SDCLK)

The 166 MHz access speed is for a single processor. When mul-tiple ADSP-21368 processors are connected in a shared memory system, the access speed is 100 MHz.

The processor needs to be programmed in tSDCLK = 2.5 × tCCLK mode when operated at 350 MHz.

Table 23. SDRAM Interface Timing1

350 MHz All Other Speed Grades UnitParameter Min Max Min Max UnitTiming RequirementstSSDAT DATA Setup Before SDCLK 500 500 pstHSDAT DATA Hold After SDCLK 1.23 1.23 nsSwitching CharacteristicstSDCLK SDCLK Period 7.14 6.0 nstSDCLKH SDCLK Width High 3 2.6 nstSDCLKL SDCLK Width Low 3 2.6 nstDCAD Command, ADDR, Data Delay After SDCLK2 4.8 4.8 nstHCAD Command, ADDR, Data Hold After SDCLK2 1.2 1.2 nstDSDAT Data Disable After SDCLK 5.3 5.3 nstENSDAT Data Enable After SDCLK 1.3 1.3 ns

1 For fCCLK = 400 MHz (SDCLK ratio = 1:2.5).2 Command pins include: SDCAS, SDRAS, SDWE, MSx, SDA10, SDCKE.

Figure 16. SDRAM Interface Timing

tHCAD

tHCAD

tDSDAT

tSSDAT

tDCAD

tENSDAT

tHSDATtSDCLKL

tSDCLKHtSDCLK

SDCLK

DATA (IN)

DATA(OUT)

CMND ADDR(OUT)

tDCAD

ADSP-21367/ADSP-21368/ADSP-21369


SDRAM Interface Enable/Disable Timing (166 MHz SDCLK)

Table 24. SDRAM Interface Enable/Disable Timing1

1 For fCCLK = 400 MHz (SDCLK ratio = 1:2.5).

Parameter Min Max UnitSwitching CharacteristicstDSDC Command Disable After CLKIN Rise 2 × tPCLK + 3 nstENSDC Command Enable After CLKIN Rise 4.0 nstDSDCC SDCLK Disable After CLKIN Rise 8.5 nstENSDCC SDCLK Enable After CLKIN Rise 3.8 nstDSDCA Address Disable After CLKIN Rise 9.2 nstENSDCA Address Enable After CLKIN Rise 2 × tPCLK – 4 4 × tPCLK ns

Figure 17. SDRAM Interface Enable/Disable Timing

CLKIN

COMMANDSDCLKADDR

tDSDC

tDSDCC

tDSDCA

tENSDC

tENSDCACOMMAND

SDCLKADDR

tENSDCC


ADSP-21367/ADSP-21368/ADSP-21369

Memory Read

Use these specifications for asynchronous interfacing to memo-ries. These specifications apply when the processors are the bus master accessing external memory space in asynchronous access mode. Note that timing for ACK, DATA, RD, WR, and strobe timing parameters only apply to asynchronous access mode.

Table 25. Memory Read

Parameter Min Max UnitTiming RequirementstDAD Address, Selects Delay to Data Valid1 W + tSDCLK –5.12 ns tDRLD RD Low to Data Valid W – 3.2 ns tSDS Data Setup to RD High 2.5 ns tHDRH Data Hold from RD High2, 3 0 nstDAAK ACK Delay from Address, Selects1, 4 tSDCLK –9.5 + W ns tDSAK ACK Delay from RD Low4 W – 7.0 ns Switching CharacteristicstDRHA Address Selects Hold After RD High RH + 0.20 ns tDARL Address Selects to RD Low1 tSDCLK – 3.3 nstRW RD Pulse Width W – 1.4 nstRWR RD High to WR, RD Low HI + tSDCLK – 0.8 nsW = (number of wait states specified in AMICTLx register) × tSDCLK.HI =RHC + IC (RHC = number of read hold cycles specified in AMICTLx register) × tSDCLK IC = (number of idle cycles specified in AMICTLx register) × tSDCLK.H = (number of hold cycles specified in AMICTLx register) × tSDCLK.

1 The falling edge of MSx is referenced.2 Note that timing for ACK, DATA, RD, WR, and strobe timing parameters only apply to asynchronous access mode.3 Data hold: User must meet tHDA or tHDRH in asynchronous access mode. See Test Conditions on Page 46 for the calculation of hold times given capacitive and dc loads.4 ACK delay/setup: User must meet tDAAK, or tDSAK, for deassertion of ACK (low). For asynchronous assertion of ACK (high), user must meet tDAAK or tDSAK.

Figure 18. Memory Read

ACK

DATA

tDARL tRW

tDAD

tDAAK

tHDRH

tRWR

tDRLD

tDRHA

tDSAK

tSDS

ADDRESSMSx

RD

WR

ADSP-21367/ADSP-21368/ADSP-21369


Memory Write

Use these specifications for asynchronous interfacing to memo-ries. These specifications apply when the processors are the bus masters, accessing external memory space in asynchronous

access mode. Note that timing for ACK, DATA, RD, WR, and strobe timing parameters only applies to asynchronous access mode.

Table 26. Memory Write

Parameter Min Max UnitTiming RequirementstDAAK ACK Delay from Address, Selects1, 2 tSDCLK – 9.7 + W ns tDSAK ACK Delay from WR Low 1, 3 W – 4.9 ns Switching CharacteristicstDAWH Address, Selects to WR Deasserted2 tSDCLK – 3.1+ W ns tDAWL Address, Selects to WR Low2 tSDCLK – 2.7 ns tWW WR Pulse Width W – 1.3 ns tDDWH Data Setup Before WR High tSDCLK – 3.0+ W ns tDWHA Address Hold After WR Deasserted H + 0.15 ns tDWHD Data Hold After WR Deasserted H + 0.02 ns tWWR WR High to WR, RD Low tSDCLK – 1.5+ H ns tDDWR Data Disable Before RD Low 2tSDCLK – 4.11 nstWDE WR Low to Data Enabled tSDCLK – 3.5 nsW = (number of wait states specified in AMICTLx register) × tSDCLK.H = (number of hold cycles specified in AMICTLx register) × tSDCLK.

1 ACK delay/setup: System must meet tDAAK, or tDSAK, for deassertion of ACK (low). For asynchronous assertion of ACK (high), user must meet tDAAK or tDSAK.2 The falling edge of MSx is referenced.3 Note that timing for ACK, DATA, RD, WR, and strobe timing parameters only applies to asynchronous access mode.

Figure 19. Memory Write

ACK

DATA

tDAWL tWW

tDAAK

tWWRtWDE

tDDWR

tDWHAtDAWH

tDSAK

tDDWH

tDWHD

ADDRESSMSx

WR

RD


ADSP-21367/ADSP-21368/ADSP-21369

Asynchronous Memory Interface (AMI) Enable/Disable

Use these specifications for passing bus mastership between ADSP-21368 processors (BRx).

Table 27. AMI Enable/Disable

Parameter Min Max UnitSwitching CharacteristicstENAMIAC Address/Control Enable After Clock Rise 4 ns tENAMID Data Enable After Clock Rise tSDCLK + 4 ns tDISAMIAC Address/Control Disable After Clock Rise 8.7 ns tDISAMID Data Disable After Clock Rise 0 ns

Figure 20. AMI Enable/Disable

CLKIN

ADDR, WR, RD,MS1-0, DATA

tDISAMIAC

tDISAMID

tENAMIAC

tENAMID

ADDR, WR, RD,MS1-0, DATA

ADSP-21367/ADSP-21368/ADSP-21369


Shared Memory Bus Request

Use these specifications for passing bus mastership between ADSP-21368 processors (BRx).

Table 28. Multiprocessor Bus Request

Parameter Min Max UnitTiming RequirementstSBRI BRx, Setup Before CLKIN High 9 ns tHBRI BRx, Hold After CLKIN High 0.5 ns Switching CharacteristicstDBRO BRx Delay After CLKIN High 9 ns tHBRO BRx Hold After CLKIN High 1.0 ns

Figure 21. Shared Memory Bus Request

tHBRItSBRI

CLKIN

tDBRO

tHBRO

BRX (OUT)

BRX (IN)


ADSP-21367/ADSP-21368/ADSP-21369

Serial Ports

To determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay and frame sync setup and hold, 2) data delay and data setup and hold, and 3) SCLK width.

Serial port signals SCLK, frame sync (FS), data channel A, data channel B are routed to the DAI_P20–1 pins using the SRU. Therefore, the timing specifications provided below are valid at the DAI_P20–1 pins.

Table 29. Serial Ports—External Clock

400 MHz 333 MHz 266 MHzParameter Min Max Min Max Min Max UnitTiming RequirementstSFSE

1 FS Setup Before SCLK (Externally Generated FS in Either Transmit or Receive Mode)

2.5 2.5 2.5 ns

tHFSE1 FS Hold After SCLK

(Externally Generated FS in Either Transmit or Receive Mode)

2.5 2.5 2.5 ns

tSDRE1 Receive Data Setup Before Receive

SCLK1.9 2.0 2.5 ns

tHDRE1 Receive Data Hold After SCLK 2.5 2.5 2.5 ns

tSCLKW SCLK Width (tCCLK × 8) ÷ 2 – 0.5 (tCCLK × 8) ÷ 2 – 0.5 (tCCLK × 8) ÷ 2 – 0.5 ns tSCLK SCLK Period tCCLK × 8 tCCLK × 8 tCCLK × 8 nsSwitching CharacteristicstDFSE

2 FS Delay After SCLK (Internally Generated FS in Either Transmit or Receive Mode)

10.25 10.25 10.25 ns

tHOFSE2 FS Hold After SCLK

(Internally Generated FS in Either Transmit or Receive Mode)

2 2 2 ns

tDDTE2 Transmit Data Delay After Transmit

SCLK7.8 9.6 9.8 ns

tHDTE2 Transmit Data Hold After Transmit

SCLK2 2 2 ns

1 Referenced to sample edge.2 Referenced to drive edge.

ADSP-21367/ADSP-21368/ADSP-21369


Table 30. Serial Ports—Internal Clock

Parameter Min Max UnitTiming RequirementstSFSI

1 FS Setup Before SCLK (Externally Generated FS in Either Transmit or Receive Mode)

7 ns

tHFSI1 FS Hold After SCLK

(Externally Generated FS in Either Transmit or Receive Mode)2.5 ns

tSDRI1 Receive Data Setup Before SCLK 7 ns

tHDRI1 Receive Data Hold After SCLK 2.5 ns

Switching CharacteristicstDFSI

2 FS Delay After SCLK (Internally Generated FS in Transmit Mode) 4 ns tHOFSI

2 FS Hold After SCLK (Internally Generated FS in Transmit Mode) –1.0 nstDFSIR

2 FS Delay After SCLK (Internally Generated FS in Receive Mode) 9.75 nstHOFSIR

2 FS Hold After SCLK (Internally Generated FS in Receive Mode) –1.0 nstDDTI

2 Transmit Data Delay After SCLK 3.25 ns tHDTI

2 Transmit Data Hold After SCLK –1.0 ns tSCLKIW

3 Transmit or Receive SCLK Width 2 × tPCLK – 1.5 2 × tPCLK + 1.5 ns1 Referenced to the sample edge.2 Referenced to drive edge.3 Minimum SPORT divisor register value.

Table 31. Serial Ports—Enable and Three-State

Parameter Min Max UnitSwitching CharacteristicstDDTEN

1 Data Enable from External Transmit SCLK 2 ns tDDTTE

1 Data Disable from External Transmit SCLK 10 ns tDDTIN

1 Data Enable from Internal Transmit SCLK –1 ns 1 Referenced to drive edge.

Table 32. Serial Ports—External Late Frame Sync

Parameter Min Max UnitSwitching CharacteristicstDDTLFSE

1 Data Delay from Late External Transmit FS or External Receive FS with MCE = 1, MFD = 0

7.75 ns

tDDTENFS1 Data Enable for MCE = 1, MFD = 0 0.5 ns

1 The tDDTLFSE and tDDTENFS parameters apply to left-justified sample pair as well as DSP serial mode, and MCE = 1, MFD = 0.


ADSP-21367/ADSP-21368/ADSP-21369

Figure 22. External Late Frame Sync1

1 This figure reflects changes made to support left-justified sample pair mode.

DRIVE SAMPLE DRIVE

DAI_P20-1(SCLK)

DAI_P20-1(FS)

DAI_P20-1(DATA CHANNEL A/B)

DRIVE SAMPLE DRIVE

LATE EXTERNAL TRANSMIT FS

EXTERNAL RECEIVE FS WITH MCE = 1, MFD = 0

1ST BIT 2ND BIT

DAI_P20-1(SCLK)

DAI_P20-1(FS)

1ST BIT 2ND BIT

tHFSE/ItSFSE/I

tDDTE/ItDDTENFS

tDDTLFSE

tHDTE/I

tSFSE/I

tDDTE/ItDDTENFS

tDDTLFSE

tHDTE/I


NOTE: SERIAL PORT SIGNALS (SCLK, FS, DATA CHANNEL A/B) ARE ROUTED TO THE DAI_P20-1 PINSUSING THE SRU. THE TIMING SPECIFICATIONS PROVIDED HERE ARE VALID AT THE DAI_P20-1 PINS.

tHFSE/I

ADSP-21367/ADSP-21368/ADSP-21369


Figure 23. Serial Ports

DAI_P20-1(SCLK)

DAI_P20-1(FS)

DRIVE EDGE SAMPLE EDGE

DATA RECEIVE—INTERNAL CLOCK DATA RECEIVE—EXTERNAL CLOCK


NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL), SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE.

tSDRI tHDRI

tSFSItHFSI

tDFSIR

tHOFSIR

tSCLKIW

tSDREtHDRE

tSFSEtHFSE

tDFSE

tSCLKW

tHOFSE


tDDTI


DATA TRANSMIT—INTERNAL CLOCK

tSFSItHFSI

tDFSI

tHOFSI

tSCLKIW

tHDTI

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL), SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE.

tDDTE


DATA TRANSMIT—EXTERNAL CLOCK

tSFSE tHFSE

tDFSE

tHOFSE

tSCLKW

tHDTE

DAI_P20-1(SCLK)

DAI_P20-1(FS)


DAI_P20-1(SCLK)

DAI_P20-1(FS)


DAI_P20-1(SCLK)

DAI_P20-1(FS)


DRIVE EDGE

DAI_P20-1SCLK (INT)

DRIVE EDGE DRIVE EDGE

SCLKDAI_P20-1SCLK (EXT)

tDDTTEtDDTEN

tDDTIN




ADSP-21367/ADSP-21368/ADSP-21369

Input Data Port

The timing requirements for the IDP are given in Table 33. IDP signals SCLK, frame sync (FS), and SDATA are routed to the DAI_P20–1 pins using the SRU. Therefore, the timing specifica-tions provided below are valid at the DAI_P20–1 pins.

Table 33. IDP

Parameter Min Max UnitTiming RequirementstSISFS

1 FS Setup Before SCLK Rising Edge 4 ns tSIHFS

1 FS Hold After SCLK Rising Edge 2.5 ns tSISD

1 SDATA Setup Before SCLK Rising Edge 2.5 ns tSIHD

1 SDATA Hold After SCLK Rising Edge 2.5 ns tIDPCLKW Clock Width (tCCLK × 8) ÷ 2 – 1 ns tIDPCLK Clock Period tCCLK × 8 ns

1 DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins.

Figure 24. IDP Master Timing

DAI_P20-1(SCLK)

DAI_P20-1(FS)

SAMPLE EDGE

tSISFS tSIHFS

tIDPCLK

DAI_P20-1(SDATA)

tIDPCLKW

tSISD tSIHD

ADSP-21367/ADSP-21368/ADSP-21369


Parallel Data Acquisition Port (PDAP)

The timing requirements for the PDAP are provided in Table 34. PDAP is the parallel mode operation of Channel 0 of the IDP. For details on the operation of the IDP, see the IDP chapter of the ADSP-21368 SHARC Processor Hardware

Reference. Note that the most significant 16 bits of external PDAP data can be provided through the DATA31–16 pins. The remaining four bits can only be sourced through DAI_P4–1. The timing below is valid at the DATA31–16 pins.

Table 34. Parallel Data Acquisition Port (PDAP)

Parameter Min Max UnitTiming RequirementstSPCLKEN

1 PDAP_CLKEN Setup Before PDAP_CLK Sample Edge 2.5 nstHPCLKEN

1 PDAP_CLKEN Hold After PDAP_CLK Sample Edge 2.5 ns tPDSD

1 PDAP_DAT Setup Before SCLK PDAP_CLK Sample Edge 3.85 ns tPDHD

1 PDAP_DAT Hold After SCLK PDAP_CLK Sample Edge 2.5 ns tPDCLKW Clock Width (tCCLK × 8) ÷ 2 – 3 ns tPDCLK Clock Period tCCLK × 8 ns Switching CharacteristicstPDHLDD Delay of PDAP Strobe After Last PDAP_CLK Capture Edge for a Word 2 × tPCLK + 3 ns tPDSTRB PDAP Strobe Pulse Width 2 × tPCLK – 1 ns

1 Source pins of DATA are ADDR7–0, DATA7–0, or DAI pins. Source pins for SCLK and FS are: 1) DAI pins, 2) CLKIN through PCG, or 3) DAI pins through PCG.

Figure 25. PDAP Timing

DAI_P20-1(PDAP_CLK)

SAMPLE EDGE

tPDSD tPDHD

tSPCLKEN tHPCLKEN

tPDCLKW

DATA

DAI_P20-1(PDAP_CLKEN)

tPDSTRB

tPDHLDD

DAI_P20-1(PDAP_STROBE)

tPDCLK


ADSP-21367/ADSP-21368/ADSP-21369

Pulse-Width Modulation Generators

Sample Rate Converter—Serial Input Port

The SRC input signals SCLK, frame sync (FS), and SDATA are routed from the DAI_P20–1 pins using the SRU. Therefore, the timing specifications provided in Table 36 are valid at the DAI_P20–1 pins.

Table 35. PWM Timing

Parameter Min Max UnitSwitching CharacteristicstPWMW PWM Output Pulse Width tPCLK – 2 (216 – 2) × tPCLK – 2 nstPWMP PWM Output Period 2 × tPCLK – 1.5 (216 – 1) × tPCLK – 1.5 ns

Figure 26. PWM Timing

PWMOUTPUTS

tPWMW

tPWMP

Table 36. SRC, Serial Input Port

Parameter Min Max UnitTiming RequirementstSRCSFS

1 FS Setup Before SCLK Rising Edge 4 ns tSRCHFS

1 FS Hold After SCLK Rising Edge 5.5 ns tSRCSD

1 SDATA Setup Before SCLK Rising Edge 4 ns tSRCHD

1 SDATA Hold After SCLK Rising Edge 5.5 ns tSRCCLKW Clock Width (tCCLK × 8) ÷ 2 – 1 ns tSRCCLK Clock Period tCCLK × 8 ns

1 DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins.

Figure 27. SRC Serial Input Port Timing

DAI_P20-1(SCLK)

DAI_P20-1(FS)

SAMPLE EDGE

tSRCSFS tSRCHFS

tSRCCLK

DAI_P20-1(SDATA)

tSRCCLKW

tSRCSD tSRCHD

ADSP-21367/ADSP-21368/ADSP-21369


Sample Rate Converter—Serial Output Port

For the serial output port, the frame-sync is an input and it should meet setup and hold times with regard to SCLK on the output port. The serial data output, SDATA, has a hold time

and delay specification with regard to SCLK. Note that SCLK rising edge is the sampling edge and the falling edge is the drive edge.

Table 37. SRC, Serial Output Port

Parameter Min Max UnitTiming RequirementstSRCSFS

1 FS Setup Before SCLK Rising Edge 4 ns tSRCHFS

1 FS Hold After SCLK Rising Edge 5.5 ns tSRCCLKW Clock Width (tCCLK × 8) ÷ 2 – 1 ns tSRCCLK Clock Period tCCLK × 8 ns Switching CharacteristicstSRCTDD

1 Transmit Data Delay After SCLK Falling Edge 9.9 ns tSRCTDH

1 Transmit Data Hold After SCLK Falling Edge 1 ns 1 DATA, SCLK, and FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins.

Figure 28. SRC Serial Output Port Timing

DAI_P20-1(SCLK)

DAI_P20-1(FS)

tSRCSFS tSRCHFS

DAI_P20-1(SDATA)

tSRCTDD

tSRCTDH

SAMPLE EDGEtSRCCLK

tSRCCLKW


ADSP-21367/ADSP-21368/ADSP-21369

S/PDIF Transmitter

Serial data input to the S/PDIF transmitter can be formatted as left justified, I2S, or right justified with word widths of 16, 18, 20, or 24 bits. The following sections provide timing for the transmitter.

S/PDIF Transmitter—Serial Input WaveformsFigure 29 shows the right-justified mode. LRCLK is high for the left channel and low for the right channel. Data is valid on the rising edge of SCLK. The MSB is delayed 12-bit clock periods (in 20-bit output mode) or 16-bit clock periods (in 16-bit output mode) from an LRCLK transition, so that when there are 64 SCLK periods per LRCLK period, the LSB of the data is right-justified to the next LRCLK transition.

Figure 30 shows the default I2S-justified mode. LRCLK is low for the left channel and high for the right channel. Data is valid on the rising edge of SCLK. The MSB is left-justified to an LRCLK transition but with a single SCLK period delay.

Figure 31 shows the left-justified mode. LRCLK is high for the left channel and low for the right channel. Data is valid on the rising edge of SCLK. The MSB is left-justified to an LRCLK transition with no MSB delay.

Figure 29. Right-Justified Mode

DAI_P20-1LRCLK

DAI_P20-1SCLK

DAI_P20-1SDATA

LEFT CHANNEL RIGHT CHANNEL

MSB-1 MSB-2 LSB+2 LSB+1 LSB MSB MSB-1 MSB-2 LSB+2 LSB+1 LSBLSB MSB

Figure 30. I2S-Justified Mode

MSB-1 MSB-2 LSB+2 LSB+1 LSB

LEFT CHANNEL

RIGHT CHANNEL

MSB MSB-1 MSB-2 LSB+2 LSB+1 LSB MSBMSB

DAI_P20-1LRCLK

DAI_P20-1SCLK

DAI_P20-1SDATA

Figure 31. Left-Justified Mode

LEFT CHANNEL RIGHT CHANNEL

MSB-1 MSB-2 LSB+2 LSB+1 LSB MSB MSB-1 MSB-2 LSB+2 LSB+1 LSB MSB MSB+1MSB

DAI_P20-1LRCLK

DAI_P20-1SCLK

DAI_P20-1SDATA

ADSP-21367/ADSP-21368/ADSP-21369


S/PDIF Transmitter Input Data TimingThe timing requirements for the input port are given in Table 38. Input signals SCLK, frame sync (FS), and SDATA are routed to the DAI_P20–1 pins using the SRU. Therefore, the timing specifications provided below are valid at the DAI_P20–1 pins.

Oversampling Clock (TxCLK) Switching CharacteristicsThe S/PDIF transmitter has an oversampling clock. This TxCLK input is divided down to generate the biphase clock.

Table 38. S/PDIF Transmitter Input Data Timing

Parameter Min Max UnitTiming RequirementstSISFS

1 FS Setup Before SCLK Rising Edge 3 ns tSIHFS

1 FS Hold After SCLK Rising Edge 3 ns tSISD

1 SData Setup Before SCLK Rising Edge 3 ns tSIHD

1 SData Hold After SCLK Rising Edge 3 ns tSISCLKW Clock Width 36 ns tSISCLK Clock Period 80 ns tSITXCLKW Transmit Clock Width 9 ns tSITXCLK Transmit Clock Period 20 ns

1 DATA, SCLK, and FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins.

Figure 32. S/PDIF Transmitter Input Timing

DAI_P20-1(SCLK)

DAI_P20-1(FS)

SAMPLE EDGE

tSISD

tSISFS

tSISCLKW

DAI_P20-1(SDATA)

DAI_P20-1(TXCLK)

tSIHD

tSIHFS

tSITXCLKW tSITXCLK

Table 39. Oversampling Clock (TxCLK) Switching Characteristics

Parameter Min Max UnitTxCLK Frequency for TxCLK = 384 × FS 73.8 MHzTxCLK Frequency for TxCLK = 256 × FS 49.2 MHzFrame Rate 192.0 kHz


ADSP-21367/ADSP-21368/ADSP-21369

S/PDIF Receiver

The following section describes timing as it relates to the S/PDIF receiver.

Internal Digital PLL ModeIn the internal digital phase-locked loop mode the internal PLL (digital PLL) generates the 512 × FS clock.

Table 40. S/PDIF Receiver Internal Digital PLL Mode Timing

Parameter Min Max UnitSwitching CharacteristicstDFSI LRCLK Delay After SCLK 5 nstHOFSI LRCLK Hold After SCLK –2 nstDDTI Transmit Data Delay After SCLK 5 nstHDTI Transmit Data Hold After SCLK –2 nstSCLKIW

1 Transmit SCLK Width 40 ns1 SCLK frequency is 64 × FS where FS = the frequency of LRCLK.

Figure 33. S/PDIF Receiver Internal Digital PLL Mode Timing


DAI_P20-1(SCLK)

DAI_P20-1(FS)


tSCLKIW

tDFSI

tDDTI

tHOFSI

tHDTI

ADSP-21367/ADSP-21368/ADSP-21369


SPI Interface—Master

The processors contain two SPI ports. The primary has dedi-cated pins and the secondary is available through the DPI. The timing provided in Table 41 and Table 42 on Page 44 applies to both.

Table 41. SPI Interface Protocol—Master Switching and Timing Specifications

Parameter Min Max UnitTiming RequirementstSSPIDM Data Input Valid to SPICLK Edge (Data Input Setup Time) 8.2 nstHSPIDM SPICLK Last Sampling Edge to Data Input Not Valid 2 nsSwitching CharacteristicstSPICLKM Serial Clock Cycle 8 × tPCLK – 2 nstSPICHM Serial Clock High Period 4 × tPCLK – 2 nstSPICLM Serial Clock Low Period 4 × tPCLK – 2 nstDDSPIDM SPICLK Edge to Data Out Valid (Data Out Delay Time) 2.5 nstHDSPIDM SPICLK Edge to Data Out Not Valid (Data Out Hold Time) 4 × tPCLK – 2 nstSDSCIM FLAG3–0IN (SPI Device Select) Low to First SPICLK Edge 4 × tPCLK – 2 nstHDSM Last SPICLK Edge to FLAG3–0IN High 4 × tPCLK – 2 nstSPITDM Sequential Transfer Delay 4 × tPCLK – 1 ns

Figure 34. SPI Master Timing

LSBVALID

MSBVALID

tSSPIDMtHSPIDM

tHDSPIDM

LSBMSB

tHSPIDM

tDDSPIDM

MOSI(OUTPUT)

MISO(INPUT)

FLAG3-0(OUTPUT)

SPICLK(CP = 0)

(OUTPUT)

SPICLK(CP = 1)

(OUTPUT)

tHDSPIDM

LSBVALID

LSBMSB

MSBVALID

tHSPIDM

tDDSPIDM

MOSI(OUTPUT)

MISO(INPUT)

tSSPIDM

CPHASE = 1

CPHASE = 0

tSPICHM tSPICLM

tSPICLM

tSPICLKM

tSPICHM

tHDSM tSPITDMtSDSCIM

tSSPIDM


ADSP-21367/ADSP-21368/ADSP-21369

SPI Interface—Slave

Table 42. SPI Interface Protocol—Slave Switching and Timing Specifications

Parameter Min Max UnitTiming RequirementstSPICLKS Serial Clock Cycle 4 × tPCLK – 2 nstSPICHS Serial Clock High Period 2 × tPCLK – 2 nstSPICLS Serial Clock Low Period 2 × tPCLK – 2 nstSDSCO SPIDS Assertion to First SPICLK Edge, CPHASE = 0 or CPHASE = 1 2 × tPCLK nstHDS Last SPICLK Edge to SPIDS Not Asserted, CPHASE = 0 2 × tPCLK nstSSPIDS Data Input Valid to SPICLK Edge (Data Input Setup Time) 2 nstHSPIDS SPICLK Last Sampling Edge to Data Input Not Valid 2 nstSDPPW SPIDS Deassertion Pulse Width (CPHASE = 0) 2 × tPCLK nsSwitching CharacteristicstDSOE SPIDS Assertion to Data Out Active 0 6.8 nstDSOE

1 SPIDS Assertion to Data Out Active (SPI2) 0 8 nstDSDHI SPIDS Deassertion to Data High Impedance 0 6.8 nstDSDHI

1 SPIDS Deassertion to Data High Impedance (SPI2) 0 8.6 nstDDSPIDS SPICLK Edge to Data Out Valid (Data Out Delay Time) 9.5 nstHDSPIDS SPICLK Edge to Data Out Not Valid (Data Out Hold Time) 2 × tPCLK nstDSOV SPIDS Assertion to Data Out Valid (CPHASE = 0) 5 × tPCLK ns

1 The timing for these parameters applies when the SPI is routed through the signal routing unit. For more information, see the ADSP-21368 SHARC Processor Hardware Reference, “Serial Peripheral Interface Port” chapter.

Figure 35. SPI Slave Timing

tHSPID S

tD DSPIDS

tDSD HI

LSBMSB

MSB VALID

tDSOEtDDSPIDS

tHD SPID S

MISO(OUTPUT)

MOSI(INPUT)

tSSPIDS

SPIDS(INPUT)

SPICLK(CP = 0)(INPUT)

SPICLK(CP = 1)(INPUT)

tSDSC O

tSPICHS tSPICLS

tSPICL S

tSPICLKS

tHDS

tSPICHS

tSSPIDStH SPID S

tDSDHI

LSB VALID

MSB

MSB VALID

tDSOEtDDSPIDS

MISO(OUTPUT)

MOSI(INPUT)

tSSPIDS

LSB VALID

LSB

CPHASE = 1

CPHASE = 0

tSDPPW

tDSOV tHD SPID S

ADSP-21367/ADSP-21368/ADSP-21369


JTAG Test Access Port and Emulation

Table 43. JTAG Test Access Port and Emulation

Parameter Min Max UnitTiming RequirementstTCK TCK Period tCK nstSTAP TDI, TMS Setup Before TCK High 5 nstHTAP TDI, TMS Hold After TCK High 6 nstSSYS

1 System Inputs Setup Before TCK High 7 nstHSYS

1 System Inputs Hold After TCK High 18 nstTRSTW TRST Pulse Width 4tCK nsSwitching CharacteristicstDTDO TDO Delay from TCK Low 7 nstDSYS

2 System Outputs Delay After TCK Low tCK ÷ 2 + 7 ns1 System Inputs = AD15–0, SPIDS, CLK_CFG1–0, RESET, BOOT_CFG1–0, MISO, MOSI, SPICLK, DAI_Px, FLAG3–0.2 System Outputs = MISO, MOSI, SPICLK, DAI_Px, AD15–0, RD, WR, FLAG3–0, CLKOUT, EMU.

Figure 36. IEEE 1149.1 JTAG Test Access Port

TCK

TMSTDI

TDO

SYSTEMINPUTS

SYSTEMOUTPUTS

tSTAP

tTCK

tHTAP

tDTDO

tSSYS tHSYS

tDSYS


ADSP-21367/ADSP-21368/ADSP-21369

OUTPUT DRIVE CURRENTSFigure 37 shows typical I-V characteristics for the output driv-ers and Figure 38 shows typical I-V characteristics for the SDCLK output drivers. The curves represent the current drive capability of the output drivers as a function of output voltage.

TEST CONDITIONSThe ac signal specifications (timing parameters) appear in Table 15 on Page 21 through Table 43 on Page 45. These include output disable time, output enable time, and capacitive loading. The timing specifications for the SHARC apply for the voltage reference levels in Figure 39. Timing is measured on signals when they cross the 1.5 V level as described in Figure 39. All delays (in nanoseconds) are mea-sured between the point that the first signal reaches 1.5 V and the point that the second signal reaches 1.5 V.

CAPACITIVE LOADINGOutput delays and holds are based on standard capacitive loads of an average of 6 pF on all pins (see Figure 40). Figure 45 and Figure 46 show graphically how output delays and holds vary with load capacitance. The graphs of Figure 41 through Figure 46 may not be linear outside the ranges shown for Typi-cal Output Delay vs. Load Capacitance and Typical Output Rise Time (20% to 80%, V = Min) vs. Load Capacitance.

Figure 37. Typical Drive at Junction Temperature

Figure 38. SDCLK1–0 Drive at Junction Temperature

SWEEP (VDDEXT) VOLTAGE (V)

-20

0 3.50.5 1.0 1.5 2.0 2.5 3.0

0

-40

-30

20

40

-10

SO

UR

CE

(VD

DE

XT)

CU

RR

EN

T(m

A)

VOL

3.11V, 125°C

3.3V, 25°C

3.47V, -45°C

VOH30

10

3.11V, 125°C

3.3V, 25°C

3.47V, -45°C

3.11V, 105°C

3.11V, 105°C

-60

0 3.50.5 1.0 1.5 2.0 2.5 3.0

0

-45

-30

60

75

-15

SO

UR

CE

(VD

DE

XT)

CU

RR

EN

T(m

A)

VOL

3 .13V, 125°C

3.3V, 25°C

3 .47V, -45°C

VOH

3.13V, 105°C

45

-90

-75

-105

30

15

3.13V, 125°C

3.3V, 25°C

3 .47V, -45°C

3 .13V, 105°C

SWEEP (VD DEXT) VOLTAGE (V)

Figure 39. Voltage Reference Levels for AC Measurements

Figure 40. Equivalent Device Loading for AC Measurements (Includes All Fixtures)

INPUTOR

OUTPUT1.5V 1.5V

T1

ZO = 50 (impedance)TD = 4.04 1.18 ns

2pF

TESTER PIN ELECTRONICS

50

0.5pF

70

400

45

4pF

NOTES:THE WORST CASE TRANSMISSION LINE DELAY IS SHOWN AND CAN BE USEDFOR THE OUTPUT TIMING ANALYSIS TO REFELECT THE TRANSMISSION LINEEFFECT AND MUST BE CONSIDERED. THE TRANSMISSION LINE (TD), IS FOR LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS.

ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING FOR A GIVEN SYSTEM REQUIREMENT. IF NECESSARY, A SYSTEM MAY INCORPORATE EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES.

1.5VDUT

OUTPUT

ADSP-21367/ADSP-21368/ADSP-21369


Figure 41. Typical Output Rise/Fall Time (20% to 80%, VDDEXT = Min)

Figure 42. Typical Output Rise/Fall Time (20% to 80%, VDDEXT = Max)

LOAD CAPACITANCE (pF)

12

0 50 100 150 200 250

10

8

6

4

RIS

EA

ND

FA

LL

TIM

ES

(ns)

2

0

RISE

FALLy = 0.049x + 1.5105

y = 0.0482x + 1.4604


8

00 100 250

12

4

2

10

6

RIS

EA

ND

FA

LL

TIM

ES

(ns)

20015050

FALL

y = 0.0467x + 1.6323

y = 0.045x + 1.524

RISE

Figure 43. SDCLK Typical Output Rise/Fall Time (20% to 80%, VDDEXT = Min)

Figure 44. SDCLK Typical Output Rise/Fall Time (20% to 80%, VDDEXT = Max)


0 50 100 150 200 250

10

8

6

4

RIS

EA

ND

FA

LL

TIM

ES

(ns)

2

0

RISE

FALL

y = 0.0372x + 0.228

y = 0.0277x + 0.369


0 50 100 150 200 250

10

8

6

4

RIS

EA

ND

FALL

TIM

ES

(ns)

2

0

RISE

FALL

y = 0.0364x + 0.197

y = 0.0259x + 0.311


ADSP-21367/ADSP-21368/ADSP-21369

THERMAL CHARACTERISTICSThe ADSP-21367/ADSP-21368/ADSP-21369 processors are rated for performance over the temperature range specified in Operating Conditions on Page 16.Table 44 and Table 45 airflow measurements comply with JEDEC standards JESD51-2 and JESD51-6 and the junction-to-board measurement complies with JESD51-8. Test board design complies with JEDEC standards JESD51-9 (BGA_ED) and JESD51-8 (LQFP_EP). The junction-to-case measurement com-plies with MIL-STD-883. All measurements use a 2S2P JEDEC test board.The LQFP-EP package requires thermal trace squares and ther-mal vias, to an embedded ground plane, in the PCB. Refer to JEDEC standard JESD51-5 for more information.

To determine the junction temperature of the device while on the application PCB, use:

where:TJ = junction temperature (°C)TTOP = case temperature (°C) measured at the top center of the packageΨJT = junction-to-top (of package) characterization parameter is the typical value from Table 44 and Table 45.PD = power dissipation (see EE Note EE-299)Values of θJA are provided for package comparison and PCB design considerations. θJA can be used for a first-order approxi-mation of TJ by the equation:

where:TA = ambient temperature (°C)Values of θJC are provided for package comparison and PCB design considerations when an external heat sink is required. This is only applicable when a heat sink is used.Values of θJB are provided for package comparison and PCB design considerations. The thermal characteristics values pro-vided in Table 44 and Table 45 are modeled values @ 2 W.

Figure 45. Typical Output Delay or Hold vs. Load Capacitance (at Junction Temperature)

Figure 46. SDCLK Typical Output Delay or Hold vs. Load Capacitance (at Junction Temperature)


0 20050 100 150

10

8

OU

TPU

TD

EL

AY

OR

HO

LD(n

s)

-4

6

0

4

2

-2

y = 0.0488x - 1.5923


6

-20 100

2

0

8

4

RIS

EA

ND

FA

LL

TIM

ES

(ns)

20015050

y = 0.0256x - 0.021

Table 44. Thermal Characteristics for 256-Ball BGA_ED

Parameter Condition Typical UnitθJA Airflow = 0 m/s 12.5 °C/WθJMA Airflow = 1 m/s 10.6 °C/WθJMA Airflow = 2 m/s 9.9 °C/WθJC 0.7 °C/WθJB 5.3 °C/WΨJT Airflow = 0 m/s 0.3 °C/WΨJMT Airflow = 1 m/s 0.3 °C/WΨJMT Airflow = 2 m/s 0.3 °C/W

Table 45. Thermal Characteristics for 208-Lead LQFP EPAD (With Exposed Pad Soldered to PCB)

Parameter Condition Typical UnitθJA Airflow = 0 m/s 17.1 °C/WθJMA Airflow = 1 m/s 14.7 °C/WθJMA Airflow = 2 m/s 14.0 °C/WθJC 9.6 °C/WΨJT Airflow = 0 m/s 0.23 °C/WΨJMT Airflow = 1 m/s 0.39 °C/WΨJMT Airflow = 2 m/s 0.45 °C/WΨJB Airflow = 0 m/s 11.5 °C/WΨJMB Airflow = 1 m/s 11.2 °C/WΨJMB Airflow = 2 m/s 11.0 °C/W

TJ TTOP ΨJT PD×( )+=

TJ TA θJA PD×( )+=

ADSP-21367/ADSP-21368/ADSP-21369


256-BALL BGA_ED PINOUTTable 46. 256-Ball BGA_ED Pin Assignment (Numerically by Ball Number)

Ball No. Signal Ball No. Signal Ball No. Signal Ball No. SignalA01 NC B01 DAI5 C01 DAI9 D01 DAI10A02 TDI B02 SDCLK11 C02 DAI7 D02 DAI6A03 TMS B03 TRST C03 GND D03 GNDA04 CLK_CFG0 B04 TCK C04 VDDEXT D04 VDDEXT

A05 CLK_CFG1 B05 BOOT_CFG0 C05 GND D05 GNDA06 EMU B06 BOOT_CFG1 C06 GND D06 VDDEXT

A07 DAI4 B07 TDO C07 VDDINT D07 VDDINT

A08 DAI1 B08 DAI3 C08 GND D08 GNDA09 DPI14 B09 DAI2 C09 GND D09 VDDEXT

A10 DPI12 B10 DPI13 C10 VDDINT D10 VDDINT

A11 DPI10 B11 DPI11 C11 GND D11 GNDA12 DPI9 B12 DPI8 C12 GND D12 VDDEXT

A13 DPI7 B13 DPI5 C13 VDDINT D13 VDDINT

A14 DPI6 B14 DPI4 C14 GND D14 GNDA15 DPI3 B15 DPI1 C15 GND D15 VDDEXT

A16 DPI2 B16 RESET C16 VDDINT D16 GNDA17 RESETOUT/CLKOUT B17 DATA30 C17 VDDINT D17 VDDEXT

A18 DATA31 B18 DATA29 C18 VDDINT D18 GNDA19 NC B19 DATA28 C19 DATA27 D19 DATA26A20 NC B20 NC C20 NC/RPBA2 D20 DATA24E01 DAI11 F01 DAI14 G01 DAI15 H01 DAI17E02 DAI8 F02 DAI12 G02 DAI13 H02 DAI16E03 VDDINT F03 GND G03 GND H03 VDDINT

E04 VDDINT F04 GND G04 VDDEXT H04 VDDINT

E17 GND F17 VDDEXT G17 VDDINT H17 VDDEXT

E18 GND F18 GND G18 VDDINT H18 GNDE19 DATA25 F19 GND/ID22 G19 DATA22 H19 DATA19E20 DATA23 F20 DATA21 G20 DATA20 H20 DATA18J01 DAI19 K01 FLAG0 L01 FLAG2 M01 ACKJ02 DAI18 K02 DAI20 L02 FLAG1 M02 FLAG3J03 GND K03 GND L03 VDDINT M03 GNDJ04 GND K04 VDDEXT L04 VDDINT M04 GND


ADSP-21367/ADSP-21368/ADSP-21369

J17 GND K17 VDDINT L17 VDDINT M17 VDDEXT

J18 GND K18 VDDINT L18 VDDINT M18 GNDJ19 GND/ID12 K19 GND/ID02 L19 DATA15 M19 DATA12J20 DATA17 K20 DATA16 L20 DATA14 M20 DATA13N01 RD P01 SDA10 R01 SDWE T01 SDCKEN02 SDCLK0 P02 WR R02 SDRAS T02 SDCASN03 GND P03 VDDINT R03 GND T03 GNDN04 VDDEXT P04 VDDINT R04 GND T04 VDDEXT

N17 GND P17 VDDINT R17 VDDEXT T17 GNDN18 GND P18 VDDINT R18 GND T18 GNDN19 DATA11 P19 DATA8 R19 DATA6 T19 DATA5N20 DATA10 P20 DATA9 R20 DATA7 T20 DATA4U01 MS0 V01 ADDR22 W01 GND Y01 GNDU02 MS1 V02 ADDR23 W02 ADDR21 Y02 NCU03 VDDINT V03 VDDINT W03 ADDR19 Y03 NCU04 GND V04 GND W04 ADDR20 Y04 ADDR18U05 VDDEXT V05 GND W05 ADDR17 Y05 NC/BR12

U06 GND V06 GND W06 ADDR16 Y06 NC/BR22

U07 VDDEXT V07 GND W07 ADDR15 Y07 XTALU08 VDDINT V08 VDDINT W08 ADDR14 Y08 CLKINU09 VDDEXT V09 GND W09 AVDD Y09 NCU10 GND V10 GND W10 AVSS Y10 NCU11 VDDEXT V11 GND W11 ADDR13 Y11 NC/BR32

U12 VDDINT V12 VDDINT W12 ADDR12 Y12 NC/BR42

U13 VDDEXT V13 VDDEXT W13 ADDR10 Y13 ADDR11U14 VDDEXT V14 GND W14 ADDR8 Y14 ADDR9U15 VDDINT V15 VDDINT W15 ADDR5 Y15 ADDR7U16 VDDEXT V16 GND W16 ADDR4 Y16 ADDR6U17 VDDINT V17 GND W17 ADDR1 Y17 ADDR3U18 VDDINT V18 GND W18 ADDR2 Y18 GNDU19 DATA0 V19 DATA1 W19 ADDR0 Y19 GNDU20 DATA2 V20 DATA3 W20 NC Y20 NC

1 The SDCLK1 signal is only available on the SBGA package. SDCLK1 is not available on the LQFP_EP package.2 Applies to ADSP-21368 models only.

Table 46. 256-Ball BGA_ED Pin Assignment (Numerically by Ball Number) (Continued)

Ball No. Signal Ball No. Signal Ball No. Signal Ball No. Signal

ADSP-21367/ADSP-21368/ADSP-21369


Figure 47 shows the bottom view of the BGA_ED ball configu-ration. Figure 48 shows the top view of the BGA_ED ball configuration.

Figure 47. 256-Ball BGA_ED Ball Configuration (Bottom View)

12

34

56

78

910

111214

15 1316

171920 18

RPNMLKJHGFEDCBA

YWVUT

NO CONNECT

VDDINT

I/O SIGNALS GND

KEY

VDDEXTAVSSAVDD

BOTTOMVIEW

Figure 48. 256-Ball BGA_ED Ball Configuration (Top View)

12

34

56

78

910

1112 14

151316

17 192018

RPNMLK

JHGFEDC

B

A

YWVUT

NO CONNECT

VDDINT

I/O SIGNALS GND

KEY

VDDEXTAVSSAVDD

TOPVIEW


ADSP-21367/ADSP-21368/ADSP-21369

208-LEAD LQFP_EP PINOUTTable 47. 208-Lead LQFP_EP Pin Assignment (Numerically by Lead Number)

Lead No. Signal Lead No. Signal Lead No. Signal Lead No. Signal Lead No. Signal1 VDDINT 43 VDDINT 85 VDDEXT 127 VDDINT 169 CLK_CFG02 DATA28 44 DATA4 86 GND 128 GND 170 BOOT_CFG03 DATA27 45 DATA5 87 VDDINT 129 VDDEXT 171 CLK_CFG14 GND 46 DATA2 88 ADDR14 130 DAI19 172 EMU5 VDDEXT 47 DATA3 89 GND 131 DAI18 173 BOOT_CFG16 DATA26 48 DATA0 90 VDDEXT 132 DAI17 174 TDO7 DATA25 49 DATA1 91 ADDR15 133 DAI16 175 DAI48 DATA24 50 VDDEXT 92 ADDR16 134 DAI15 176 DAI29 DATA23 51 GND 93 ADDR17 135 DAI14 177 DAI310 GND 52 VDDINT 94 ADDR18 136 DAI13 178 DAI111 VDDINT 53 VDDINT 95 GND 137 DAI12 179 VDDEXT

12 DATA22 54 GND 96 VDDEXT 138 VDDINT 180 GND13 DATA21 55 VDDEXT 97 ADDR19 139 VDDEXT 181 VDDINT

14 DATA20 56 ADDR0 98 ADDR20 140 GND 182 GND15 VDDEXT 57 ADDR2 99 ADDR21 141 VDDINT 183 DPI1416 GND 58 ADDR1 100 ADDR23 142 GND 184 DPI1317 DATA19 59 ADDR4 101 ADDR22 143 DAI11 185 DPI1218 DATA18 60 ADDR3 102 MS1 144 DAI10 186 DPI1119 VDDINT 61 ADDR5 103 MS0 145 DAI8 187 DPI1020 GND 62 GND 104 VDDINT 146 DAI9 188 DPI921 DATA17 63 VDDINT 105 VDDINT 147 DAI6 189 DPI822 VDDINT 64 GND 106 GND 148 DAI7 190 DPI723 GND 65 VDDEXT 107 VDDEXT 149 DAI5 191 VDDEXT

24 VDDINT 66 ADDR6 108 SDCAS 150 VDDEXT 192 GND25 GND 67 ADDR7 109 SDRAS 151 GND 193 VDDINT

26 DATA16 68 ADDR8 110 SDCKE 152 VDDINT 194 GND27 DATA15 69 ADDR9 111 SDWE 153 GND 195 DPI628 DATA14 70 ADDR10 112 WR 154 VDDINT 196 DPI529 DATA13 71 GND 113 SDA10 155 GND 197 DPI430 DATA12 72 VDDINT 114 GND 156 VDDINT 198 DPI331 VDDEXT 73 GND 115 VDDEXT 157 VDDINT 199 DPI132 GND 74 VDDEXT 116 SDCLK0 158 VDDINT 200 DPI233 VDDINT 75 ADDR11 117 GND 159 GND 201 RESETOUT/CLKOUT34 GND 76 ADDR12 118 VDDINT 160 VDDINT 202 RESET35 DATA11 77 ADDR13 119 RD 161 VDDINT 203 VDDEXT

36 DATA10 78 GND 120 ACK 162 VDDINT 204 GND37 DATA9 79 VDDINT 121 FLAG3 163 TDI 205 DATA3038 DATA8 80 AVSS 122 FLAG2 164 TRST 206 DATA3139 DATA7 81 AVDD 123 FLAG1 165 TCK 207 DATA2940 DATA6 82 GND 124 FLAG0 166 GND 208 VDDINT

41 VDDEXT 83 CLKIN 125 DAI20 167 VDDINT

42 GND 84 XTAL 126 GND 168 TMS

ADSP-21367/ADSP-21368/ADSP-21369


PACKAGE DIMENSIONSThe ADSP-21367/ADSP-21368/ADSP-21369 processors are available in 256-ball RoHS compliant and leaded BGA_ED, and 208-lead RoHS compliant LQFP_EP packages.

Figure 49. 208-Lead Low Profile Quad Flat Package, Exposed Pad [LQFP_EP](SW-208-1)

Dimensions shown in millimeters

COMPLIANT TO JEDEC STANDARDS MS-026-BJB-HD

0.150.100.05 0.08

COPLANARITY

0.200.150.09

1.451.401.35

7°3.5°0°

VIEW AROTATED 90° CCW

0.270.220.17

0.750.600.45

0.50BSC

LEAD PITCH

28.1028.00 SQ27.90

30.2030.00 SQ29.80

TOP VIEW(PINS DOWN)

BOTTOM VIEW(PINS UP)

EXPOSEDPAD

1

5253

5253

105104

105104

156

208

1

208157

156

157

PIN 1

1.60 MAX

1.00 REF

SEATINGPLANE

VIEW A

8.890REF

8.712REF

25.50REF

NOTE:THE EXPOSED PAD IS REQUIRED TO BE ELECTRICALLY AND THERMALLY CONNECTED TO VSS.THIS SHOULD BE IMPLEMENTED BY SOLDERING THE EXPOSED PAD TO A VSS PCB LAND THAT IS THE SAME SIZEAS THE EXPOSED PAD. THE VSS PCB LAND SHOULD BE ROBUSTLY CONNECTED TO THE VSS PLANE IN THE PCBWITH AN ARRAY OF THERMAL VIAS FOR BEST PERFORMANCE.


ADSP-21367/ADSP-21368/ADSP-21369

SURFACE-MOUNT DESIGNTable 48 is provided as an aide to PCB design. For industry-standard design recommendations, refer to IPC-7351, Generic Requirements for Surface-Mount Design and Land Pattern Standard.

Figure 50. 256-Ball Ball Grid Array, Thermally Enhanced [BGA_ED](BP-256)

Dimension shown in millimeters

1.27NOM 1.70 MAX

0.900.750.60

BALLDIAMETER

0.700.600.50

1.000.800.60

0.10MIN

SEATINGPLANE

0.20COPLANARITY

0.25 MIN 4�

TOP VIEW

A1 BALLINDICATOR

COMPLIES WITH JEDEC STANDARD MO-192-BAL-2.

12

34

56

78

910

111214

15 1316

171920 18

RPNMLKJHGFEDCBA

YWVUT

BOTTOMVIEW

27.00BSC SQ

24.13REF SQ

A1 CORNERINDEX AREA

DETAIL A

DETAIL A

Table 48. BGA_ED Data for Use with Surface-Mount Design

Package Ball Attach Type Solder Mask Opening Ball Pad Size256-Lead Ball Grid Array BGA_ED (BP-256)

Solder Mask Defined (SMD) 0.63 mm 0.73 mm

ADSP-21367/ADSP-21368/ADSP-21369


AUTOMOTIVE PRODUCTSAn ADSP-21369 model is available for automotive applications with controlled manufacturing. Note that this special model may have specifications that differ from the general release models.

The automotive grade product shown in Table 49 is available for use in automotive applications. Contact your local ADI account representative or authorized ADI product distributor for specific product ordering information. Note that all automo-tive products are RoHS compliant.

ORDERING GUIDE

Table 49. Automotive Products

Model Temperature Range1Instruction Rate

On-Chip SRAM ROM Package Description

Package Option

AD21369WBSWZ1xx –40°C to +85°C 266 MHz 2M bit 6M bit 208-Lead LQFP_EP SW-208-11 Referenced temperature is ambient temperature.

Model Temperature Range1

1 Referenced temperature is ambient temperature.

Instruction Rate

On-Chip SRAM ROM Package Description

Package Option

ADSP-21367KBP-2A2

2 Available with a wide variety of audio algorithm combinations sold as part of a chipset and bundled with necessary software. For a complete list, visit our website at www.analog.com/SHARC.

0°C to +70°C 333 MHz 2M bit 6M bit 256-Ball BGA_ED BP-256

ADSP-21367KBPZ-2A2, 3

3 Z = RoHS Compliant Part.

0°C to +70°C 333 MHz 2M bit 6M bit 256-Ball BGA_ED BP-256

ADSP-21367BBP-2A2 –40°C to +85°C 333 MHz 2M bit 6M bit 256-Ball BGA_ED BP-256

ADSP-21367BBPZ-2A2, 3 –40°C to +85°C 333 MHz 2M bit 6M bit 256-Ball BGA_ED BP-256

ADSP-21367KBPZ-3A2, 3 0°C to +70°C 400 MHz 2M bit 6M bit 256-Ball BGA_ED BP-256

ADSP-21367KSWZ-1A2, 3 0°C to +70°C 266 MHz 2M bit 6M bit 208-Lead LQFP_EP SW-208-1



ADSP-21367BSWZ-1A2, 3 –40°C to +85°C 266 MHz 2M bit 6M bit 208-Lead LQFP_EP SW-208-1

ADSP-21368KBP-2A 0°C to +70°C 333 MHz 2M bit 6M bit 256-Ball BGA_ED BP-256

ADSP-21368KBPZ-2A3 0°C to +70°C 333 MHz 2M bit 6M bit 256-Ball BGA_ED BP-256

ADSP-21368BBP-2A –40°C to +85°C 333 MHz 2M bit 6M bit 256-Ball BGA_ED BP-256

ADSP-21368BBPZ-2A3 –40°C to +85°C 333 MHz 2M bit 6M bit 256-Ball BGA_ED BP-256


ADSP-21369KBP-2A 0°C to +70°C 333 MHz 2M bit 6M bit 256-Ball BGA_ED BP-256


ADSP-21369BBP-2A –40°C to +85°C 333 MHz 2M bit 6M bit 256-Ball BGA_ED BP-256

ADSP-21369BBPZ-2A2 –40°C to +85°C 333 MHz 2M bit 6M bit 256-Ball BGA_ED BP-256


ADSP-21369KSWZ-1A3 0°C to +70°C 266 MHz 2M bit 6M bit 208-Lead LQFP_EP SW-208-1



ADSP-21369BSWZ-1A3 –40°C to +85°C 266 MHz 2M bit 6M bit 208-Lead LQFP_EP SW-208-1


ADSP-21367/ADSP-21368/ADSP-21369

©2008 Analog Devices, Inc. All rights reserved. Trademarks andregistered trademarks are the property of their respective owners.

D05267-0-11/08(D)

SHARC Processors ADSP-21367/ADSP-21368/ADSP-21369€¦ · pm data bus dm data bus pm address bus 32 dm address bus 64 processing px register element (pey) timer instruction cache

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