SFF SDR DP - MBDK tutorial

SFF SDR development platformModel-based design tutorial

Version 3.1—May 2010

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Revision history

Version Date Modifications

1.0 2008-05-01 First edition.

1.1 2008-06-01 Corrections of erroneous information and instructions.

2.0 2009-04-14 Updated to account for releases 3.0.0 and 3.1.0 of the ADP software tools. First official release.

3.0 2009-09-08 Updated to account for release 3.2.0 of the ADP software tools.

3.1 2010-05-12 Updated to account for release 4.1.1 of the ADP software tools.

© Lyrtech Inc. All rights reserved.

No part of this document may be reproduced or used in any form or by any means—graphical, electronic, or mechanical (which includes photocopying, recording, taping, and information storage/retrieval systems)—without the express written permission of Lyrtech Inc.

To ensure the accuracy of the information contained herein, particular attention was given to usage in preparing this document. It corresponds to the product version manufactured prior to the date appearing on the title page. There may be differences between the document and the product, if the product was modified after the production of the document.

Lyrtech Inc. reserves itself the right to make changes and improvements to the product described in this document at any time and without notice.

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Trademarks

Acrobat, Adobe, and Reader are either registered trademarks or trademarks of Adobe Systems Incorporated in the United States and/or other countries. IBM is a registered trademark of International Business Machines Corporation in the United States, other countries, or both. Intel and Pentium are registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. Microsoft, MS-DOS, Windows, Windows NT, and the Windows logo are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. MATLAB, Simulink, and Real-Time Workshop are registered trademarks of The MathWorks, Inc. Xilinx, Spartan, and Virtex are registered trademarks of Xilinx, Inc. Texas Instruments, Code Composer Studio, C62x, C64x, and C67x are trademarks of Texas Instruments Incorporated. All other product names are trademarks or registered trademarks of their respective holders.

The TM and ® marks have been omitted from the text.

Warning

Do not use Lyrtech products in conjunction with life-monitoring or life-critical equipment. Failure to observe this warning relieves Lyrtech of any and all responsibility.

FCC warning

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Table of contentsIntroduction.......................................................................................................................................... 1

Purpose and structure ...................................................................................................................... 1

Conventions ................................................................................................................................. 1

Glossary of terms ......................................................................................................................... 2

Technical support ............................................................................................................................. 3

Requirements ....................................................................................................................................... 5

Software requirements .................................................................................................................... 5

General ........................................................................................................................................ 5

DSP development software .......................................................................................................... 5

FPGA development software ....................................................................................................... 5

Preliminary readings ........................................................................................................................ 5

Accessing the platform’s documentation ..................................................................................... 6

Using the platform’s DSP ...................................................................................................................... 7

Targeting the DSP ............................................................................................................................. 7

Tutorial 1—Audio loopback simulation ............................................................................................ 7

Goals ............................................................................................................................................ 7

Creating a new model .................................................................................................................. 7

Simulating the model ................................................................................................................... 10

Running the model on your platform .......................................................................................... 11

Tutorial 2—Processing an audio signal with a FIR filter ................................................................... 16

Goals ............................................................................................................................................ 16

Modifying an existing model ........................................................................................................ 16

Running the model on your platform .......................................................................................... 17

Using the platform’s FPGA .................................................................................................................... 19

Targeting the FPGA ........................................................................................................................... 19

Tutorial 3—Incorporating an FPGA in a Simulink simulation ........................................................... 19

Goals ............................................................................................................................................ 19


Configuring the simulation parameters ....................................................................................... 23

Saving the model ......................................................................................................................... 23

Running the model ...................................................................................................................... 23

Observing the results ................................................................................................................... 24

Stopping and disconnecting ......................................................................................................... 24

Using the platform’s mixed processor architecture .............................................................................. 25

Tutorial 4—Using VPSS for streaming application in the FPGA model ............................................. 25

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Goals ............................................................................................................................................ 25


Saving the model ......................................................................................................................... 27

Building an FPGA model ............................................................................................................... 27


Tutorial 5—Using the VPSS to stream data in a DSP model ............................................................. 28

Goals ............................................................................................................................................ 28


Running the model on the platform ............................................................................................ 30

Using the data conversion and RF modules ......................................................................................... 33

Tutorial 6—Using the DAC in an FPGA model .................................................................................. 33

Goals ............................................................................................................................................ 33


Building the FPGA model ............................................................................................................. 36


Saving the model ......................................................................................................................... 36

Tutorial 7—Using the data conversion and RF modules in a DSP model.......................................... 36

Goals ............................................................................................................................................ 36


Building the model ....................................................................................................................... 38

Connecting to the target and running the model ........................................................................ 38


Stopping and disconnecting ......................................................................................................... 39

1

Introduction

IntroductionThis document goes over one of the applicative examples supplied with the SFF SDR development platforms. The document treats of DSP designs and FPGA designs and, once your are done, you will be able to perform a narrow-band FM transmission to the FRS handset supplied with the low-band platform.

Purpose and structureThis step-by-step approach can prove useful in mastering the intricacies of model-based design with your platform. The guide includes of number of specific elements that you should understand prior to reading it, as they will help you understand the way the information is organized.

ConventionsIn a procedure containing several steps, the operations that you must perform are numbered (1, 2, 3…). The diamond (◊) is used to indicate single-step procedures. Lowercase letters (a, b, c…) are be used to indicate secondary steps in a complex procedure.

Capitals are used to identify keys on the keyboard (for example, CTRL+V). All software user interface words (for example, names of menus, commands, dialog boxes, text boxes, and options) appear in bold font style (for example, File).

The abbreviation N/A is used to indicate something that is not applicable or not available at the time of press. The abbreviation NC is used to indicate no connection.

This symbol is used to call your attention to important information, crucial to the correct operation of your product.

This symbol is used to call your attention to information that may prove useful in operating your product, but is not vital to correct operation.

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Introduction

Glossary of termsThroughout this document, you will find references to the following terms. Refer to the following table as to their definitions.

Glossary of termsTable 1

Term Definition

Application programming interface (API) An application programming interface is the interface that a computer system, library, or application provides to allow requests for services to be made of it by other computer programs or to allow data to be exchanged between them.

Base design Empty design or template that is incapable of data processing and is not instantiated in the custom logic of the board’s FPGA.

Board software development kit Abbreviated BSDK, this kit gives users the possibility to quickly become fully functional developing C/C++ or assembly code for the DSP, and HDL code for the FPGA through an understanding of all Lyrtech boards’ major interfaces.

Chassis Refers to the rigid framework onto which the CPU board, Lyrtech development platforms, and other equipment are mounted. It also supports the shell-like case—the housing that protects all the vital internal equipment from dust, moisture, and tampering.

Computer communication development Refers to developing custom communications applications to communicate with Lyrtech boards.

cPCI Short for CompactPCI, refers to a 3U or 6U Eurocard-based industrial computer where the all boards are connected through a passive PCI backplane.

cPCI chassis system Refers to the chassis-CPU board-case system.

cPCI CPU Host CPU of the cPCI chassis system, responsible for processing and communications between the hardware in the cPCI chassis and the remote computer connected to the cPCI chassis system.

Default design Design loaded by default on Lyrtech boards used for FPGA design.

Digital signal processing Digital signal processing is the study of signals in a digital representation and the processing methods of these signals. The algorithms required for DSP are sometimes performed using specialized devices that use specialized microprocessors called digital signal processors (DSP).

Digital signal processor (DSP) A digital signal processor is a specialized microprocessor designed specifically for digital signal processing, generally in real time.

Example Refers to examples used to demonstrate functions or applications supplied with the board software development kit. For this reason, examples come in two flavors: application examples and functional examples.

Eurocard Refers to a European standard format for printed-circuit boards that can be connected together in a standardized subrack.

HDL Stands for hardware description language.

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Introduction

Term Definition

Host A host is defined as the device that configures and controls a Lyrtech board. The host may be a standard computer or the CPU board of the cPCI chassis system where the Lyrtech board is installed. You can develop applications on the host for Lyrtech boards through the use of an application programming interface (API) that comprises protocols and functions necessary to build software applications. These API are supplied with the Lyrtech board.

Model-based design Refers to all the Lyrtech board-specific tools and software used for development with the boards in MATLAB and Simulink and the Lyrtech model-based design kit(s).

Reception Any data received by the referent is a reception. Abbreviated RX.

Reference design Blueprint of an FPGA system implanted on Lyrtech boards. It is intended for others to copy and contains the essential elements of a working system (in other words, it is capable of data processing), but third parties may enhance or modify the design as necessary.

Software development Refers to development performed with and for the board with a software development kit. Software development for a board comes in three flavors: host software development, DSP software development, and FPGA software development.

Transmission Any data transmitted by the referent is a transmission. Abbreviated TX.

VHDL Stands for VHSIC hardware description language.

VHSIC Stands for very-high-speed integrated circuit.

Technical supportLyrtech is firmly committed to providing the highest level of customer service and product support. If you experience any difficulties using our products or if it fails to operate as described, first refer to the documentation accompanying the product. If you find yourself still in need of assistance visit the technical support page in the Support section of our Web site at www.lyrtech.com.

http://www.lyrtech.com

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Introduction

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Requirements

RequirementsBefore you can use your SFF SDR development platform in developing model-based designs, you must meet the requirements outlined below.

For details about the exact software versions supported by your SFF SDR development platform, refer to your platform’s quick start guide.

Software requirementsTo complete all the tutorials in this guide, the following software must be installed on your computer:

GeneralAdvanced development platform (ADP) software tools• MATLAB• Simulink• Signal Processing Blockset• Signal Processing Toolbox•

You should be familiar with MATLAB and Simulink before proceeding.

DSP development softwareCode Composer Studio• Real-Time Workshop•

FPGA development softwareSystem Generator for DSP• ISE Foundation•

Preliminary readingsBefore going through this guide, we recommend that you familiarize yourself with the following, to help you gain a working knowledge of the SFF SDR development platform’s capabilities:

SFF SDR development platform user’s guide• SFF SDR development platform model-based design guide• FAQ supplied with the platform•

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Requirements

Accessing the platform’s documentationOn the Windows 1 Start menu, point to All Programs.Point to 2 Lyrtech, SFF SDR, and then click Documentation.

Your default Web browser starts and displays a page containing links to all the documents supplied with the SFF SDR development platform.

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Using the platform’s DSP

Using the platform’s DSPIn this chapter, you will learn how to use Real-Time Workshop and Code Composer Studio to target the Texas Instruments DM6446 DSP of your platform.

The results presented in this chapter are only supplied for illustration purposes. They are not intended to represent actual results.

Targeting the DSPTo target the DSP of your platform with the model-based design kit (MBDK) from Lyrtech, you must always perform certain procedures:

Create a new model or modify an existing model.1 Simulate the model.2 Run the model on the platform.3

Tutorial 1—Audio loopback simulationGoals

Demonstrate how to use Simulink to build a simple design and perform a simulation• Demonstrate how to configure the audio codec• Demonstrate how to configure a Simulink model to monitor data and perform remote operations•

Creating a new modelStart MATLAB.1 At the MATLAB command prompt, type 2 simulink.On the 3 File menu, point to New, and then click Model.Right-click anywhere in the model window, and then click 4 Model Properties on the shortcut menu that appears.The Models Properties dialog box appears.

On the 5 Callbacks tab, in the Model pre-load function group, Fs_DSP = 32000.The Fs_DSP variable appears as 32000 when you open the model for the first time. It is the sampling frequency of the audio path used later on in this tutorial.

Use the sample time as a relative time base. This means that specifying a Sample Time of 1 does not force the block to run at 1 Hz, it rather forces the block to run at a frequency relative to other blocks’ Sample Time values.

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Using the platform’s DSPFor example, if you specify a Sample Time of 2/48000 for block A and block B has a sample time of 1/48000, block B runs twice as fast as block A. In other words, its associated code is executed twice as fast as that of block A.

If no I/O block forces the DSP to run at a specific sample rate, the DSP runs the code as fast as possible. In other words, the DSP is free running. However, if you insert an I/O block such as an audio ADC block in your model, then the Sample Time is associated to the effective sample rate configured in the block (24 kHz, for example). This means that all the other blocks having the same sample time as the I/O block (e.g. 24 kHz) run at the same sample rate.

If you also specify a Frame Size, then the actual frame time (i.e. the time to execute a frame) is imposed by the following formula:

Frame time = Sample Time × Frame Size

By default, the Sample Time is 1.

Using the model properties is a good way to ensure that all your parameters remain with your .mdl file. You can also use a .mat file to save your MATLAB workspace parameters. Refer to Simulink Help to learn more about model properties.

To add the 6 Fs_DSP variable to the MATLAB workspace parameters, type Fs_DSP = 32000 at the MATLAB command prompt.Alternately, exit the model, and then reopen it.

Insert the following blocks in the new model:7 Signal processing Blockset—Signal Processing Sinks

1 × • Vector Scope1 × • Spectrum Scope

Lyrtech SFF SDR DP Blockset—DSP—Onboard1 × • DSP Options1 × • Audio Codec Configuration2 × • Audio Codec I/O

The following dialog box appears when you add the DSP Options block in your model:

MBDK DSP default configuration dialog boxFigure 1

Click 8 Yes.This configures the default simulation parameters of your SFF SDR development platform.

Connect the blocks as illustrated.9

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Using the platform’s DSPConnecting blocks in the modelFigure 2

Configure the blocks as follows10 Audio Codec Configuration

Sampling Frequency• : 32 kHzFrame Size• : 128Sample Time• : 1/Fs_DSP

Audio Codec I/OFrame Size• : 128Data Type• : SingleSelect the • Normalize ADC samples check boxSample Time• : 1/Fs_DSPDirection• : Input

Audio Codec I/O1Frame Size• : 128Data Type• : SingleSelect the • Normalize Audio Data Samples check boxSelect the • Enable Data Saturation check boxSample Time• : 1/Fs_DSPDirection• : Output

On the 11 Format menu, point to Port/Signal Displays, and then click Sample Time Colors.

Selecting Sample Time Colors is a good way to have an overview of the sample times of every block in your model. In the model at hand, all the blocks become red, indicating that all the blocks have the same sample time (i.e. they are executed at the base sample time). Refer to Simulink Help to learn more about this function.

On the 12 Format tab, point to Port/Signal Displays, and then click Port Data types.

Selecting Port Data types is a good way to have an overview of the data types of every link in your model. Refer to Simulink Help to learn more about this function.

On the 13 Format tab, point to Port/Signal Displays, and then click Signal Dimensions.

Selecting Signal Dimensions is a good way to have an overview of the dimensions of the signals, particularly when they are frame based. Refer to Simulink Help to learn more about this

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Using the platform’s DSPfunction.

Press CTRL+D on your keyboard.14 Alternately, on the Edit menu, click Update Diagram.

Updated modelFigure 3

Simulating the modelOn the model’s toolbar, configure the simulation’s stop time as 1 1.Select the simulation’s mode as 2 Normal.Click the play button.3 Two windows appear.

Right-click anywhere in the windows and click 4 Autoscale on the shortcut menu that appears.The following results are expected.

The values on the x and y axes are accurate in terms of frequency and time because the sample time value is equal to the sample time of the audio codec sampling frequency.

Time domain and frequency domain simulation resultsFigure 4

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Running the model on your platformTo take your simulation model and implement it on the SFF SDR development platform, you must perform the procedures outlined in this section.

Configuring the Real-Time Workshop target

On the model’s 1 Simulation menu, click Configuration Parameters.The Configuration Parameters dialog box appears.

Select 2 Real-Time Workshop.The following appear.

Real-Time Workshop configuration parametersFigure 5

Verify that 3 System target file is rt_sdr.tlc and that Template makefile is rt_sdr.tmf.

Configuring model Solver parameters

If not already open, on the model’s 1 Simulation menu, click Configuration Parameters.The Configuration Parameters dialog box opens.Select 2 Solver.On the 3 Type list, select Fixed-step.On the 4 Solver list, select discrete.

The code generated by the MBDK DSP solution runs indefinitely, regardless of the Stop time parameter. This parameter, however, determines the default time range of Simulink scopes when their Time range parameters are auto.

Configuring the hardware implementation model

If not already open, on the model’s 1 Simulation menu, click Configuration Parameters.The Configuration Parameters dialog box opens.

Select 2 Hardware Implementation.The following appears.

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Using the platform’s DSPHardware Implementation parametersFigure 6

Make sure that the 3 Device type is TI C6000.Click 4 OK.The Configuration Parameters dialog box closes.

Building the model

When building a DSP model, the building folder is always your current MATLAB folder.

On the toolbar of the model window, click the build button.◊◊

Alternately, press CTRL+B on your keyboard. You can also point to Real-Time Workshop on the model’s Tools menu, and then click Build Model.

When the build is successful, the ### Created Executable :{model name} message appears in the MATLAB window.

Running the model

Make sure that your platform is on and that an Ethernet cable is connected to its Ethernet port.1 Press the hardware reset button.2 Refer to the platform’s user’s guide for the location of this button.Connect an audio source such as an MP3 player to the line in connector.3 Connect headphones or speakers to the line out connector.4 On the model’s 5 Simulation menu, click External.Verify that your model is configured properly:6

On the model’s a Simulation menu, click Configuration Parameters.Expand b Real-Time Workshop, and then select Interface.Verify that the following parameters are configured as illustrated:c

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Using the platform’s DSPInterface selectionFigure 7

Click d OK.

In the model window, click the connect to model button.7 The Lyrtech development platform detection dialog box appears.Select a platform that is not in a locked state, and then click 8 Connect to Lyrtech development platform.

Lyrtech development platform detection dialog boxFigure 8

When the 9 .out file is loaded to the DSP of the platform, the model starts automatically.Your audio signal is displayed on the time and vector scopes. Use the auto-scale feature, if necessary. The actual aspect of the scope depends on the audio signal.

For details about targeting the DSP with the MBDK DSP solution, refer to the model-based design guide of the SFF SDR development platform.

Observing results

The scopes react according to the signal fed to the platform. For a better real-time display quality in the scope, proceed as follows:

On the 1 Tools menu, click External mode Control Panel.

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Using the platform’s DSPExternal mode control panelFigure 9

Click 2 Signal & Triggering.In the 3 External Signal & Triggering window, type 1 in the Duration text box.

You must not be connected to the platform to modify this parameter.

External Signal & TriggeringFigure 10

Click 4 Apply.Click 5 Close.

As a rule, when frame based, the Data Logging Size (in the DSP Options block) should be greater than the Duration value multiplied by the frame size and the number of scopes.

Saving, stopping, and disconnecting

Click 1 Disconnect from target.Save the model as 2 my_tutorial1.mdl.Close the model.3

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Tutorial 2—Processing an audio signal with a FIR filterGoals

Demonstrate how to use the FDA design block• Describe various data types supported by the MBDK DSP solution••

Modifying an existing model

Open the 1 my_tutorial1.mdl file or the tutorial1.mdl file (if you have not completed tutorial 1).Insert the following blocks in your model:2 Simulink—Math Operation

1 × • Add

Simulink—Signal Routing1 × • Switch

Simulink—Signal Attributes1 × • Data Type Conversion

Signal Processing Blockset—Filtering—Filter Designs1 × • Digital Filter Design

Lyrtech SFF SDR DP Blockset—DSP—Onboard1 × • Buttons


Connecting the blocksFigure 11

Configure the blocks as follows:4 Data Type Conversion block

Output data type mode• : singleInput and output to have equal• : Real World Value (RWV)

Buttons blockSample Time• : 128/Fs_DSPSelect the • Button 1 check box

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Using the platform’s DSPClear the • Button 2 to Button 5 check boxes

Switch blockCriteria for passing first input• : u2 > Threshold

Double-click the 5 Digital Filter Design block.The Digital Filter Design block implements a digital FIR or IIR filter that you design with the filter design and analysis tool (FDA Tool).

In the 6 Response Type group, select Lowpass.In the 7 Design Method group, select FIR, and then select Least-square.In the 8 Filter Order group, select Specify order, and then specify 4 in the text box.In the 9 Frequency Specifications group, on the Units list, select Hz.In the 10 Frequency Specifications group, specify 32000 for Fs, 3000 for Fpass, and 3300 for Fstop.In the 11 Magnitude Specifications group, specify 10 for Wpass and 1 for Wstop.Click 12 Design Filter.When the 13 Designing filter… Done message appears at the bottom of the window, close the Digital Filter Design window.

Running the model on your platformTo take your simulation model and implement it on the SFF SDR development platform, you must perform the following procedures:

Building the model

On the model’s ◊ Tools menu, point to Real-Time Workshop, and then click Build Model.

Alternately, you can press CTRL+B on your keyboard.

Running the model

Make sure that your platform is on and that an Ethernet cable is connected to its Ethernet port.1 Press the hardware reset button.2 Refer to the platform’s user’s guide for the location of this button.

Connect an audio source such as an MP3 player to the line in connector.3 Connect headphones or speakers to the line out connector.4 On the model’s 5 Simulation menu, click Connect to target.Alternately, you can click the connect to target button.

Click the play button.6 Alternately, press CTRL+T on your keyboard.

Observing the results

You should see and hear the differences in your signal between when you press button S5 and when you do not (assuming that your signals are at frequencies higher than 3 kHz, as is the case of most MP3 files). Refer to the platform’s user’s guide for the button’s location.

Saving, stopping, and disconnecting

Click 1 Disconnect from target.Save the model as 2 my_tutorial2.mdl.Close the model.3

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Using the platform’s FPGA

Using the platform’s FPGAIn this chapter, you will learn how to use the platform’s FPGA in your models. To achieve this goal, you will be called upon to create an FM modulator simulation with System Generator for DSP. You will design the simulation for narrow-band FM with a 100 kHz carrier frequency. For illustration purposes, that model is configured with an FPGA system clock of 1 MHz, shortening simulation time. The model used in this chapter will be reused and adapted later on to demonstrate transmissions to an FRS handset (supplied with the platform).

Make sure that System Generator for DSP is installed on your computer before proceeding with the • • tutorials of this chapter.In System Generator for DSP all the data paths are always sample based, but all the data type are • • fixed point. No floating-point data types are available.The results presented in this chapter are only supplied for illustration purposes. They are not • • intended to represent your actual results.

Targeting the FPGATo target the FPGA on your platform with the MBDK, you must perform certain procedures, just as with the DSP:

Create a new model or modify an existing model.1 Simulate the model.2 Run the model on the platform.3

Tutorial 3—Incorporating an FPGA in a Simulink simulationGoals

Demonstrate how to use System Generator for DSP to perform a simulation.• Demonstrate how to use the System Generator for DSP’s • DDS v5_0 block.

Creating a new modelStart MATLAB.1 At the MATLAB command prompt, type 2 simulink.On the 3 File menu, point to New, and then click Model.Right-click anywhere in the model window, and click 4 Model Properties on the shortcut menu that appears.

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Using the platform’s FPGAThe Model Properties dialog box appears.

On the 5 Callbacks tab, in the Model pre-load function group, type Fs_FPGA = 1e6.The Fs_FPGA variable is created and becomes the frequency of the system clock.

The sampling frequency specified in each block is not imposed on the FPGA clock. In a Simulink model, the sample time is merely a tag on each “step” of an algorithm. A sampling time of 1 would produce the same bitstream file (.bit) for the FPGA. For the spectrum scope and time scope, it is sometimes useful to see the results of the simulation in terms of clock cycles, while sometimes it is useful to do so in terms of seconds. Using a variable allows you to switch all the sample times of your design simultaneously. Use a sample time of 1 for clock cycle information and a clock period cycle for the time domain and frequency domain information.

Insert the following blocks in the new model:6 Simulink—Simulink Sink

1 × • Scope


Simulink—Signal Routing1 × • Manual Switch

Signal Processing Blockset—Signal Processing Sources1 ×• Sine Wave1 × • DSP Constant

Signal Processing Blockset—Signal Processing Sinks1 × • Spectrum Scope

Xilinx Blockset—Index1 × • System Generator1 × • Gateway In2 × • Gateway Out1 × • CMult2 × • Const1 ×• AddSub1 × • DDS v5_0

DDS stand for direct digital synthesizer. It is the main block used in this model. Refer to System Generator for DSP Help for details.


A constant corresponding to the carrier frequency is added to the amplitude from the Sine Wave block, which is then sent to the data port of the DDS v5_0 block. The frequency output, controlled by the data port, thus changes as the amplitude of the sine wave changes.

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Using the platform’s FPGAConnecting blocks in the modelFigure 12

Configure the blocks as follows:8 Data Type Conversion block

Output data type mode• : int16Input and output to have equal• : Real World Value (RWV)

Sine Wave blockAmplitude• : 2^15-1Frequency• : 3000Sample Time• : 1/Fs_FPGAOutput Data Type• : single

Spectrum Scope blockOn the • Scope Properties tab, select the Buffer Input check boxOn the • Scope Properties tab, specify Buffer Size as 2^12On the • Axis Properties tab, specify Frequency display limits as User-definedOn the • Axis Properties tab, specify the Minimum X-limit as 90 and the Maximum X-limit as 110

System Generator blockSimulink System Period• : 1/Fs_FPGA

Gateway In blockNumber of bits• : 16Binary point• : 0Sample period• : 1/Fs_FPGA

Gateway Out blockClear the • Translate into output port check box

Const blockClear the • Sampled Constant check box

DDS v5_0 blockFunction• : sine and cosineOutput Frequencies• : ProgrammableExplicit Sample Period• : Inferred from inputsClear the • Provide enable port check box

To get two inputs from one scope, double-click the scope block. In the window that appears (below), click the parameters button. In the Axes group, modify Number of axes to 2. Click OK.

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Using the platform’s FPGAGetting two inputs from one scopeFigure 13

In the 9 Constant block connected to the WE of the DDS v5_0 block, select type Boolean and constant value 1.Double-click the 10 DDS v5_0 block.On the 11 Advanced tab, specify the following:

DDS clock rate (MHz)• : 1. This is the actual clock rate of your hardware clock. A lower clock frequency means less points to calculate, thus a faster simulation. For the purposes of this example, use 1 MHz.Spurious free dynamic range (dB)• : 16*6. This lowers the spurious in the output signal by increasing the resolution (bits) of the output. As a rule, 1 bit equals 6 dB of SFDR.Frequency Resolution (Hz)• : 0.2. This impacts the number of bits of the input data type at the data input port. To determine how many bits the port needs, at the MATLAB command prompt, type ceil(log2(1e6/0.2)), indicating that the answer is 23 bits.Noise shaping• : Phase dithering. This noise shaping technique is necessary as the SFDR is between 60 dB and 102 dB.

On the 12 Implementation tab, select Block RAM.12 Double-click the 13 AddSub block.On the 14 Output Type tab, select User-Defined Precision, specify the output type as Signed, the number of bits as 23, and the binary point as 0.Double-click the 15 Constant block connected to the AddSub block.Select 16 Signed, specify the constant value as (100e3/1e6)*2^23, specify the number of bits as 23, and the binary point as 0.

The carrier frequency is configured through the Constant block connected to the AddSub block. The value sent to the data input port is called phase increment. We want a 100 kHz carrier frequency from a DDS with a 1 MHz clock. The relation is simple:

DDSclock

fout =Pinc_max

Pinc_data_port

For details on phase incrementation and DDS, refers to System Generator for DSP Help.

Double-click the 17 CMult block, specify (1.5e3/1e6)*2^(23–15) as the Value, specify the number of bits as 16, and the binary point as 16.

The last value configures the peak frequency deviation. It is related to the frequency modulation index. Frequency modulation (FM) conveys information by varying the frequency of a carrier signal. The frequency modulation index indicates by how much the modulated variable varies around its unmodulated level. The formula for the modulation index is:

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Using the platform’s FPGA

b =fm

Df

Where fm is the highest modulating frequency and Δf is the carrier frequency deviation. For narrow-band FM, such as FRS, the modulation indices must be smaller than 1. Let us use 0.5. The highest modulating frequency coming from the sine wave is 3 kHz; therefore, we need a carrier frequency deviation of 1.5 kHz. The phase increment corresponding to 1.5 kHz is equal to (1.5×103/1×106)×223. The peak value of our 16-bit sine wave is 215–1. We are looking for the constant value K where:

(215- 1)K =

106

1.5 # 103

c m# 223

Configuring the simulation parametersOn the model’s 1 Simulation menu, click Configuration Parameters.Alternately, you can press CTRL+E on your keyboard.

In the 2 Simulation time group, specify 1 in the Stop time text box.In 3 Solver options section, select Variable-step as the type and discrete as the solver.Click 4 OK.

Saving the modelSave the model file as ◊ my_tutorial3.mdl.

Running the modelClick the play button.◊

Alternately, press CTRL+T on your keyboard.

System Generator for DSP produces simulation results that are bit-true and cycle-true to the hardware it generates. To say that a simulation is bit-true means that, at the boundaries (e.g. interfaces between the System Generator block and non-System Generator for DSP blocks), a value produced in a simulation is identical, bit for bit, to the corresponding value produced in the hardware.

To say that a simulation is cycle-true means that, at the boundaries, corresponding values are produced at corresponding times. The boundaries of the design are the points where System Generator for DSP blocks exist. When the System Generator for DSP generates hardware, the Gateway In or Gateway Out blocks become top-level input or output ports.

Observing the resultsOn the spectrum scope, you can see a typical FM spectrum around the carrier frequency of 100 kHz. On the time scope, you can see that both DDS output signals are in quadrature with each other.

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Using the platform’s FPGASpectrum scope view of FM with a 0.5 spectrum index and Time scope quadrature signalFigure 14

Stopping and disconnectingClick the stop simulation button.1 Close the model.2

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Using the platform’s mixed processor architecture


In this chapter, you will use the VPSS in transferring data from a DSP to an FPGA. To do so, you will use the platform’s codec’s synchronization mechanism and the custom registers.

Tutorial 4—Using VPSS for streaming application in the FPGA modelGoals

Demonstrate how to achieve codec synchronization• Demonstrate how to use the VPSS in a DSP model• Demonstrate how to use custom registers to receive DSP control signals•

Creating a new modelStart MATLAB.1 At the MATLAB command prompt, type 2 simulink.On the 3 File menu, point to New, and then click Model.Right-click anywhere in the model window, and then click 4 Model Properties on the shortcut menu that appears.The Model Properties dialog box appears.On the 5 Callbacks tab, in the Model pre-load function group, type Fs_FPGA = 37.5e6.The Fs_FPGA variable’s value is 37.5e6, which becomes the system clock’s frequency.Insert the following blocks in the model.6 Simulink—Sinks

1 × • Scope4 × • Terminator

Signal Processing Blockset—Signal Processing Sources1 × • Sine Wave3 × • DSP Constant

Lyrtech SFF SDR DP Blockset—FPGA—Onboard1 × • FPGA Configuration1 × • Custom Register2 × • VPSS

Xilinx Blockset—Basic Elements1 × • System Generator3 × • Const1 × • Mux

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Using the platform’s mixed processor architectureConnect the blocks as illustrated.7

Connecting the blocks in the modelFigure 15

Configure the blocks as follows:8 Sine Wave block

Amplitude• : 2^15–1Frequency• : 3000Sample time• : 1024/Fs_FPGA

FPGA configuration blockClock Source• : 37.5 MHzSelect the • Synchronize Audio Codec with FPGA System Clock check boxClock divider• : 4

Custom register blockRegister ID• : 0Direction• : ReadOutput Arithmetic Type• : UnsignedOutput Width• : 1Binary Point• : 0Sample period• : 1024/Fs_FPGA

VPSS blockDirection• : one RX (the one with the Sine Wave block) and one TX (the one with the scope)Output Arithmetic Type• : SignedOutput width• : 32Binary Point• : 0Sample period• : 1024/Fs_FPGA

System Generator blockSimulink system period• : 1/Fs_FPGA

Const block for the ren and wen inputs of the VPSS (2) blockClear the • Sampled constant check boxType• : boolValue• : 1

Const block for input d1 of Mux blockType• : SignedValue• : 0Sample Time• : 1024/Fs_FPGA

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For data streaming applications, configure your • ren and wen as always asserted.Because the • Synchronize Audio Codec with FPGA System Clock check box is selected in the FPGA configuration block, the FPGA system clock and the codec clock are the same.

Saving the modelSave the model as my_tutorial4.mdl.◊

Building an FPGA modelBefore you can build an FPGA model, you must provide to the MBDK FPGA solution and System Generator for DSP the necessary information to build the model. Proceed as follows to do so.

Configure the 1 FPGA configuration block.On the a Clock Type list, select Real-Time Hardware Implementation.On the b Clock Source list, select the hardware clock used by the System Generator for DSP design.

Configure the 2 System Generator block to build the FPGA model.On the a Compilation list, point to Hardware Co-Simulation, then Lyrtech, and then click SFF SDR DP.In the b Target directory text box, specify the folder where the generated FPGA code must be created. This folder also contains the bitstream corresponding to your model, when the building process is complete. The name of the bitstream is name_of_FPGA_model_evm.bit, where name_of_FPGA_model corresponds to the name of your FPGA model.On the c Synthesis tool list, select XST.On the d Hardware description language list, select VHDL.In the e FPGA clock period and Simulink system period text boxes, specify 1e9/37.5e6 or less.

To build the bitstream, click 3 Generate.The code generation process starts for each block of the FPGA model (except for Simulink I/O blocks, only present for simulation purposes). When the code generation is complete, the System Generator block opens a Perl session and uses ISE Foundation tools to create a bitstream from the model’s generated code. When the process is complete, a message appears to inform you of the fact.

Observing the resultsThis bitstream will be use with the .out of the following DSP model. Proceed to the next section.

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Tutorial 5—Using the VPSS to stream data in a DSP modelGoals

Demonstrate how to use the VPSS in a DSP model• Demonstrate how to use the • Custom Register for DSP control signalDemonstrate how to achieve codec synchronization in a DSP model• Demonstrate how to load a bitstream from the DSP model•

Modifying an existing modelOpen the 1 my_tutorial2.mdl file.Remove the 2 Digital Filter Design block and Switch block from the model.Insert the following blocks in the model:3 Simulink—Signal Routing

Manual Switch • (×1)

Lyrtech SFF SDR DP Blockset—DSP—OnboardCustom Register • (×1)VPSS • (×2)

Lyrtech SFF SDR DP Blockset—DSP—Miscellaneous toolsSet bitstream• (×1)Lyrtech priority manager • (×1)



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Using the platform’s mixed processor architectureConfigure the blocks as follows:5 Custom Register block

Register ID• : 0Direction• : Write to FPGAFPGA Data Type• : UnsignedFPGA Binary Point• : 0DSP Data Type• : Int32Sample period• : 128/Fs_DSP

Audio Codec Configuration blockSampling frequency• : Defined with FPGA configuration block

VPBE blockPacket size• : 128Data Type• : SingleSample period• : 1/Fs_DSP

VPFE blockPacket size• : 128Data Type• : SingleSample period• : 1/Fs_DSP

Data Type Conversion blockOutput data type mode• : int32

Right-click anywhere in the model window, and then click 6 Model Properties on the shortcut menu that appears.On the 7 Callbacks tab, in the Model pre-load function group, type Fs_DSP = 36621.This maintains the scope accurate as this is the new sampling frequency of the codec (37.5 MHz/1024 = 36621 Hz).On the model’s 8 Format menu, point to Block Displays, and select Sorted.Update your model and make sure that 9 VPBE is smaller than VPFE.If it is not, open the Lyrtech priority manager block.

Lyrtech priority managerFigure 17

Select the name the VPFE block (by default, VPSS Bus or VPSS Bus 1), and then click Down until the block is below the VPBE block.

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Using the platform’s mixed processor architectureLyrtech priority managerFigure 18

The sorted order of blocks shows the sequence in which each part of the processing is called. In the case of the VPBE and VPFE, it is useful because if the VPFE is performed before the VPBE, the VPSS port becomes deadlocked.

Double-click 10 Set Bitstream, and then select the bitstream created during tutorial 4.

Running the model on the platformTo take your simulation model and implement it on the SFF SDR development platform, proceed as follows:

Building the model

On the model’s ◊ Tools menu, point to Real-Time Workshop, and then click Build Model.Alternately, you can press CTRL+B on your keyboard.

Before building the model, verify that the value of Fs_DSP is 36621. If it is not, save the model as my_tutorial5.mdl, close the model, and then reopen it. Alternately, you can type Fs_DSP = 36621 at the MATLAB command prompt.

Connecting to the target and running the model

Make sure that the SFF SDR development platform is on and that and Ethernet cable is connected 1 to its Ethernet port.Press the hardware reset button.2 Refer to the platform’s user’s guide for the location of this button.Connect an audio source such as an MP3 player to the line in connector.3 Connect headphones or speakers to the line out connector.4 On the model’s 5 Simulation menu, click Connect to target.Alternately, you can click the toolbar’s connect to target button.Click the play button.6 Alternately, press CTRL+T on your keyboard.

Observing the results

Toggle the manual switch of the DSP model. Normally hearing audio in both switch positions indicates that the VPSS is functioning properly. Press the S5 button of the digital processing module. This mutes the audio signal when the manual switch is positioned for the VPFE.

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Stopping, stopping, and disconnecting

Click the disconnect from target button.1 Save the model as 2 my_tutorial5.mdl.Close the model.3

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31

Using the data conversion and RF modules


This chapter will help you learn how to include all three modules of your platform into your designs.

Tutorial 6—Using the DAC in an FPGA modelGoals

Demonstrate how to use the DAC block• Demonstrate how to synchronize with the DAC clock•

Modifying an existing modelOpen models 1 my_tutorial3.mdl and my_tutorial4.mdl.Move the 2 DDS v5_0 block and its Constant block, the Add block, the two Gateway Out blocks, the Spectrum Scope block, and the Scope block from the tutorial 3 model into the tutorial 4 model.Connect the blocks as illustrated.3


Remove the two 4 Gateway Out blocks from the model.Insert the following blocks in the model:5

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Using the data conversion and RF modulesSignal Processing Blockset—Signal Processing Sources

1 × • DSP Constant

Lyrtech SFF SDR DP Blockset—FPGA—Onboard1 × • Custom Register (×1)

Lyrtech SFF SDR DP Blockset—FPGA—Add-on hardware modules2 × • ADACMaster III1 × • RF module configuration1 × • RF module

Duplicate the 6 Mux and Zero constant twice.Connect the blocks as illustrated.7


Configure the blocks as follows:8 DSP Constant block

Value• : ceil((462.5625e6-432e6)/80e6*2^29)Sample period• : 2560/Fs_FPGA

Custom Register blockRegister ID• : 1Direction• : ReadOutput Arithmetic Type• : UnsignedOutput Width• : 29Binary Point• : 0Sample period• : 2560/Fs_FPGA

ADACMaster III output (DAC) blocksChannel ID• : One A and one BSample period• : 1/Fs_FPGABinary point• : 15Mode• : DAC

Insert the following blocks in the model:9 Xilinx Blockset—Basic Elements

1 × • Convert2 × • Upsampler1 × • Inverter

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Using the data conversion and RF modulesSignal Processing Blockset—Signal Processing Sources

1 × • DSP Constant

Simulink—Sinks2 × • Terminator



Configure the block as follows:11 Upsampler block

Sampling Rate• : 2560Select the • Copy samples check box

Convert blockType• : Bool

Right-click anywhere in the model window, and then click 12 Model Properties on the shortcut menu that appears.The Model Properties dialog box appears.On the 13 Callbacks tab, in the Model pre-load function group, type Fs_FPGA = 80e6.The Fs_FPGA variable’s value is 80e6, which becomes the frequency of the system clock.Double-click the 14 DDS v5_0 block.On the 15 Basic tab, select the Negate sine check box.On the 16 Advanced tab, modify DDS clock rate to 80.Double-click the 17 AddSub block.On the 18 Output Type tab, modify the Number of bits to 29.Double-click the 19 FPGA configuration block.On the 20 FPGA system clock list, select Clock source LYRIO+ Sync Bus 1 clock.Select the 21 Synchronize audio codec with FPGA system clock check box.Specify the clock source value as 80 MHz and the clock divider value as 10.22 This creates a codec clock running at 31.25 kHz. For details about valid clock divider values, refer to the FPGA configuration block’s Help.Double-click the 23 DSP Constant blocks, and then configure all the sample time values to 2560/Fs_FPGA.Double-click the 24 VPSS blocks, and then configure all the sample time values to 2560/Fs_FPGA.Double-click the 25 Sine Wave block, and then configure its sample time value to 2560/Fs_FPGA.Double-click the 26 Custom Register blocks, and then configure all the sample time values to 2560/Fs_FPGA.

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The negative sine is necessary to get an upper sideband signal from the analog quadrature • modulator of the RF module. This can be ascertained with a spectrum analyzer.The number of bits of the DDS data import port is explained in tutorial 3.• The mult is discarded from tutorial 3 because K’s value for FRS specifications nears 1.•

Building the FPGA modelDouble-click the 1 System Generator block, and then specify 1e9/80e6 as the FPGA clock period.Save your model as 2 my_tutorial6.mdl.In the 3 System Generator dialog box, click Generate.

Before building the FPGA model, verify that the value of Fs_FPGA is 80000000. If it is not, close the model, and then reopen it. Alternately, you can type Fs_FPGA = 80e6 at the MATLAB command prompt.

Observing the resultsThe bitstream generated with the System Generator block is used with the .out file of the following tutorial. Proceed to tutorial 7.

Saving the modelSave the model as ◊ my_tutorial6.mdl.

Tutorial 7—Using the data conversion and RF modules in a DSP modelGoals

Demonstrate how to configure the RF module to perform an FRS transmission.• Demonstrate how to achieve codec synchronization in a DSP model.•

Modifying an existing modelOpen the 1 my_tutorial5.mdl file (or the tutorial5.mdl file if you did not complete tutorial 5).Insert the following blocks in the model:2 Lyrtech SFF SDR DP Blockset—DSP—Onboard

1 × • Custom Register

Lyrtech SFF SDR DP Blockset—DSP—Add-on hardware modules1 × • RF module1 × • ADACMaster III control

Signal Processing Blockset—Signal Processing Sources1 × • DSP Constant


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Using the data conversion and RF modulesRight-click anywhere in the model window, and then click 3 Model Properties on the shortcut menu that appears.The Model Properties dialog box appears.On the 4 Callbacks tab, in the Model pre-load function group, type Fs_DSP = 31250.This maintains the scope accurate because this is the new sampling frequency of the codec (80 MHz/2560 = 31250 Hz).Open the 5 my_tutorial2.mdl file (or the tutorial2.mdl file if you did not complete tutorial 2).Drag the 6 Digital filter design tool block from the my_tutorial2.mdl to the my_tutorial5.mdl (or from tutorial2.mdl to tutorial5.mdl, according to your situation).Double-click the 7 Digital filter design tool block, and then modify the Fs value for 31250.Connect the blocks as illustrated.8


Configure the blocks as follows:9 Custom Register block

Register ID• : 1Direction• : Write to FPGAFPGA Data Type• : UnsignedFPGA Binary Point• : 0DSP Data Type• : Int32Sample period• : 128/Fs_DSP

RF module blockSelect the • TX check boxTX base frequency• : 432 MHzReference Clock Source• : Onboard 10 MHzSample Time• : 128/Fs_DSP

VPBE and VPFE blocksData Type• : Int32

Audio Codec I/O In blockClear the • Normalize Audio Data Samples check box

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Using the data conversion and RF modulesAudio Codec I/O Out block

Clear the • Normalize Audio Data Samples check boxClear the • Enable Data Saturation check box

ADACMaster III control blockOn the • DAC tab, select the Enable DAC check box.On the • DAC tab, on the Operation Mode list, select Full Bypass.On the • Clock and PLL tab, ADC/DAC Clock Source: Use PLLOn the • Clock and PLL tab, PLL Reference Time Base: ExternalOn the • Clock and PLL tab, Additional Reference Time Value: 10On the • Clock and PLL tab, Required clock for ADC, FPGA design, and DAC: 80On the • Advanced tab, Sample time: 128/Fs_DSP

DSP Constant blockValue• : ceil((462.5625e6 -432e6) /80e6*2^29)Data Type• : int32Sample Time• : 128/Fs_DSP

The equation used in calculating the DSP constant is the same as the one presented in tutorial 3 • for setting the carrier frequency. The carrier frequency of FRS channel 1 is 462.5625 MHz, which is obtained from intermediate frequency (IF) 30.5625 MHz (controlled by the DSP constant) and heterodyned with a frequency of 432 MHz.Because the DAC and ADC are AC coupled, you must always work at an IF higher than 3 MHz.•

Right-click the RF Module block and select Block properties. Enter the value 0 in the Priority field.10

Because the conversion module gets its clock signal form the RF module, the latter must be initialize first.

Double-click the 11 Set Bitstream block, and then select the bitstream created in tutorial 6.

Building the modelSave the model as 1 my_tutorial7.mdl.On the model’s 2 Tools menu, point to Real-Time Workshop, and then click Build Model.Alternately, you can press CTRL+B on your keyboard.

Before building the model, verify that the value of Fs_DSP is 31250. If it is not, close the model, and then reopen it. Alternately, you can type Fs_DSP = 31250 at the MATLAB command prompt.

Connecting to the target and running the modelMake sure that the SFF SDR development platform is on and that an Ethernet cable is plugged to its 1 Ethernet port.Press the hardware reset button.2 Refer to the platform’s user’s guide for the location of this button.Connect an audio source such as an MP3 player to the line in connector.3 Connect headphones or speakers to the line out connector.4

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Using the data conversion and RF modulesOn the model’s 5 Simulation menu, click Connect to target.Alternately, you can click the connect to target button.Click the play button.6 Alternately, press CTRL+T on your keyboard.

Observing the resultsTurn on the FRS handset supplied with the platform, tune into channel 1, and then make sure that there is no privacy code. If this is the case, you see 00 next to the channel number. When you press button S5 on the digital processing module, the audio signal from the line out connector stops and is output by the FRS handset.

Stopping and disconnectingClick the disconnect from target button.1 Close the model.2

SFF SDR DP - MBDK tutorial

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