INSTITUTO POLITECNICO NACIONAL ESCUELA SUPERIOR DE INGENIERIA MECANICA Y ELECTRICA UNIDAD ZACATENCO INGENIERIA EN COMUNICACIONES Y ELECTRONICA “Guia de Instrucciones del Microcontrolador MSP430G2231 y Modos de Direccionamiento” Alumno: González Mondragón Luis Alejandro Grupo: 7CM7 Materia: Microcontroladores Profesor: Edgar Roman Calderón Díaz
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INSTITUTO POLITECNICO NACIONAL ESCUELA SUPERIOR DE INGENIERIA MECANICA
Y ELECTRICA
UNIDAD ZACATENCO
INGENIERIA EN COMUNICACIONES Y ELECTRONICA
“Guia de Instrucciones del Microcontrolador MSP430G2231
y Modos de Direccionamiento”
Alumno: González Mondragón Luis Alejandro Grupo: 7CM7 Materia: Microcontroladores Profesor: Edgar Roman Calderón Díaz
Indice
• Modos de Direccionamiento a) Modo de Registros b) Modo Indexado c) Modo Simbolico d) Modo Absoluto e) Modo de Registros Indirecto f) Modo Indirecto de Registro Autoincrementado g) Modo Inmediato
• Set de Instrucciones del Microcontrolador MSP430G2231
a) Set de Instrucciones b) Instrucciones de Formato Doble c) Instrucciones de Formato Simple d) Instrucciones de Salto e) Ciclos y Longitudes de las Instrucciones
Modos de Direccionamiento Existen 7 diferentes modos de direccionamiento para el operando de fuente y 4 para el de destino que pueden direccionar el espacio completo de dirección sin excepciones.
NOTA: .B o .W explican la forma en que se tratara la instrucción, si es a nivel de Bit (8 Bits) o a nivel de Palabra (16 Bits) a) Modo de Registros (Rn) Opera con información dentro de los registros de la ALU MOV.W R6 , R7 MOV.B R5 , R7
Mem (0203h) = 0A1h R5 = 00061hC = 0, Z = 0, N = 1 C = 0, Z = 0, N = 0
(Low byte of register) (Addressed byte)+ (Addressed byte) + (Low byte of register)- (Addressed byte) - (Low byte of register, zero to High byte)
3.3 Addressing ModesSeven addressing modes for the source operand and four addressing modes for the destination operandcan address the complete address space with no exceptions. The bit numbers in Table 3-3 describe thecontents of the As (source) and Ad (destination) mode bits.
Table 3-3. Source/Destination Operand Addressing ModesAs/Ad Addressing Mode Syntax Description00/0 Register mode Rn Register contents are operand01/1 Indexed mode X(Rn) (Rn + X) points to the operand. X is stored in the next word.01/1 Symbolic mode ADDR (PC + X) points to the operand. X is stored in the next word.
Indexed mode X(PC) is used.01/1 Absolute mode ADDR The word following the instruction contains the absolute
address. X is stored in the next word. Indexed mode X(SR) isused.
10/- Indirect register mode @Rn Rn is used as a pointer to the operand.11/- Indirect autoincrement @Rn+ Rn is used as a pointer to the operand. Rn is incremented
afterwards by 1 for .B instructions and by 2 for .W instructions.11/- Immediate mode #N The word following the instruction contains the immediate
constant N. Indirect autoincrement mode @PC+ is used.
The seven addressing modes are explained in detail in the following sections. Most of the examples showthe same addressing mode for the source and destination, but any valid combination of source anddestination addressing modes is possible in an instruction.
NOTE: Use of Labels EDE, TONI, TOM, and LEO
Throughout MSP430 documentation EDE, TONI, TOM, and LEO are used as generic labels.They are only labels. They have no special meaning.
50 CPU SLAU144H December 2004 Revised April 2011Submit Documentation Feedback
SET DE INSTRUCCIONES El set completo del MSP430 consiste en 27 instrucciones de Nucleo y 24 instrucciones emuladas. Hay 3 formatos para las instrucciones de Nucleo:
Ø Operando Doble Ø Operando Simple Ø Salto
Todas las instrucciones de operando Simple y de Doble Operando pueden ser instrucciones usadas como byte o palabra mediante las extensiones .B o .W. Si no se usa una extensión, la instrucción es una instrucción de palabra.
0xxx
4xxx
8xxx
Cxxx
1xxx
14xx
18xx
1Cxx
20xx
24xx
28xx
2Cxx
30xx
34xx
38xx
3Cxx
4xxx
5xxx
6xxx
7xxx
8xxx
9xxx
Axxx
Bxxx
Cxxx
Dxxx
Exxx
Fxxx
RRC RRC.B SWPB RRA RRA.B SXT PUSH PUSH.B CALL RETI
Ø Instrucciones de Formato Doble En el siguiente listado se pueden apreciar las instrucciones que gozan de este formato.
Ejemplos de el uso de algunas instrucciones de Doble formato usando algunos modos de Direccionamiento previamente vistos: MOV.B #0X00, &P2SEL MOV.W #DATOS, R5 MOV.B @R5+,&PIOUT MOV.W #49998,R4 MOV.B &P2IN,R5 CMP.B #0XC0,R5 BIC.B #BIT6 + BIT7,&P2DIR BIS.B #0XFF, &P1DIR AND.B #0XC0,R5
* The status bit is affectedThe status bit is not affected
0 The status bit is cleared1 The status bit is set
NOTE: Instructions CMP and SUBThe instructions CMP and SUB are identical except for the storage of the result. The same istrue for the BIT and AND instructions.
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* The status bit is affectedThe status bit is not affected
0 The status bit is cleared1 The status bit is set
All addressing modes are possible for the CALL instruction. If the symbolic mode (ADDRESS), theimmediate mode (#N), the absolute mode ( EDE) or the indexed mode x(RN) is used, the word thatfollows contains the address information.
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Conditional jumps support program branching relative to the PC and do not affect the status bits. Thepossible jump range is from 511 to +512 words relative to the PC value at the jump instruction. The10-bit program-counter offset is treated as a signed 10-bit value that is doubled and added to the programcounter:PCnew = PCold + 2 + PCoffset 2
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El numero de ciclos de reloj del CPU requeridos por una Instrucción depende del formato de la instrucción y de los modos de direccionamiento usados, no de la misma Instrucción. El numero de ciclos de reloj se refiere al MCLK. Ciclos y Longitudes de las Instrucciones de Formato Simple:
Todas las instrucciones de Salto requieren un código de palabra, y toman 2 ciclos de CPU para ejecutarse, sin importar si el salto se hace o no.
Instruction Set www.ti.com
3.4.4 Instruction Cycles and LengthsThe number of CPU clock cycles required for an instruction depends on the instruction format and theaddressing modes used - not the instruction itself. The number of clock cycles refers to the MCLK.
3.4.4.1 Interrupt and Reset CyclesTable 3-14 lists the CPU cycles for interrupt overhead and reset.
Table 3-14. Interrupt and Reset CyclesAction No. of Cycles Length of InstructionReturn from interrupt (RETI) 5 1Interrupt accepted 6 -WDT reset 4 -Reset (RST/NMI) 4 -
3.4.4.2 Format-II (Single Operand) Instruction Cycles and LengthsTable 3-15 lists the length and CPU cycles for all addressing modes of format-II instructions.
Table 3-15. Format-II Instruction Cycles and LengthsNo. of Cycles
NOTE: Instruction Format II Immediate ModeDo not use instruction RRA, RRC, SWPB, and SXT with the immediate mode in the destinationfield. Use of these in the immediate mode results in an unpredictable program operation.
3.4.4.3 Format-III (Jump) Instruction Cycles and LengthsAll jump instructions require one code word, and take two CPU cycles to execute, regardless of whetherthe jump is taken or not.
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Ciclos y Longitudes de las Instrucciones de Formato Doble:
www.ti.com Instruction Set
3.4.4.4 Format-I (Double Operand) Instruction Cycles and LengthsTable 3-16 lists the length and CPU cycles for all addressing modes of format-I instructions.
Table 3-16. Format 1 Instruction Cycles and LengthsAddressing Mode Length of