Session 06 v.3

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» Fifth levelD i g i t a l D e s i g n u s i n g V H D L

Session Six

Introduced by

Cairo-Egypt

Version 03 – June 20121

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about Start Group

2

Mahmoud AbdellatifAlaa Salah Shehata Mohamed SalahMohamed Talaat

[email protected] www.slideshare.net/StartGroup

www.facebook.com/groups/start.group www.startgroup.weebly.com [email protected]

+ 02 0122-4504158 M.A www.youtube.com/StartGroup2011+ 02 0128-0090250 A.S

Session Six

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Outline

Session Six 3

What is FSM

Vending Machine Example

String Detector

6

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What is FSM

Session Six 4

Any digital system consists of two part:

Data part Responsible for the processing of data. The processing is done through some blocks such as (full adder, digital filter, decoder,…)

Control partDescribes how and when these blocks will communicate with each other.The control part is generally described using a finite state machine.

Data Part

Control Part

Inputs Outputs

Controls

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What is FSM

Session Six 5

Finite State Machine

FSM is simply a finite number of states that each state describes a certain set of control outputs that are connected to the data part blocks.

The transition between these states depends mainly on the inputs of the FSM.

There are two main types of FSM: Moore FSM Mealy FSM

S1

S2

S4

S3

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What is FSM

Session Six 6

Assigning Moore OutputsUse a combinational ‘process’ to model Output LogicOutputs are only dependent on the current state

Assigning Mealy OutputsUse a combinatorial ‘process’ to model Output LogicOutputs are dependent on the current state as well as the input Output

Logic

OutputLogic

OutputLogic

OutputLogic

Outputs = f(Inputs, State)

Outputs = f(State)

Machine State

Registers

Next state

Present state Outputs

InputsOutputLogic

Next StateLogic

Machine State

Registers

Next state

Present state Outputs

InputsOutputLogic

Next StateLogic

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What is FSM

Session Six 7

Moore FSM

Mealy FSM

state 1 state 2

transitioncondition 1

transitioncondition 2

state 1 state 2

transition condition 1 /output 1

transition condition 2 /output 2

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What is FSM

Session Six 8

Example Detecting 10 sequence

S0 / 0 S1 / 0 S2 / 1

0 1

1 0

reset

Meaning of states:

S0: No elements of the sequenceobserved

S1: “1”observed

S2: “10”observed

S0 S1

0 / 0 1 / 0 1 / 0

0 / 1reset

Meaning of states:

S0: No elements of the sequenceobserved

S1: “1”observed

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What is FSM

Session Six 9

Example Detecting 10 sequence

clock

input

Moore

Mealy

0 1 0 0 0

S0 S1 S2 S0 S0

S0 S1 S0 S0 S0

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FSM in VHDL [Three Processes]

Session Six 10

The “3 Processes, 1 Clocked + separate transitions/actions” style

1-Process modeling “Next State Logic”

2-Process modeling "Current State Registers"

3-Process modeling “Output Logic”

State Registers

OutputLogic

Next StateLogic

Machine State

Registers

Next state

Present state Outputs

InputsOutputLogic

Next StateLogic

Mealy machines

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Example 24

Session Six 11

Vending Machine Using Moore Machine (3 Processes)

Specifications-Deliver package of gum after 0.75 LE deposited -Single coin slot for 0.25 LE and 0.50 LE

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Example 24

Session Six 12

STEP IUnderstand the problem Draw a block diagramN = 0.25 LE D = 0.50 LE

CoinSensor

Vending Machine

FSM

N

D

reset

Clk

Open

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Example 24

Session Six 13

STEP IIDraw State Diagram

S3

S6

S8 S7

S5

S2

S4

S1

S0 N

N

N

N

D

D

D

D

openopen

open open open

Reset

N = 0.25 LED = 0.5 LE

CoinSensor

Vending Machine

FSM

N

D

reset

Clk

Open

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Example 24

Session Six 14

STEP IIIState Diagram Minimization

Reset

S2

S3

S1 D

open

S0

N

D

N

N,D

CoinSensor

Vending Machine

FSM

N

D

reset

Clk

Open

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Example 24

Session Six 15

STEP IVVHDL CODE

1- FSM INTERFACE

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity vend_machine_moore is Port (

N : in STD_LOGIC; D : in STD_LOGIC; reset : in STD_LOGIC; clk : in STD_LOGIC; tank_open : out STD_LOGIC);

end vend_machine_moore;

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Example 24

Session Six 16

STEP IVVHDL CODE

2- DEFINE STATES

architecture Behavioral of vend_machine_moore is type states is (s0,s1,s2,s3); signal n_state,p_state :states;

Begin ..

Reset

S2

S3

S1 D

open

S0

N

DN

N,D

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Example 24

Session Six 17

STEP IVVHDL CODE

3- Transition Process

transition :process(clk,reset) begin

if reset='1' then p_state <=s0 ;

elsif rising_edge(clk) then p_state <= n_state ;

end if; end process transition;

Reset

S2

S3

S1 D

open

S0

N

DN

N,D

Machine State

Registers

Next state

Present state Outputs

InputsOutputLogic

Next StateLogic

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Example 24

Session Six 18

STEP IVVHDL CODE

4- Next State Logic

Responsible for generating the next

state logic.

next_state :process(N,D,p_state) --p_state in list to trigger --process if inputs are constants

begin case p_state is when s0 =>

if N='1' then n_state <= s1;

elsif D='1' then n_state <= s2;

else n_state <= s0; end if; ..

Machine State

Registers

Next state

Present state Outputs

InputsOutputLogic

Next StateLogic

Reset

S2

S3

S1 D

open

S0

N

DN

N,D

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Example 24

Session Six 19

STEP IVVHDL CODE

- Next State Logic

when s1 => if N='1' then

n_state <= s2; elsif D='1' then

n_state <= s3; else

n_state <= s1; end if;

when s2 => if N='1' then

n_state <= s3; elsif D='1' then

n_state <= s3; else

n_state <= s2; end if;

when s3 => n_state <= s0;

end case; end process next_state;

Reset

S2

S3

S1 D

open

S0

N

DN

N,D

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Example 24

Session Six 20

STEP IVVHDL CODE

5- Output Logic

Responsible for generating Output

logic.

output_logic :process(p_state) begin case p_state is

when s0 => tank_open <='0';

when s1 => tank_open <='0';

when s2 => tank_open <='0';

when s3 => tank_open <='1';

end case; end process output_logic ; end Behavioral;

Machine State

Registers

Next state

Present state Outputs

InputsOutputLogic

Next StateLogic

Reset

S2

S3

S1 D

open

S0

N

DN

N,D

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Lab 07

Session Six 21

Title:Mealy Machine Vending Machine

Goal: Dealing with FSMs

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Lab 07

Session Six 22

String Detector

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity vend_machine_moore is Port (

N : in STD_LOGIC; D : in STD_LOGIC; reset : in STD_LOGIC; clk : in STD_LOGIC; tank_open : out STD_LOGIC);

end vend_machine_moore;

S2

S1 D, 0

S0

Reset

N, 0

N, 0

N/D, 1D, 1

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Lab 07

Session Six 23

String Detector

architecture Behavioral of vend_machine_moore is type states is (s0,s1,s2); signal n_state,p_state :states;

Begin ..

transition :process(clk,reset) begin

if reset='1' then p_state <=s0 ;

elsif rising_edge(clk) then p_state <= n_state ;

end if; end process transition;

S2

S1 D, 0

S0

Reset

N, 0

N, 0

N/D, 1D, 1

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Lab 07

Session Six 24

String Detectornext_state :process(N,D,p_state) begin case p_state is

when s0 => if N='1' then

tank_open <='0'; n_state <= s1;

elsif D='1' then n_state <= s2; tank_open <='0';

else n_state <= s0; tank_open <='0';

end if; when s1 =>

if N='1' then n_state <= s2; tank_open <='0';

elsif D='1' then …

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Lab 07

Session Six 25

String Detectorn_state <= s0; tank_open <='1';

else n_state <= s1; tank_open <='0';

end if; when s2 =>

if N='1' then n_state <= s0; tank_open <='1';

elsif D='1' then n_state <= s0; tank_open <='1';

else n_state <= s2; tank_open <='0';

end if; end case; end process next_state; end Behavioral;

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Exercise 08

Session Six 26

Draw Moore and Mealy State diagram for string detector that detect 1110 sequence

1 1 1 0

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Lab 08

Session Six 27

Title:String Detector State Machine

Goal: Dealing with FSMs

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Session Six 28

Start Notes [Synthesis Notes]

Modeling FSM

-FSMs Can Be Easily Described With Processes. Synthesis Tools understand FSMs if Certain Rules Are Followed. State transitions should be described in a process sensitive to clock and asynchronous reset signals only. Output function described using rules for comb. logic, concurrent statements or a process with all inputs in the sensitivity list.

One process describes state register. state transaction and output logic.Advantage : registered outputsDisadvantage : verbose syntax.

poorly debugging one clock latency for outputs

Two process the first describes state register. the second combinatorial logic.

Advantage : easy to debugging. simply and readable code.

Disadvantage : non registered outputs. needs assignment to next state and outputs for all possible cases.

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Session Six 29

Start Notes [Synthesis Notes]

Three processes one for state register. one for next state logicone for outputs

Advantage : easy to debugging. simply and readable code.

Disadvantage : non registered outputs. redundant code.

Three processes first for state register. second for next state logic third for synchronous outputs.

Advantage : fully synchronous. readable codeeasy for debugging.

• Disadvantage :one clock cycle latency for output assertion

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Summary

Session Six 30

- FSM is simply a finite number of states that each state describes a certain set of control outputs that are connected to the data part blocks.

Examples Exercises Labs

24 8 7-8

Machine State

Registers

Next state

Present state Outputs

InputsOutputLogic

Next StateLogic

Mealy machines

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Time for Your Questions

Session Six 31

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Take Your NotesPrint the slides and take your notes here

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See You Next Session .. Don’t miss

Thank

You