Service Manual FILE NO. R CONTENTS DVD Player DVD-1500 DVD-S1500 PRODUCT CODE No. 137 093 05 (AU) 137 093 04 (US) REFERENCE No. SM5810142 MIN MAX PHONE LEVEL PHONES PLAY PAUSE/STEP STOP f e k a n q OPEN/CLOSE z /ON STANDBY z/ON PICTURE MODE LAST MEMO OPEN/CLOSE q ON SCREEN SUBTITLE AUDIO SET UP RETURN REV FWD REV SLOW PAUSE/STEP STOP FWD SLOW PREV PLAY NEXT d c k n f a e CLEAR MENU TITLE ZOOM 1 2 3 C 4 5 6 7 8 9 0 PROGRAMSEARCH MODE ANGLE ANGLE REPLAY BOOKMARK REPEAT A-B REPEAT 4 5 ENT b a SPECIFICATIONS .................................................. 1 LASER BEAM SAFETY PRECAUTION .................. 1 MECHANISM REPLACEMENT .............................. 1 MECHANISM OPERATION .................................... 3 DVD P.W.BOARD OPERATION ............................. 4 CHECK FLOW AND TROUBLE SHOOTING ....... 9 TROUBLE SHOOTING (CHECK WAVEFORM) ... 16 TROUBLE SHOOTING (CHECK WAVEFORM) ... 33 TROUBLE SHOOTING (SCHEMATIC DIAGRAM FOR WAVEFORM CHECK) ................................ 34 TROUBLE SHOOTING (SCHEMATIC DIAGRAM FOR VOLTAGE CHECK) .................................... 46 MPEG P.W.BOARD OPERATION .......................... 48 CHECK WAVEFORM ........................................... 55 SCHEMATIC DIAGRAM FOR WAVEFORM CHECK ................................ 58 EXPLODED VIEW (CABINET & CHASSIS) .......... 60 EXPLODED VIEW (DVD MECHANISM) ............... 61 PARTS LIST ............................................................ 62 IC BLOCK DIAGRAM & DESCRIPTION ................. 70 WIRING CONNECTION ......................................... 79 SCHEMATIC DIAGRAM (DVD) ............................ 80 SCHEMATIC DIAGRAM (MPEG for AU) .............. 84 SCHEMATIC DIAGRAM (MPEG for US) .............. 88 SCHEMATIC DIAGRAM (FRONT for AU) ............ 92 SCHEMATIC DIAGRAM (FRONT for US) ............ 94 WIRING DIAGRAM (DVD A SIDE) ....................... 82 WIRING DIAGRAM (DVD B SIDE) ....................... 83 WIRING DIAGRAM (MPEG A SIDE for AU) ......... 86 WIRING DIAGRAM (MPEG B SIDE for AU) ......... 87 WIRING DIAGRAM (MPEG A SIDE for US) ......... 90 WIRING DIAGRAM (MPEG B SIDE for Us) .......... 91 WIRING DIAGRAM (FRONT,PHONE SOCKET, POWER SWITCH,TRAY LED, TRAY OPEN/CLOSE MOTOR, TRAY OPEN/CLOSE SWITCH) ............................ 96 WIRING DIAGRAM (AMP) ..................................... 97 VOLTAGE TABLE ................................................... 98 (AU) (US)
74
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Service Manual DVD Player DVD-1500 DVD-S1500(US)cncms.com.au/SANYO-SMs/Consumer-Electronics/DVD Player/dvd-1500/dvd-1500_sm 1-2.pdfdvd player dvd-1500 dvd-s1500 product code no. 137
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VOLTAGE TABLE ................................................... 98
(AU)
(US)
- 1 -
1.Cautionary instructions in handling the assy(Safety instructions)Optical pickupThe laser beam used in the pickup is classified as "class 2". Exposingyour eyes or skin to the beam is harmful. Take care not to do so.
(Caution against static electricity and leakage voltage)Ground securely the work tables, tools, fixtures, soldering irons(including those made of ceramic) and measuring instruments usedin the production lines and inspection departments that handleloaders. The workers shall also be grounded.
(Cautionary instructions in handling)Do not touch the object lens when handling a loader, or the lens willbe stained, resulting in inadequate playability.There is no power supply protection circuit provided for this productor adjustment/inspection device. Short-circuiting may lead to fire ordamage.Take care so as to protect from exposure to water, the entry ofmetallic pieces or dew condensation.In particular, a strong magnet adjacent to the pickup will not onlyget inoperative but can damage the pickup if a small metallic piece,such as a screw or swarm, enters.The loader edge can cause injury if inadvertently handled.Do not touch a rotating disk, or injury may result.
This product is a precision device. Handle carefully.A shock or dropping will cause misalignment or destruction. If itshould occur, refer to clause 2.This product is so designed as to endure an initial shock equivalentto a drop from a height of approx. 90 cm under the packed condition.After the initial shock, the resistivity will still remain at a level of 50to 60 G, but the mechanical robustness will weaken.Do not place in a dusty location.
LASER BEAM SAFETY PRECAUTION
MECHANISM REPLACEMENTThe entry and deposition of dirt into or on the pickup lens or movingsection will cause malfunction or degradation.
(Connectors)Do not connect or disconnect while power is on.Connecting or disconnecting signal wires or the main power cordwhen the power is on may destruct the unit or fixture.When connecting, push all the way in securely.An insufficient insertion may cause a bad contact, leading to anerroneous operation.Do not connect or disconnect roughly by an excessively strong force,or a broken wire or bad contact may result.Semiconductors are connected. Do not touch connector terminalsdirectly.If the worker is grounded, there is nothing to worry about staticelectricity, but the rust on the connector terminal surface caused bythe touch may result in bad contact.
(Power source)The power source need be good in quality (free from instantaneousinterruptions or noises).A low quality power source may well cause malfunction.
(Storage)Do not place or store in a dusty place or a place where dewcondensation is possible.The entry and deposition of dirt or dust into or on the pickup lens ormoving section will cause malfunction or degradation.Also, dew condensation causes rust;the rust penetrate into theprecision part of a pickup, causing malfunction, or degrading theoptical quality of the internal lens and reflector, which also leads tomalfunction.
SPECIFICATIONSType ........................................ DVD player
Signal format ........................... NTSC or PAL color
CAUTION – INVISIBLE LASER RADIATION WHEN OPEN ANDINTERLOCKS DEFEATED. AVOID EXPOSURE TO BEAM.ADVARSEL – USYNLIG LASER STRÅLING VED ÅBNING, NÅRSIKKERHEDSAFBRYDERE ER UDE AF FUNKTION, UNDGÅ UDS ÆTTELSEFOR STRÅLING.VARNING – OSYNLIG LASER STRÅLNING NÄR DENNA DEL ÄR ÖPPNADOCH SPÄRR ÄR URKOPPLAD. STRÅLEN ÄR FARLIG.VORSICHT – UNSICHTBARE LASERSTRAHLUNG TRITT AUS, WENNDECKEL GEÖFFNET UND WENN SICHERHEITSVERRIEGELUNGÜBERBRÜCKT IST. NICHT, DEM STRAHL AUSSETZEN.VARO – AVATTAESSA JA SUOJALUKITUS OHITETTAESSA OLET ALTTIINANÄKYMÄTTÖMÄLLE LASERSÄTEILYLLE. ÄLÄ KATSO SÄTEESEEN.
(AU)
- 2 -
MECHANISM REPLACEMENT
FLOIL OILG-474B
FLOIL OILG-2000B
FLOIL OILG-2000B
Don't disassemble part ① because of difficulty ofadjustment.
MOLYKOTEEM-50L
MOLYKOTEEM-50L
MOLYKOTEEM-50L
MOLYKOTEEM-50L
SILICON GREASEKS-64
4. TRAY PART
MOLYKOTEEM-50L
GREASECDF-409
GREASCDF-40
5. BASE MECHANISM PART
Slide the switch as an arrow markwhen removing pick up.
1. PICK UP P.W.B PART
2. TRAY AND BASE MECHANISM PART
3. Base mechanism mounting PART
1
- 3 -
MECHANISM OPERATION
SHASSISFRONT SIDE
MOTOR
MARKER
MARKER
2
1
2
3
3
1.How to setting the tray. 1. The GEAR 1 move from side to side.
2. Match the mark of GEAR 2 and mark of GEAR 3,
and then install the BOSS.
3. Turn the GEAR 1 counterclockwise, and then SLIDE
move right side.
RIB
RIB GREASEEM-50L
GREASEEM-50L
GREASEEM-50L
LARGE TOOTH
GEAR HO
CHASSIS HOLE5
4
LOARDINGGEAR
MARKER
MARKER
TRAY
HOLE6
7
8
9
4. Move the SLIDE left side.
5. Match the Hole of GEAR 5 and Hole of CHASSIS 4.
6. Match the hole of GEAR 7 and hole of chassis while turning
GEAR 6.
7. Match the mark of LOADING GEAR 8 and gear of TRAY
where see horn hole 9 of tray.
8.Push a tray with the state that turned the entire surface of a
tray into approximately 5 degrees the lower part slowly.
- 4 -
General operation diagram
PC
K U
P
SP
IND
LEM
OT
OR
SLE
DM
OT
OR
LOA
DIN
GM
OT
OR
Mec
hani
sm S
W (
OP
EN
, CLO
SE
, The
inte
rnal
circ
umfe
renc
eLIM
IT)
MLD
1, 2
SLD
1, 2
F0±
, TR±
LCD
1, L
CD
2
LD, M
D, V
R, H
FM
A, B
, C, D
, E, F
VC
C, V
C, G
ND
AC
T.
I / V LD
RFA
MP
Spi
ndle
DR
V.
4ch
DR
V.
IC50
1TA
1254
AF
IC60
2B
A68
49
IC60
1B
A59
31
5V
VR
2VR
2.1V
4.2V
9V 9V
AM
P
AM
P
FO
O, T
RO
, FM
O
DV
R2.
1 / 1
.65
LD1,
LD
2
EQ
B, E
QF
(E
qual
izer
Aju
st.)
TE
, RP
O, R
PZ
, LV
LR
F (
CD
)
DM
O_C
DIC
701
TC
9461
F
16.9
MH
z5V
5V
IC80
1T
C90
A41
F
27 M
Hz
3.3V
Ser
vo, D
SP
CD
deco
der
DV
Dde
code
r
RF
(D
VD
)
DV
R
PW
M O
ut
DV
O_D
VD
MIC
OM
FLA
SH
ME
MO
RY
VC
D16
.9 M
Hz
384
Fs
HR
ST
from
BA
CK
EN
D
from
BA
CK
EN
D
FE
SC
D, S
CL,
SC
B, *
FR
ST,
C
D/*
DV
D, D
PC
TL,
LC
SW
DV
D/*
CD
, *F
RS
T,
SP
DL-
FG
IC80
2T
C68
15
*C
S3,
(*
CS
2), *
SW
R,
*IN
TD
EC
,*R
D, *
FR
ST,
(*
RD
Y),
(B
CLK
),D
0 -
D1,
A0
- A1
FLG
A, F
LGB
, FLG
C, F
LGD
, *C
CE
, B
UC
K, B
US
0, B
US
1, B
US
2, B
US
3,
*F
RS
T(*
RS
T),
SLD
-LK
, SB
OK
, S
BS
Y, S
LD-L
OC
K
*R
OM
, *R
DD
0 -
D7,
A0
- A11
DVD P.W.BOARD OPERATION
This is a basic explanation.
- 5 -
FOCUS DRV.IC601 25pin
FETP513
TETP512
SLEDIC601 20pin
VRA
① ⑤③②
④
⑥
The orientation that optical lens
DiskDistinction
FServoCLV ON
pick return play (If there is pick in perimeter of a circle, there is it, and time of bottom gets longer)
TServo ON
(Actuating description)
1. After turning on the power or inserting a disk, this DVD Assy starts to perform a disk identification operation.1) Sets the circuit to the DVD mode, returns the pickup, lowers the lens an lights the LASER lamp.
The pickup return, lens operation and LASER lamp illumination are visuall recognizable.(spindle kick)
2) In PU mode (CD), raises the lens.
Focus level measurement (A), judges the FE pulse whether to be 1 or 2.
3) In PU mode (DVD), lowers the lens.
Focus level measurement (B).
4) Judgment pulse 2 : DVD two-layer disk,
(B)/(A)>1.5 : DVD one-layer disc.
Other than the above condition : CD
5) Sets the circuit to the PU mode (based on the above disk judgment, the circuit is set to the PU mode)
6) Servo attracting operation (servo turns on):CLV turns on in the same way as a CD player.
CD
DVD
one-layer
disk
DVD
two- layer
disk
Two Focus err.
DVD P.W.BOARD OPERATION
level difference
Disc distinction
Disc distinction
Disc distinction
Disc distinction
Disc distinction
Zoom
Disc distinction
Focus point
Don’t Servo on
Servo on
Focus error signal(lens distant→near)
Image
- 6 -
FOCUS DRV.IC601 25pin
FETP513
TETP512
SLEDIC601 20pin
VRA
DiskDistinction
ServoAdjust.��
Inner From Exter From inner
Data read
ServoAdjust.Exter
INITAttention
Fsearch
2. Automatic servo alignmentContents of the servo alignment and the alignment method
1) Tracking balance
2) Focus balance
3) Focus gain
4) Tracking gain
5) RF gain
Set by the command the micon, reading the correction value of the TC9461, gives to the TA1254.
6) RF equalizer (DVD only)
The micon, monitoring the error rate (TC90A41), sets a PWM data (TC90A41) and provides a voltage for the TA1254.
Performed automatically by the TC9461 based on the command
given by the micon (microcomputer)
to PU Equalize voltage
to P
U
Micon I / F
DVD : PLCK (27MHz)CD : BCK (1.4MHz)
DVD : TC90A41FCD : TC9461F
TC9461F
TC90A41F Micon Setting
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
VCKF
VccP
LVL
TEO
FEO
DFTN
VssS
RPZ
RPO
RPB
RPP
RFO
NC
NC
VccR
DPDB
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
P2FN
P2FP
GNDS
P2DI
P2CI
P2BI
P2AI
LDP2
GNDR
P1AI
P1BI
P1CI
P1DI
LDP1
P1FP
P1FN
TE
B
FE
B
PS
C
Vcc
2
NC
EQ
D
GN
D2
RF
DC
RFA
EQ
B
EQ
F
MD
I1
LD
O1
P1
TN
P1
TP
NC
VR
CK
SC
D
SC
L
SC
B
DP
D2
DP
D1
DP
BD
DPA
C
Vd
d
VrD
VrA
MD
I2
LD
O2
P2
TN
P2
TP
GN
D
F-gainAdjustment
F-gainAdjustment
T-gainAdjustment
R-gainAdjustment
TE-gainAdjustment
FTE-gainAdjustment
LevelDetection
BUSTime
ConstantAdjustmentAPC2
APC1
3BTEGeneration
DPDTEGeneration
FEGeneration
RF RippleGeneration
EQ
sel-DPD
sel-LVL
sel-FE
sel-PD
sel-RF
sel-TE
mode-IC
mode-TE
DVD P.W.BOARD OPERATION
An automatic alignment method (e.g.
automatic alignment sequence) varies with
the version of the micon. In any case, it is
important to recognize that the above-
mentioned alignments are conducted
regardless of the version.
Amp mode setting
focus gain: F-gain, FE-gain
tracking gain : T-gain, TE-gain
RF gain : R-gain
TE : mode-TE (DPD or 3beam)
- 7 -
3. Data reading(1) The SLED control is performed by the control output "FMO" (TC9461, pin 48), which reaches the IC601 via the
IC605 and drives the SLED motor.
(2)The SPINDLE control is performed by the control output "DMO CD" (TC9461) in the case of a CD, and "DMO DVD" (TC90A41AF)
in the case of a DVD, which reaches the IC602 via the IC605, whose reference voltage is set by the DVD/CD* of the micon,
and drives the SPINDLE motor (brushless motor).
The reference voltage is 1.65 V for a DVD, and 2.1 V for a CD.
(3) The PLL control is conducted by the TC9461 for a CD, and by the TC90A41AF for a DVD.
(4) An output is in accordance with the respective disks.
CD :TC9461 serial data (BCK, CDDATA, LRCK, C2PO) output (CN802)
DVD:TC9461 serial data (BCK, CDDATA, LRCK, C2PO) and this are inputted into the ROM decoder (IC802), converted to the
MPEG decoder signals (parallel data) and then outputted (CN801).
DVD:TC90A41AF MPEG data:parallel signals (SD0-7, SERR, SBGN, SENB, SDCK and SREQ) are inputted into the ROM
decoder (IC802), decode the digital copy protection and are converted to the MPEG decoder signals (parallel data)
and then outputted (CN801).
DVD P.W.BOARD OPERATION
- 8 -
Depress open/close switch.
Place a disk on tray.
Tray close/closed
Tray opens.
"LASER" lights.
Lowers lens (approx. 400 ms).
Pickup returns.
INIT processing of TC9461 Laser off 20 ms
Lowers lens
Rotates SPINDLE at a speed of twice that of CD.
Waits for prescribed number of rotations to be completed. Checks FG.
STOP
YESNO
DVDCD
(b)/(a)>1.5
FE pulses;one or two
One-layer DVD
Sets one-layer DVD circuit to pickup mode.
Sets two-layer DVD circuit to pickup mode
Sets CD circuit to pickup mode.
YES
NO
2
1
DVD/CD
DVD
CD
Measures error rate
Error judgementOK
NG
OK
OK
OK
OK
NG
NG
NG
NG
CD
CD/DVD
Optimization
CDDVD
Turn on power.
Depress open/close switch.
Two-layer DVD
Laser on.DVD/CD
Aligns tracking balance
Error judgement
EQB
Error judgement
EQF
Error judgement
Error judgement
Aligns tracking balance
TIME OUT:ERR.
Raises lens.
FOCUS OK?
SPINDLE motor turns on.
8/12 cm identification.FG confirmation
Rotates at a speed of approx. 0.7 time that of CD
Waits for approx. 500 ms.
New disk?
Layer jump
Old
New
Tracking balance alignment
Rotates at a speed of twice that of CD.
Waits for 100 ms.
Lowers lens with each IC in DVD mode
Measures FE level (a)
FE pulse 1 or 2
Lowers lens with in LCD and DVD mode
Rotates at a speed of two times that of CD
Measures FE level (a)
TRACKING ON SLED OFF
Sets to normal speed.
ADDRESS CHECK
200ms wait
Focus balance alignment
Focus gain alignment
Tracking gain alignment
SLED ON
RF gain alignment
100ms wait
One-layer or two-layer
Two-layer completedOne-layer
Two-layer completed
Measures poor playability varlue
READ-IN playCD : TOC READ
DVD : CSS processing
Pickup moves outward.
Optimization Wait to PLAYBACK
DVD P.W.BOARD OPERATION(GENERAL FLOW) This is a basic flowchart.
- 9 -
CHECK FLOW AND TROUBLE SHOOTING
(Power on)
Power onProblem/symptom Check Waveform Schematic diagram Reference data
CN803 (PH5P)1 Cannot be energised Check for a voltage of 5 V/9 V.
Check for the HRST. (17)(19) KTurn off power at once. Check SPINDLE/SLED servo system. BA6849 voltage table (4)
2 SPINDLE motor runs away. Check for FLOW signal. (44)(45) A , BCheck and trace control signals. (46) A , BTurn off power at once. Check SPINDLE/SLED servo system.
3 SLED motor runs away. Check for FLOW signal. I BA5931 voltage table (5)Check and trace control signals. (47)(48)
(Tray open / close)
Tray open/closeProblem/symptom Check Waveform Schematic diagram Reference data
Check for motor drive input/output. (1) J BA5931 voltage table (6)1 Neither opens nor closes Check mechanical switch & its output. (16) J
Check for HRST & FRST. (18)(19) J2 Opens but immediately closes. Check for motor drive input/output. (1) J BA5931 voltage table (6)
Check mechanical switch & its output. (16) J3 Opens but motor does not stop.Check for motor drive input/output. (1) J BA5931 voltage table (6)
Check mechanical switch & its output. (16) J4 Loading speed abnormal Check for motor drive input/output. (1) J BA5931 voltage table (3)
An extract from "GENERAL FLOW" An extract from "GENERAL FLOW"
Turn on power.
Tray close/closed
"LASER" lights. Pickup returns.
8/12 cm identification
Identifies disk Sets mode
INIT processing of TC9461 Laser off 20 ms
Laser on. Focus search
Automatic alignmentTracking balanceFocus balance
Focus gainTracking gain
RF gain
Check for connector and power source.
Turn on power.
Tray close/closed
"LASER" lights. Pickup returns.
8/12 cm identification
Identifies disk Sets mode
NIT processing of TC9461 Laser off 20 ms
Laser on. Focus search
Depress open/close switch.
Tray opens.
Place a disk on tray.
Depress open/close switch.
Tray open/close
- 10 -
LASER ON/ 8/12 cm identificationProblem/symptom Check Waveform Schematic diagram Reference data
Check LASER ON timing and drive transistor voltage. (18)(19)Check VCC2 at pin 36 of IC501 TA1254. LCheck for short-circuiting of LASER (excessive current [R5100], though protected by fixture)
1 "LASER" does not light. Check for LASER destruction. If so, check LASER current (R5100).Check micon interface (SCB, SCL & SCD) TA1254 voltage Check FRST (LASER to be active at LOW). table (2)Check signal FLOW. (28) ~ (31) LCheck and trace control signals. L
2 No pickup return operation. Check SLED voltage and timing. Check limit switch. (35) ~ (37) I , I'3 Disk does not rotate. Check SPINDLE voltage and timing. (44) ~ (46) A , B Voltage table (4)
Check SPINDLE voltage and timing. (44) ~ (46) A , B Voltage table (4)4 Disk rotates at a high speed. Check SPDL FO.
Turn off power at once.Check SPINDLE/SLED servo system.
(LASER ON/ 8/12 cm identification)
Laser focus search after initial processing.Problem/symptom Check Waveform Schematic diagram Reference data
1 Disk error due to erroneous Check disk identifying waveform in LASER mode. 2,(34) ~ (38) Fdisk identification (28) ~ (31) L
2 Focus servo inactive Check waveforms up to “focus ok" with each disk. (34)(35)(37)(38) FCheck pin 43 of IC701 TC9461. 2,(36)Check DFTN. (40) ~ (43)DFTN:normally High, at SCRATCH:Low C,D,EData output normal? CN801/IC802 C,D,E
3 Disk unreadable Check DVD/*CD signal (CD/*DVD). Voltage table DVD:High, CD:Low (44) ~ (46) (8)(IC900 pin 1, IC501 pin 35, Q6001 base)Check SEL signal (must be High when laser is on). (28) ~ (31) L
(Laser focus search after initial processing.)CHECK FLOW AND TROUBLE SHOOTING
An extract from "GENERAL FLOW" An extract from "GENERAL FLOW"
Disk identification/mode settingProblem/symptom Check Waveform Schematic diagram Reference data
Check that disk identification is correct. 2 FNot focusable Check that FOO waveform is normal or smooth.
1 (disk error) Error 21 Check that peak value of detection pulse (S curve) is correct. (34) ~ (38)Check that lens up/down operation is normal.Check that lens is free from dirt or stain.
2 Not focusable Check LASER current (R5100). F(disk error) Error 21 Compare it with that indicated close to pickup's serial number.
3 No focus search FLGC TP716 (IC900 80pin) F4 No focus search Check RFO (IC501 pin 28). (2) ~ (4) F
Wrong ROM5 Inactive Check LCSW Voltage tables
Repair CD/*DVD (DVD/*CD). (7) & (8)
(Disk identification/mode setting)
CHECK FLOW AND TROUBLE SHOOTINGAn extract from "GENERAL FLOW"
Automatic alignment blockProblem/symptom Check Waveform Schematic diagramReference data Focus unstable focus servo system. (24)~(27) F
1 Susceptable to shock Check for signal flow Oscillatory noise from pickup Check for signal flow Squeaky noise while pickup is travelling If not rotating with board, pickup need be analyzed.Excessively long time taken for alignment tracking servo system. (20)~(23) G, H
2 Susceptable to shock Check for signal flow Oscillatory noise from pickup Check for signal flow Squeaky noise while pickup is travelling If not rotating with board,pickup need be analyzed.
Playing CDProblem/symptom Check Waveform Schematic diagram Reference data
1 Unplayable (no sound, no picture) Is output signal around? (5)~(10) D,E2 Sound skipped Check waveform. (11)~(15),(33) D,E3 No or intermittent sound Is spindle motor waveform normal? 1,(5)~(10) D,E4 No sound Check DATA. (4)~(6) D,E
Poor playability Check RF waveform (any difference from that of good unit) (2)~(4) D,ESurface shaking, warp Realignment of mechanism (11)~(15)Scratch Check DFTN (40)~(43) D,E,H TA1254
DVD 48kHz fs384fs 18.4344MHzBCLK 3.07MHz(64fs)LRCLK 48.0kHz
DVD 96kHz fsS384fs 36.864MHzBCLK 6.14MHz(64fs)LRCLK 96.0kHz
7
- 57 -
MPEG P.W.BOARD CHECK WAVEFORM
8 9
1011
12
- 60 -
EXPLODED VIEW (CABINET & CHASSIS)
52
11Y04
Y04
1
4
2
3
6
71
72
8
9
12
13
14
16
51
74
75
76
77
17
18
15
5
Y04
Y04
Y04
Y04
Y04
7
Y05Y06
Y07
Y07
Y06
Y06
Y07
Y07
Y08
Y12
Y10
Y10Y10
Y09
Y09
Y13Y14
Y14
Y09
Y09
Y06
Y01
Y01
Y01
Y02
Y02
Y02Y02
Y03
Y03
Y05
7310
19
20
- 61 -
EXPLODED VIEW (DVD MECHANISM)
DM01
DM02
DM04
DM03
DM04
DM05
DM06
DM07
DM14DM09
DM08
DM10
DM11
DM12
DM22
DM23
DM13
DM15DM16
DM17DM18
DM19
DM20
DM44
DM45
DM45
DM42
DM37
DM42
DM42
DM42
DM26DM27DM34DM35
DM31
DM30
DM41DM40
DM39DM38 DM33
DM29
DM25DM34DM28
DM24
DM21DM46
- 62 -
PARTS LISTPRODUCT SAFETY NOTICE
EACH PRECAUTION IN THIS MANUAL SHOULD BE FOLLOWED DURING SERVICING. COMPONENTS IDENTIFIED WITH THE IECSYMBOL !!! IN THE PARTS LIST AND THE SCHEMATIC DIAGRAM DESIGNATED COMPONENTS IN WHICH SAFETY CAN BE OFSPECIAL SIGNIFICANCE. WHEN REPLACING A COMPONENT IDENTIFIED BY !!! , USE ONLY THE REPLACEMENT PARTS DESIGNATED,OR PARTS WITH THE SAME RATINGS OF RESISTANCE, WATTAGE OR VOLTAGE THAT ARE DESIGNATED IN THE PARTS LISTIN THIS MANUAL. LEAKAGE-CURRENT OR RESISTANCE MEASUREMENTS MUST BE MADE TO DETERMINE THAT EXPOSEDPARTS ARE ACCEPTABLY INSULATED FROM THE SUPPLY CIRCUIT BEFORE RETURNING THE PRODUCT TO THE CUSTOMER.
CAUTION : Regular type resistors and capacitors are not listed. To know those values, refer to the schematic diagram.Regular type resistors are less than 1/4 W carbon type and 0 ohm chip resistors.Regular type capacitors are less than 50 V and less than 1000 µF type of Ceramic type and Electrical type.
IC BLOCK DIAGRAM & DESCRIPTIONIC002 ADV7172KST(PAL and NTSC square pixel operation)
POWERMANAGEMENT
CONTROL(SLEEP MODE)
CGMS & WSSINSERTION
BLOCK
TELETEXTINSERTION
BLOCK
4:2:2 TO4:4:4
INTER-POLATOR
YCrCbTO
YUVMATRIX
ADDSYNC
INTER-POLATOR
INTER-POLATOR
ADDBURST
PROGRAMMABLELUMINANCE
FILTER
PROGRAMMABLECHROMINANCE
FILTER
VIDEO TIMINGGENERATOR
I C MPU PORT2REAL-TIMECONTROLCIRCUIT
SIN/COSDDS BLOCK
VOLTAGEREFERENCE
CIRCUIT
10-BITDAC
10-BITDAC
10-BITDAC
10-BITDAC
YUV TORBG
MATRIX
MULTIPLEXER
UU 10
10
10 10
10
10
10
1010
10
10
10
VV
88 9
8
8
9
88 8
88 8
44 23 24 18 35
32
31
26
27
3736
22
16
15
17 34
33
25
Y
1,11,20,28,30
4-243-38
14-129-5
10,19,29,43
Vss
CLOCKDATAP7-P0
P15-P8
RESET
HSYNC
FIELD/VSYNC
BLANK
CLOCK SCLOCK SDATA ALSB SCRESET/RTC GND
COMP
DAC A(PIN 32)
GAC B(PIN 31)
DAC C(PIN 26)
DAC D(PIN 27)
RSET
VREF
TTXREQ TTX
IC003 BA7660FS(3 CHANNEL 75 OHM DRIVER)
1
2
3
4
5
6
7
8
MUTE
INA
GND
INB
GND
N.C.
INC
GND
VCC
OUTA1
OUTA2
OUTB1
OUTB2
N.C.
OUTC1
OUTC2
16
15
14
13
12
11
10
9
6dB 75Ω
6dB 75Ω
6dB 75Ω
IC015 MC74H174AD(HEX D-TYPE FLIP-FLOP)
1
2
3
4
5
6
7
8
RESET
Q0
D0
D1
Q1
D2
Q2
GND
VCC
Q5
D5
D4
Q4
D3
Q3
CLOCK
16
15
14
13
12
11
10
9
Inputs Output
Reset
L
H
H
H
H
D
X
H
L
X
X
Q
L
H
L
No Change
No Chenge
Clock
X
L
IC101 24LC16B/P (16K EEPROM)
Name FunctionVSS
SDASCLWPVCC
A0,A1,A2
GroundSerial Address/Data I/OSerial ClockWrite Protect Input+2.5V to 5.5V Power SupplyNo Internal Connection
4
3
2
1
5
6
7
8
SDA
SCL
WP
VCC
VSS
A2
A1
A0 24LC
16B
IC115 PCM1723(D/A CONVERTER)
No. Name I/O DESCRIPTION1 XT1 - 27 MHz x'tal oscillate input or external oscillator2 SCKO O System clock output3 VCP - PLL power source4 NC - N.C5 MCKO O Master clock buffer output6 ML I Software control latch7 MC I Software control clock8 MD I Software control data9 RSTB I Reset10 ZERO O Zero data flag output11 VOUTR O Rch. Analogue power output12 GNDA - Analogue ground13 VCA - Analogue power source +5V14 VOUTL O Lch. Analogue power output15 CAP - Output amplifier common16 BCKIN I Bit clock input for data17 DIN I Data input18 LRCIN I Basic sampling clock input19 NC - N.C20 RSV - N.C21 VDD - Digital power source 5V22 GNDD - Digital ground23 GNDP - PLL ground24 XTO - Crystal oscillator
IC117 T2316162A-45J(1024 x 16 DRAM)
1 2 3 4 5 6 7 8 9 10 11 12 13 14
42 41 40 39 38 37 36 35 34 33 32 31 30 29
VS
S
DQ
15D
Q14
DQ
13D
Q12
DQ
11D
Q10
DQ
9D
Q8
OE
CA
SL
CA
SH
VS
S
VC
C
DQ
0D
Q1
DQ
2
DQ
4D
Q5
DQ
6D
Q7
DQ
3
NC
NC
WE
VC
C
15 16 17 18 19 20 21
28 27 26 25 24 23 22
NC
A7
A8
A9
A6
A5
A4
VS
S
RA
S A0
NC
NC A1
A2
A3
VC
C
SYM. TYPE DESCRIPTION
Address Input
Row Address Strobe
Column Address Stlobe /Upper Byte Control
Column Address Stlobe /Lower Byte Control
Write Enable
Output Enable
Data Input /Output
Power, 5V
Ground
No Connec
A0~A9
RAS
CASH
CASL
WE
OE
DQ0~DQ15
VCC
VSS
NC
Input
Input
Input
Input
Input
Input
Input/Output
Supply
Ground
-
- 71 -
IC110 KM416S1120DT(1Mx16BIT CMOS DRAM)
1 2 3 4 5 6 7 8 9 10 11 12 13 14
50 49 48 47 46 45 44 43 42 41 40 39 38 37
VS
S
DQ
15D
Q14
DQ
13D
Q12
DQ
11D
Q10
DQ
9D
Q85
N.C
/RF
U
VD
D
DQ
0D
Q1
VS
SQ
DQ
2D
Q3
VD
DQ
DQ
4D
Q5
VS
SQ
DQ
6D
Q7
VD
DQ
LDQ
M15 16 17 18 19 20 21 22 23 24 25
36 35 34 33 32 31 30 29 28 27 26
UD
QM
CLK
CK
EN
.CA
9A
8A
7A
6A
5A
4V
SS
VS
SQ
VS
SQ
VD
DQ
VD
DQ
WE
CA
SR
AS
CS
BA
A10
/AP A0
A1
A2
A3
VD
D
Pin Name Input Function
CLK System Clock Active on the positive going edge to sample all inputs.
CS Chip SelectDisables or enable device operation by masking or enabling all inputs exceptCLK,CKE and L(U)DQM
CKE Clock EnableMasks system clock to freeze operation from the next clock cycle.CKE should be enabled at least ono cycle prior to new command.Disable input buffers for power down in standby.
A0~A10/AP AddressRow / column addresses are multiplexed on the same pins.Row address : RA0~RA10, column address : CA0~CA7
BA Bank Select AddressSelects bank to be actiaeted during row address latch time.Selects bank for read/write during column address latch time.
RAS Row Address StrobeLatches row addresses no the positive going edge of the CLK with RAS low.Enables row access & precharge.
CAS Column Address StrobeLatches column addresses on the positive going edge of the CLK with CAS low.Enables column access.
WE Write EnableEnables write operation and row precharge.Latches data in standing from CAS, WE active.
L(U)DQM Data Input/Output MaskMakes data output Hi-Z, tSHZ after the clock and masks the output.Blocks data input when L(U)DQM ctive.
DQ0~15 Data Input/Output Data inputs/outputs are multiplexed on the same pins.
VDD/VSS Power Supply/Ground Power and ground for the input buffers and the core logic.
VDDQ/VSSQ Data Output Power/GroundIsolated power supply and ground for the output buffers to probide improved noiseimmunity.
N.C/RFUNo Connection/Reserved for Future Use This pin is recommended to be left No Connection on the device.
IC BLOCK DIAGRAM & DESCRIPTION
IC480 SI-3050C(DC REGULATER)
1
2
3
4
5
1. GND2. VC(on/off)3. Vo4. Vosense5. VIN
IC490 STR-G6651(SWITCH REGULATER)
4
1
2
5
3
START O.V.P LATCH
O.S.C
DRIVE
REG.
T.S.D
+
+
-
-
Comp.2
Comp.1
Vth(2)
Vth(1)
VIN
D
S
O.C.P/F
GND
Pin No. Sym. Description Function
1
2
3
Drain terminal
Source terminal
Ground terminal
Overcurrent/Feedbackterminal
Overvoltage protectioncircuit
Thermal shutdowncircuit
MOS FET drain
MOS FET source
Ground
Input of overcurrent detection signaland constant voltage control signal
Overvoltage protection circuit
Terminal shutdown circuit
D
S
GND
O.C.P/F.B
O.V.P
T.S.D.
5
4Input of power supply for controlcircuit
VIN
-
-
Power Supply terminal
IC710 TC7SHU04FU(INVERTER)
4
2
1 5 VCC
GND
IN A
NC
OUT Y3
- 72 -
IC116 HD6437043E00F(MICON)
PA23/WRHHPE14/IOC/DACK0/AH
PA22/WRHLPA21/CASHH
PE15/TIOC4D/DACK1/IRQOUTVcc
PC0/A0PC1/A1PC2/A2PC3/A3PC4/A4
VccPC5/A5
VssPC6/A6PC7/A7PC8/A8PC9/A9
PC10/A10PC11/A11PC12/A12PC13/A13PC14/A14PC15/A15
PB0/A16Vcc
PB1/A17Vss
PA20/CASHLPA19/BACK/DRAK1
PB2/IRQ0/POE0/RASPB3/IRQ1/POE1/CASL
PA18/BREQ/DRAK0PB4/IRQ2/POE2/CASH
VssPB5/IRQ3/POE3/RDWR
PES Vpp*2PA15/CKPLLVSSPLLCAPPLLVCCMD0MD1PA17/WAITPA16/AHVcc/(FWP)*1NMIMD2EXTALMD3XTALVssPD0/D0PD1/D1PD2/D2PD3/D3PD4/D4VssPD5/D5VccPD6/D6PD7/D7PD8/D8PD9/D9PD10/D10VssPD11/D11VccPD12/D12PD13/D13PD14/D14PD15/D15
IC BLOCK DIAGRAM & DESCRIPTIONIC601 BA5931FP(POWER DROVER)
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 36 25 24 23 22 21 20 19 18 17 16 14
+
+
+
-
-
+-
-
D
D D
x2D
x2
x2 x2D Dx2 x2
Dx2
Dx2
LEVELSHIFT
LEVELSHIFT LEVEL
SHIFT
VCCVCC
FWD REV
LOGIC
VOLTAGECTRL
PIN NO. NAME DESCRIPTION PIN NO. NAME DESCRIPTION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
DRIVER CH1 (-)
DRIVER CH1 (+)
DRIVER CH1
DRIVER CH1 GAIN
NOT USED
NOT USED
NOT USED
GND
NOT USED
NOT USED
NOT USED
DRIVER CH2 LOARDING (+)
DRIVER CH2 LOARDING (-)
SUB STRAIGHT GND
LOARDING REV
LOARDING FWD
DRIVER CH3 (-)
DRIVER CH3 (+)
LOARDING
DRIVER CH3
VCC
VCC
BIAS
DRIVER CH4 GAIN
DRIVE CH4
DRIVER CH4 (+)
DRIVER CH4 (-)
SUB STRAIGHT GND
OUT-1
OUT-2
IN 1-1
IN 1-2
NC
NC
NC
GND
NC
NC
NC
OUT2-1
OUT2-2
GND
REV
FWD
OUT3-1
OUT3-2
LD IN
IN 3
VCC
VCC
Vref IN
IN 4-2
IN 4-1
OUT4-2
OUT4-1
GND
IC602 BA6849FP(TREE-PHASE MOTOR DRIVER)
A3
RNF
VM1
VM2
VCC
FG
PS
EC
ECR
FR
SB
CNF
VH
A2
A1
GND
H1+
H1-
H2+
H2-
H3+
H3-
2
28
27
26
25
24
23
22
21
20
18
17
15
4
7
8
9
10
11
12
13
14
+
-
+
-
+
-
+
-
+ -
+
-
+
-
DRIVER
GAINCONTROL
TSD
TL
PS
SHORT BRAKE
Hall bias
D R Q
QCK
VCC
VCC
HALL AMPTORQUE
SENSE AMP
CURRENTSENSE AMP
IC503, 606 BU4066BCF(QUAD ANALOG SWITCH)
1 2 3 4 5 6 7
14 13 12 11 10 9 8
VDD C1 C4 I/O4 I/O3O/I4 O/I3
I/O1 O/I1 O/I2 I/O2 VSSC2 C3
IC635 BH3540AFS(HAEDPHONE AMP)
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
MUTE1
MUTE2
AMP
BIAS TSD
BUFF EVR POW
AMP BUFF EVR POW
+-
+-
EVRCONT
BIA
S
IN1
MU
TE
1
LIN
E1
VC
NC
PO
1
VC
C
GN
D
IN2
MU
TE
2
LIN
E2
NC
NC
PO
2
PG
ND
IC891 LE28F4001EN-90(4M BIT FLASH MEMORY)
1 32 31 30234
5
6
7
8
9
10
11
12
13
14 15 16 17 18 19 20
21
22
23
24
25
26
27
28
29
DQ7
CE
A10
OE
A11
A9
A8
A13
A14
A1
7
WE
AC
C
A1
8
A1
6
A1
5
A1
2
DQ0
DQ
1
DQ
2
VS
S
DQ
3
DQ
4
DQ
5
DQ
6
A0
A1
A2
A3
A4
A5
A6
A7
PIN NAME DESCRIPTION
ADDRESS INPUT
DATA INPUT/OUTPUT
CHIP ENABLE
OUTPUT ENABLE
WRITE ENABLE
GND
POWER SOURCE
A0~A1X
DQ0~DQ7
CE
OE
WE
VSS
VCC
IC803 KM48C512DT-L6(512K x 8BIT DRAM)
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VS
S
DQ
7D
Q6
DQ
5D
Q4
CA
SO
EN
.CA
8A
7A
6A
5A
4V
SS
VC
C
DQ
0D
Q1
DQ
2D
Q3
N.C W
RA
S A9
A0
A1
A2
A3
VC
C
Pin Name Pin Function
Address Inputs
Data In/Out
Ground
Row Address Strobe
Column Address Strobe
Read/Write Input
Data Output Enable
Power(+5V)
Power(+3.3V)
No Connection
A0~A9
DQ0~DQ7
VSS
RAS
CAS
W
OE
N.C
VCC
(TSOP-II)
- 75 -
IC BLOCK DIAGRAM & DESCRIPTION
No. Name I/O DESCRIPTION No. Name I/O DESCRIPTION1 VSS - Digital ground 51 2VREF - Analogue reference power2 BCK O Bit clock(1.4122MHz) output 52 SEL O APC circuit on/off signal output3 AOUT O Audio data output 53 FLGA O External flag of internal signal monitor output4 DOUT O Digital output 54 FLGB O External flag of internal signal monitor output5 MBOV O Buffer memory over signal output 55 FLGC O External flag of internal signal monitor output6 IPF O Correction flag output 56 FKGD O External flag of internal signal monitor output7 SBOK O CRCC judgement result of subcode "Q" data output 57 VDD - Digital pulse power source8 CLCK I/O Clock output for subcode "P"~"W" data read 58 VSS - Digital ground9 VDD - Digital power plus source. 59 IOO I/O General purpose I/O port10 VSS - Digital ground. 60 IO1 I/O General purpose I/O port11 DATA O Subcode "P"~"W" data output. 61 IO2 I/O General purpose I/O port12 SFSY O Frame synchronism signal output by play. 62 IO3 I/O General purpose I/O port13 SBSY O Subcode block synchronism output 63 /DMOUT I Mode setting for IO0,1,2,314 SPCK O Clock output for process status signal read 64 /CKSE I X'tal select15 SPDA O Processor status signal output. 65 /DACT I Test16 COFS O Frame clock(7.35kHz) output by amendment 66 TESIN I Test input17 MONIT O LSI internal signal monitor 67 TESTIO1 I Test input/output18 VDD - Digital power plus source. 68 VSS - Digital ground19 TESIO0 I Test input/output 69 PXI I "DSP" clock oscillator input20 P2VRREF - 2V REF by PLL only 70 PXO O "DSP" clock oscillator output21 SPDO O VCO sensor frequency shift 71 VDD - Digital pulse power source22 PDOS O output of phase error between EFM signal and PLC signal 72 XVSS - Ground for system clock oscillator 23 PDO O output of phase error between EFM signal and PLCK signal 73 XI I System clock oscillator input24 TMAXS O TMAX detection result output 74 XO O System clock oscillator output25 TMAXS O TMAX detection result output 75 XVDD - System clock oscillator pulse power source26 LPFN I Inversion of low pass filter amplifier input 76 DVDD - power source for D/A converter27 LPFO O Low pass filter amplifier output 77 RO O "R" channel data output28 PVREF - Dedication of PLL VREF 78 DVSS - D/A converter analogue Ground29 VCOREF I VCO sensor frequency reference level 79 DVR - D/A converter Reference power source30 VCOF O VCO filter 80 LO O "L" channel data output31 AVSS - Analogue ground 81 DVDD - D/A converter power source32 SLCO O Data slice level generation "DAC" output 82 TEST1 I Test port33 RFI I RF signal input 83 TEST2 I Test port34 AVDD - Analogue power source 84 TEST3 I Test port35 RFCT I RFRP signal sensor level input 85 BUSO I/O Data input for micon interface36 RFZI I RFRP zero cross input 86 BUS1 I/O Data input for micon interface37 RFRP I Ripple 87 BUS2 I/O Data input for micon interface38 FEI I Focus error signal input 88 BUS3 I/O Data input for micon interface39 SBAD I Subbeam additional signal input 89 VDD - Digital power source40 TSIN I Test input 90 VSS - Digital ground41 TEI I Tracking error input 91 BUCK I Clock input for micon interface42 TEZI I Tracking error zero cross input 92 /CCE I Chip enable signal input for micon interface43 FOO O Focus equaliser output 93 TEST4 I Test port44 TRO O Tracking equaliser output 94 /TSMOD I Local test mode selector45 VREF - Analogue reference power 95 /RST I Reset signal input46 RFGC O RF magnitude regulation control output 96 TEST0 I Test port47 TEBC O Tracking Blanca control signal output 97 /HSO O Play speed mode flag output48 FMO O Field equaliser output 98 /UHSO O Play speed mode flag output49 FVO O Speed error signal or Field search "EQ" output 99 EMPH O Subcode "Q" data emphasis flag output50 DMO O Disc equaliser output 100 LRCK O Channel clock(44.1kHz) output
IC701 TC9461F(DIGITAL SERVO SIGNAL PROCESSOR)
IC904 MC74HC00AF(QUAD 2-INPUT NAND)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
VCC
B4
A4
Y4
B3
A3
Y3
A1
B1
Y1
A2
B2
Y2
GND
IC903 MC74HC175DR(QUAD D FLIP-FLOP)
1
2
3
4
5
6
7
8
VCC
Q3
Q3
D3
D2
Q2
Q2
CLOCK
16
15
14
13
12
11
10
9
Inputs Output
Reset
L
H
H
H
D
X
H
L
X
Q
L
H
L
Q
H
L
H
Clock
X
L No Change
- 76 -
IC801 TC90A41AF(DATA PROCESSOR)No. Name I/O DESCRIPTION No. Name I/O DESCRIPTION
1 DPCK! I Basic clock input 51 DVR I DMO basic power source2 DVDD3 - Digital power source 3.3V 52 DMO O Disc Equaliser output for DVD3 SVCK1 I Servo basic clock input 53 RASN O External RAM address selector4 SVCK0 O Servo basic clock output 54 CASN O External RAM address selector5 DVSS - Digital power source 0V 55 MOEN O External RAM output Permission signal6 DVDD3 - Digital power source 3.3V 56 MWEN O External RAM read/write select7 N.C - N.C 57 DVSS - Digital power source 0V8 HDWT I MPU write signal 58 DVDD3 - Digital power source 3.3V9 HDRD I MPU read signal 59 MA9 O External RAM address bus10 HCEN I MPU chip selector 60 MA8 O External Ram address bus11 HDO I/O MPU data buss 61 MA7 O External Ram address bus12 HD! I/O MPU data buss 62 MA6 O External Ram address bus13 HD2 I/O MPU data buss 63 MA5 O External Ram address bus14 HD3 I/O MPU data buss 64 MA4 O External Ram address bus15 HD4 I/O MPU data buss 65 MA3 O External Ram address bus16 HD5 I/O MPU data buss 66 MA2 O External Ram address bus17 HD6 I/O MPU data buss 67 MA1 O External Ram address bus18 HD7 I/O MPU data buss 68 MA0 O External Ram address bus19 DVSS - Digital power source 0V 69 DVSS - Digital power source 0V20 DVDD5 - Digital power source 5V 70 DVDD5 - Digital power source 5V21 HINT O MPU interrupt signal 71 MD7 I/O External Ram data bus22 HAO I MPU address buss 72 MD6 I/O External Ram data bus23 HA1 I MPU address buss 73 MD5 I/O External Ram data bus24 PLCK I/O Read channel clock input 74 MD4 I/O External Ram data bus25 ED0 - N.C 75 MD3 I/O External Ram data bus26 ED1 - N.C 76 MD2 I/O External Ram data bus27 ED2 - N.C 77 MD1 I/O External Ram data bus28 ED3 - N.C 78 MD0 I/O External Ram data bus29 ED4 - N.C 79 SD7 O MPEG data output30 ED5 - N.C 80 SD6 O MPEG data output31 ED6 - N.C 81 SD5 O MPEG data output32 ED7 - N.C 82 SD4 O MPEG data output33 TEST I Low setting 83 DVSS - Digital power source 0V34 PD0N O PLL phase error signal output 84 DVDD3 - Digital power source 5V35 PD0P O PLL phase error signal output 85 SD3 O MPEG data output36 PLLD O PLL detection result output 86 SD2 O MPEG data output37 LPFN I input for PLL loop filter 87 SD1 O MPEG data output38 LPFO O output for PLL loop filter 88 SD0 O MPEG data output39 VCOF O VCO filter output 89 SERR O MPEG data Reliability flag40 SLCO O Basic power output for internal Comparator 90 SBGN O MPEG output sector synchronise signal41 AVSS - Analogue power source 91 SENB O MPEG data effective flag42 AVR O Analogue power source for not PLL stem 92 SDCK O MPEG data Forwarding clock43 VRC - Resister division point voltage 93 DVSS - Digital power source44 PVR O Analogue power source for PLL stem 94 SREQ I MPEG data request flag45 AVDD - Analogue power source 95 RSTN I Hard reset input46 BAIS - Second basic power 0V 96 DVDD3 - Digital power source47 RVDD - Power source 3.3V 97 STDA O Play status monitor data48 RFIN I RF signal input 98 STCK O Play status monitor synchronies signal49 RVSS - Power source 0V 99 UPWM O General purpose PWM output50 RVR1 - First basic power source 100 DVSS - Digital power source 0V
IC BLOCK DIAGRAM & DESCRIPTION
IC911 BA033FP(REGULATOR)
1 32
OUT
GND
VCC
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IC802 TC6815AF(DVD copy protection)No. Name I/O DESCRIPTION No. Name I/O DESCRIPTION
1 SCL I Power on reset 41 N.C - Open2 VSS - Ground 42 VSS - Ground3 VDD5 - Power source 5V 43 MCK1 I System clock4 PVSDA7 - MPEG data MSB 44 VDD5 - Power source 5V5 PVSDA6 - MPEG data 45 N.C - Open6 PVSDA5 - MPEG data 46 PECTIN O Program_end_code insert timing monitor7 PVSDA4 - MPEG data 47 SREQ O Sector data request flag8 PVSDA3 - MPEG data 48 SDCK I Sector data transfer clock9 PVSDA2 - MPEG data 49 SENB I Sector data effective flag10 PVSDA1 - MPEG data 50 SBGN I Sector synchronise signal11 PVSDA0 - MPEG data LSB 51 SERR I Sector data reliability flag12 VSS - Ground 52 VSS - Ground13 PVSREQ I MPEG data request flag 53 SD0 I Sector data LSB14 PVSACK O MPEG data effective flag 54 SD1 I Sector data15 PVSERR O MPEG data reliability flag 55 SD2 I Sector data16 PVSSYNC O MPEG output selector synchronise signal 56 SD3 I Sector data17 BSTCLK O MPEG data transfer clock 57 SD4 I Sector data18 BCLK I Bit clock 58 SD5 I Sector data19 LRCK I Sample clock 59 SD6 I Sector data20 VDD5 - Power source 5V 60 SD7 I Sector data MSB21 MCK2 I System clock 61 VDD5 - Power source 5V22 VSS - Ground 62 VSS - Ground23 AOUT I Serial CD data 63 VSS - Ground24 IPF I Error flag 64 VSS - Ground25 HD7 I/O MPU data bus MSB 65 MPDAT0 I/O MPU data bus LSB26 HD6 I/O MPU data bus 66 MPDAT1 I/O MPU data bus27 HD5 I/O MPU data bus 67 MPDAT2 I/O MPU data bus28 HD4 I/O MPU data bus 68 MPDAT3 I/O MPU data bus29 HD3 I/O MPU data bus 69 MPDAT4 I/O MPU data bus30 HD2 I/O MPU data bus 70 MPDAT5 I/O MPU data bus31 HD1 I/O MPU data bus 71 MPDAT6 I/O MPU data bus32 HD0 I/O MPU data bus LSB 72 MPDAT7 I/O MPU data bus MSB33 VDD5 - Power source 5V 73 VDD5 - Power source 5V34 HA1 O MPU address bus for data process 74 MPAD0 I MPU address 35 HA0 O MPU address bus for data process 75 MPAD1 I MPU address 36 HCEN O MPU chip selector for data process 76 MPCS I MPU chip selector37 HDRD O MPU read signal for data process 77 MPRD I MPU read signal38 HDWT O MPU write signal for data process 78 MPWT I MPU write signal39 VDD5 - Power source 5V 79 N.C - Open40 N.C - Open 80 MPINT O Interrupt signal
IC BLOCK DIAGRAM & DESCRIPTION
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IC BLOCK DIAGRAM & DESCRIPTIONFL601 VACUUM FLUORESCENT DISPLAY
DISPLAY PATTERN
COLOR OF ILLUMINATIONBlue-green : Unless speci f ied segment colorRed :