Serrano 1

7/29/2019 Serrano 1

1/29

Introduction to FieldProgrammable Gate Arrays

Lecture 1/3

CERN Accelerator School on Digital Signal ProcessingSigtuna, Sweden, 31 May 9 J une 2007

J avier Serrano, CERN AB-CO-HT

7/29/2019 Serrano 1

2/29

Outline

zHistorical introduction.

zBasics of digital design.zFPGA structure.

zTraditional (HDL) design flow.zDemo.

7/29/2019 Serrano 1

3/29

Outline




7/29/2019 Serrano 1

4/29

Historical Introduction

z In the beginning, digital design was done with the 74 series of chips.

z

Some people would design their own chips based on Gate Arrays, whichwere nothing else than an array of NAND gates:

7/29/2019 Serrano 1

5/29

Historical Introduction

z The first programmable chips were PLAs (Programmable Logic Arrays): twolevel structures of AND and OR gates with user programmable connections.

z Programmable Array Logic devices were an improvement in structure andcost over PLAs. Today such devices are generically called ProgrammableLogic Devices (PLDs).

7/29/2019 Serrano 1

6/29

Historical introduction

z A complex PLD (CPLD) is nothing else than a collection of multiple PLDsand an interconnection structure.

z Compared to a CPLD, a Field Programmable Gate Array (FPGA) contains amuch larger number of smaller individual blocks + large interconnectionstructure that dominates the entire chip.

7/29/2019 Serrano 1

7/29

Outline




7/29/2019 Serrano 1

8/29

Basics of digital design

z Unless you really know what you are doing, stick tosynchronous design: sandwiching bunches of

combinational logic in between flip flops.

z Combinational logic: state of outputs depend on currentstate of inputs alone (forgetting about propagation delaysfor the time being). E.g. AND, OR, mux, decoder,adder...

zD-type Flip flops propagate D to Q upon a rising edge inthe clk input.

z Synchronous design simplifies design analysis, which is

good given todays logic densities.

7/29/2019 Serrano 1

9/29

Dont do this!

Toggle flip-flops get triggered by glitches produced by different path

lengths of counter bits.

7/29/2019 Serrano 1

10/29

Basics of (synchronous) Digital Design

dataSelectC

dataAC[31:0]

dataBC[31:0]

dataSelectCD1

dataACd1[31:0]

DataOut_3[31:0]

0

1

DataOut[31:0]

sum_1[31:0]

+sum[31:0]

DataOut[31:0][31:0]

DataInB[31:0][31:0]

DataInA[31:0][31:0]

DataSelect

Clk

Q[0]D[0]

[31:0]Q[31:0]

[31:0]D[31:0]

[31:0]Q[31:0]

[31:0]D[31:0]

Q[0]D[0]

[31:0]Q[31:0]

[31:0]D[31:0]

[31:0]

[31:0][31:0] [31:0]Q[31:0]

[31:0]D[31:0]

[31:0]

[31:0][31:0] [31:0]Q[31:0]

[31:0]D[31:0]

High clock rate:144.9 MHz on aXilinx Spartan IIE.

Higher clock rate:151.5 MHz on thesame chip.

dataSelectC

dataAC[31:0]

dataBC[31:0]

sum[31:0]

+

DataOut_3[31:0]

0

1DataOut[31:0]

DataOut[31:0][31:0]

DataInB[31:0][31:0]

DataInA[31:0][31:0]

DataSelect

ClkQ[0]D[0]

[31:0]Q[31:0]

[31:0]D[31:0]

[31:0]Q[31:0]

[31:0]D[31:0]

[31:0]

[31:0][31:0]

[31:0]

[31:0][31:0] [31:0]Q[31:0][31:0] D[31:0]

6.90 ns

6.60 ns

Illustrating the latency/throughput tradeoff

7/29/2019 Serrano 1

11/29

Outline




7/29/2019 Serrano 1

12/29

Basic FPGA architecture

7/29/2019 Serrano 1

13/29

The logic block: a summary view

Example: using a LUTas a full adder.

7/29/2019 Serrano 1

14/29

A practical example: Xilinx Virtex II Pro

family (used in the lab)

Overview ConfigurableLogic Block (CLB)

Embedded PowerPC

Digitally Controlled Impedance (DCI)

7/29/2019 Serrano 1

15/29


family

Slice

Detail of half-slice

7/29/2019 Serrano 1

16/29


family

Routing resources

7/29/2019 Serrano 1

17/29

FPGA state of the art

z In addition to logic gates and routing, in a modern FPGA

you can find:{ Embedded processors (soft or hard).

{Multi-Gb/s transceivers with equalization and hard IP for serialstandards as PCI Express and GbitEthernet.

{ Lots of embedded MAC units, with enough bits to implementsingle precision floating point arithmetic efficiently.

{ Lots of dual-port RAM.

{ Sophisticated clock management through DLLs and PLLs.

{ System monitoring infrastructure including ADCs.

{On-substrate decoupling capacitors to ease PCB design.

{Digitally Controlled Impedance to eliminate on-board termination

resistors.

7/29/2019 Serrano 1

18/29

Embedded processors

7/29/2019 Serrano 1

19/29

Why use embedded processors?

Customization: take only the

peripherals you need andreplicate them as many timesas needed. Create your owncustom peripherals.

Strike optimum balance in system partitioning.

7/29/2019 Serrano 1

20/29

Serial signaling

z Avoids clock/data skew by using embedded clock.

z Reduces EMI and power consumption.

z Simplifies PCB routing.

7/29/2019 Serrano 1

21/29

Clock management

7/29/2019 Serrano 1

22/29

Outline




7/29/2019 Serrano 1

23/29

Traditional design flow 1/3

HDL

Synthesis

Implementation

Download

HDL

Implement your

design using

VHDL or Verilog

Functional

Simulation

Timing

Simulation

In-Circuit

Verification

Behavioral

Simulation

7/29/2019 Serrano 1

24/29


Behavioral

Simulation

HDL

Synthesis

Implementation

Download

HDL

Synthesize the

design to create

an FPGA netlist

Functional

Simulation

Timing

Simulation

In-Circuit

Verification

7/29/2019 Serrano 1

25/29


Behavioral

Simulation

HDL

Synthesis

Implementation

Download

HDL

Translate, place

and route, and

generate a

bitstream todownload in the

FPGA

Functional

Simulation

Timing

Simulation

In-Circuit

Verification

7/29/2019 Serrano 1

26/29

VHDL 101

Both VHDL code segments produce exactly the same hardware.

7/29/2019 Serrano 1

27/29

VHDL 101: hierarchy

7/29/2019 Serrano 1

28/29

Outline




7/29/2019 Serrano 1

29/29

Demo

zNow, lets see how you go from design

idea to hardware, using the traditionalflow.

zMany thanks to J eff Weintraub (XilinxUniversity Program), Bob Stewart

(University of Strathclyde) and Silica forsome of the slides.

Serrano 1

Documents