Serial Communication - University of Guelph · 2012-09-12 · Serial Communication A. Asynchronous communication B. Serial communication interface (SCI) C. SCI Registers D. Synchronous

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ENGG4640/3640; Fall 2004; Prepared by Radu Muresan 1

Serial CommunicationA. Asynchronous communicationB. Serial communication interface

(SCI)C. SCI RegistersD. Synchronous serial I/OE. The SPI interfaceF. SPI topologies and applications


The Serial Subsystems68HC11 has 2 subsystems for serial interfacing

the serial communication interface (SCI) that can be used to connect a terminal or personal computer to the microcontrollerserial peripheral interface (SPI) can provide high-speed serial communication to peripherals or other microcontroller units

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Asynchronous Communication Systems

Serial communication conceptsProtocols and flow controlCommunication channels and modems


Serial Communication ConceptsAsynchronous communication

each device uses its own clockthe clocks must run at the same rate but do not need to be synchronizedthe asynchronous I/O subsystem of 68HC11 is called SCIan asynchronous communication system must have at least one transmitter and one or more receivers

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Start and Stop Framing. ParityThe basic unit of information is the character or data frameThe transmitter can send characters at any rate, so there may be delays between the transmission of each characterThe receiver needs to know when a character starts and when it stops => character is framed by start and stop bitsParity is used to detect single bit errors

type: even or oddthe quantity of 1 bits in the data det the parity bit


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ExampleShow the framing bits when the character B is sent at 7 data bits, 2 stop bits, odd parity:Solution:

start bit: 0data bits: 0100001parity bit: 1stop bits: 11


Data Speed, BaudSerial data speed is the number of bits transmitted per second (BPS)Baud is the rate at which the signal changes

Note: bauds and BPS are not equalBaud rate includes the start, parity, and stop bitsOften the baud is used to express the number of bits transferred per second => 9600 baud means 9600 bits per second

BPS = (nr of data bits)/(nr of frame bits) x baudcharacters per sec = baud/(nr of frame bits)

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RS-232 Interface StandardEquipment using asynchronous serial com. normally use the RS-232 interfaceThe logic levels used for RS-232 signals are:

Nominal levels: +12 V for logic 0; -12 V for logic 1

This is to allow signals to be transmitted over greater distancesThis is a bipolar form of NRZ formatThe standard defines 25 different signals

Many signals are not used => serial ports also use a DB-9 connectorCommon signals:

Transmit data: TxD or TDReceive data: RxD or RDRequest to send: TSRClear to send: CTSData set ready: DSRSignal ground: SGData carrier detect: DCDData terminal ready: DTRRing indicator: RI

From normal HCMOS and TTL levels we need to use special driver chips for ...


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The use of MAX 232chip to build an 68HC11 RS-232 port


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Protocols and Flow Control

Acknowledge/Not Acknowledge (ACK/NAK) flow control

transmitter waits for the receiver to send ACK or NAK (negative ACK)

Cyclic redundancy Check (CRC). a special code based on the bit pattern used to check data integrityA communication protocol specifies the type of CRC used

XON/XOFF flow control.XOFF: signal to tell the transmitter to stop tr.XON: signal to tell the transmitter to resume transmission


Communication Channel Operation

Communication channel is a signal path that connects 2 stations/devicesThere are 3 basic modes to transmit data along a communication channel:

simplexhalf-duplexfull-duplex

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ModemsModems is a contraction of modulator-demodulatorModem is used to send and receive serial digital data over a telephone lineExamples ...Basics of modemsModem is connected to a serial port

dedicated circuit

the serial port, the RS-232 data terminal equipment (DTE) -> connected to a modem, a data communication equipment (DCE) -> to a telephone lineTransmission ...Receiving ...The audio signal is know as the carrier signalTech: PSK; DPSK; QAM

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Modem Handshaking Control

Originate modem: modem that starts a trAnswer modem: modem being calledFor a modem to com with another they must establish connection => they must also, maintain the connection and later terminate itNext slide table shows the modem control signals

A serial com IC typically has pins for at least some of the modem control signalsSoftware control of general purpose I/O pin is required for any that are missingNote that 68HC112 does not have any modem control signalsSome modem chips also have a DCD signal ...


Modem Control Signal

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Handshake Control is as followsTo send data

In simplex modeIn duplex mode

Establish connection

Serial Port

Originate Modem

Serial Port

Answer Modem


The Serial Communication Interface (SCI) in 68HC11

With additional conversion circuits the SCI can be used to communicate with remote devicesSCI uses port D pin PD1 as TxD and PD0 as RxDThese lines can be enabled or disabled by one of the SCI control registers (SCCR2)When enabled SCI subsystem has control of the respective port D lines and overrides DDRD settings

Transmitting is a simple matter of writing bytes to a data register SCDR

the SCI handles the framing requirements (no parity)

The SCI receiver automatically each framed serial character into a byteBAUD register is used to configure the clockThe SCI can send break signals (SBK in SCCR2)Wake-up control bit (RWU)WAKE ...

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Double Buffering in the SCI System


Transmit OperationSystem writes a byte of data to the transmit data register TDR

character is transferred tot the output shift registerT8 included if enabled

The shift register automatically outputs a start bit and the data bits and automatically adds a stop bit at the end BAUD register determines the shift rate

TDRE (transmit data register empty) flag is set every time SCI transfers data from buffer to the shift regTDRE can be detected by polling or interrupts

writing the TDR buffer clears TDRE

The system can write the second byte while the first one is still being transferred

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Receive OperationThe first low signal, a start bit, triggers the receiver to shift in the next 8 bits

if configured transfers 9th

bit to R8 in SCCR1The setting of BAUD will determine the rate of sampling and shifting inshifting complete: content -> to RDR bufferTransferring this data sets the RDRF

The receiver samples the stop bit and waits for the next start bitA receiver driver may read the RDR buffer any time while the next data is being shifted inThe software should read the buffer before the next byte has shifted in completely RDRF is reset by reading RDR


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SCI SoftwareThe software should initialize the SCI subsystem first – this could be a subroutine that is executed after a resetOther SCI I/O handler subroutines could be responsible for transmitting a byte or receiving a byte


SCI Configuration ProcedureConfig procedures

1. Write BAUD register (SCP0-1, SCR0-2)2. select the word length and wake up – write to the SCCR1 reg (M, WAKE)3. Enable interrupts, transmit, receive, and wake up as required. Write to the SCCR2 register (TIE, TCIE, RIE, ILIE, TE, RE, RWU)

Transmit procedure/byte1. Poll SCSR or respond to the interrupt (read SCSR)

2. If applicable (M=1), write to T8 in the SCCR1 reg3. If TDRE == 1, write to the SCDR register

Receiver procedurePoll the SCSR register or respond to the interruptIf RDRF == 1, then read SCDR register3. Option: if there is an error (OR|NF|FE == 1), handle the error4. If applicable (M=1) read R8 in the SCCR1 register

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Example 1 ProgramThe program illustrates a polling technique to transmit and receive data. It is a loopback testing program

the transmit pin is connected back to the receive pinIts purpose is to test the serial interface, such as RS-232 portThe program transmits the data stored at $00 continuously to the SCI transmitter and reads it back from the SCI receiver. It stores the received byte at $01The user can set configuration registers BAUD, SCCR1, and SCCR2 as desired by setting addresses $02, $03, and $04

Xtal = 8MHz, E = 2 MHzORG 0

TRDAT FCB $A5 ; data to tr.RECDAT RMB 1BAUDDAT FCB $30 ; Baud = 9600CONF1 FCB $00 ; M=0, WAKE = 0CONF2 FCB $0C ; TE=1, RE = 1


InitializationBlock

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SCI Registers. The SCDR (Serial Communication Data Register)

Both the transmit data register (TDR buffer) and the receive data register (RDR) have the address of the SCI data register (SCDR)

if data is written to data register SCDR, data goes to the TDRif data register SCDR is read, data comes from the RDR => the MCU software cannot read back the data it has already sent

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The Baud Register (BAUD)The crystal frequency is divided by 4 to get the bus rate EThe prescale select bits SCP1-SCP0, select an initial division factor 1, 3, 4, 13 that drive a series of divide by 2 stagesThe rate select bits (SCR2-SCR0) determine where the RT clock will be tapped off this divider chainThe RT clock is 16x the baud-rate frequencyThis 16x baud-rate is finally divided by 16 to get the transmitter baud-rate clock


Serial Communication Control Register (SCCR1)

The register provides the control bits that determine word length and select the method used to wake up a sleeping receiverMultiple receivers ...Wake-up. There are two ways to wake up a receiver:

Idle-Line wake-up Address-mark wake-up

Mode select (character format) ...

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Serial Communication Control Register 2 (SCCR2)

SCCR2 provides the control bits that enable or disable individual functions for the SCITransmit interrupt enable (TIE) ...Transmit complete interrupt enable (TCIE) ...Receive interrupt enable (RIE) ...Idle line interrupt enable (RIE) ...Transmitter/Receiver enable (TE/RE)

puts the PD1/PD0 as a SCI transmit/receiver pins

Receiver wake-up control (RWU) Send break (SBK)

sends zeroes as long as SBK = 1


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;frame data


;default setting

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Serial Communication Status Register (SCSR)

SCSR provides input to the MCU internal interrupt logic circuits and for pollingTransmit data register empty flag (TDRE)

to clear TDRE: read SCSR then write SCDRTransmit complete flag (TC)

sets when tr has reached an idle state, no pending data. To clear TC: read SCSR then writhe SCDR

Receive data register full flag (RDRF)To clear RDRF: read SCSR then read SCDR

Idle line detect flag (IDLE)set when an active receive line becomes idleto clear: read SCSR then read SCDR

Receive error flags (OR, NF, FE)to clear: read SCSR then read SCDR

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Receive ErrorsOverrun error flag (OR)

a newly received character has been shifted and the buffer is still full

Noise error flag (NF)the samples when receiver samples a bit are not identical

Framing error flag (FE)an invalid stop bit was detected

Parity error: SCI doesn’t have a built-in logic to detect parity error. However, software can be used if it is necessary

Error detection: See Listing 10.4 of Chapter 10


OverrunError

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Noise Error


FramingError

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Synchronous Serial I/OSynchronous means that the transmitter and receivers all use the same clock signal

their respective clocks may be out of phase

The transmitter in a synchronous comm system sends a clock signal for receiversCategories of sync serial system: local transfers (built in); linking comp and peripheral devices over long distances (defined standard)

Serial peripheral interface (SPI) – many IC use serial I/O for interfacing with a microcontrollerThe SPI subsystem can be used for both processor to peripheral or processor comThe complete automobile control system uses many sensors and actuators that are controlled by ICs that use SPI


The Serial Peripheral Interface (SPI)

The SPI subsystem of 68HC11 can be configured to interface directly with numerous standard product peripherals supplied by various manufacturers

The subsystem can be configured as master or slave

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Bus Topology Used in SPI Communication


MicrocontrollerI/O With BusTopology

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Cascade Topology


MicrocontrollerI/O With CascadeTopology

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Configuration andRegisters


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Master SPI Operation

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Slave SPI Operation


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AssignmentsChapter 10 Exercises

THE END of the COURSE

THANK YOU !!!

Serial Communication - University of Guelph · 2012-09-12 · Serial Communication A. Asynchronous communication B. Serial communication interface (SCI) C. SCI Registers D. Synchronous

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