Serial ATA Technology Final 9-27-06

An Overview of An Overview of Serial ATA TechnologySerial ATA Technology

Chris EricksonChris EricksonGraduate StudentGraduate Student

Department of Electrical and Computer EngineeringDepartment of Electrical and Computer EngineeringAuburn University, Auburn, AL 36849Auburn University, Auburn, AL 36849

[email protected]

mailto:[email protected]

ObjectivesObjectives

Why SATA was inventedWhy SATA was invented

The differences between PATA and SATAThe differences between PATA and SATA

How the hardware is structured to transmit How the hardware is structured to transmit and receive SATAand receive SATA

Protocol of SATA transmissionProtocol of SATA transmission

What is PATA?What is PATA?

All of the below synonyms refer to a modern day All of the below synonyms refer to a modern day PATA drivePATA drive– PATA – Parallel Advanced Technology AttachmentPATA – Parallel Advanced Technology Attachment

– UDMA – Ultra Direct Memory AccessUDMA – Ultra Direct Memory Access

– IDE – Integrated Device ElectronicsIDE – Integrated Device Electronics

– EIDE – Enhanced IDEEIDE – Enhanced IDE

More on PATAMore on PATA

40 & 80 wire cable option40 & 80 wire cable option– 40 wire limited to UDMA 33 MB/s and below40 wire limited to UDMA 33 MB/s and below– 80 wire allowed for UDMA 66, 100, 133 MB/s80 wire allowed for UDMA 66, 100, 133 MB/s

Required by ATA spec to be 5v tolerant Required by ATA spec to be 5v tolerant (3.3v has been the norm for several years)(3.3v has been the norm for several years)

Must support Master/Slave/Cable SelectMust support Master/Slave/Cable Select

SATA BasicsSATA Basics

New ConnectorNew Connector– Saves spaceSaves space– More reliableMore reliable– More air flowMore air flow

Connector has 4 transmission wiresConnector has 4 transmission wires– Tx differential pairTx differential pair– Rx differential pairRx differential pair

SATA BasicsSATA Basics

SATA I for 1.5Gbps ~ 150MB/sSATA I for 1.5Gbps ~ 150MB/s

SATA II for 3.0Gbps ~ 300MB/sSATA II for 3.0Gbps ~ 300MB/s

Provides support for legacy command setProvides support for legacy command set

Includes new commands for SATA BIST Includes new commands for SATA BIST and power managementand power management

ConnectivityConnectivity

Serial ATA is point-to-point topologySerial ATA is point-to-point topology

– Hosts can support multiple devices but Hosts can support multiple devices but requires multiple linksrequires multiple links

– 100% available link bandwidth100% available link bandwidth

– Failure of one device or link does not affect Failure of one device or link does not affect other linksother links

Link CharacteristicsLink Characteristics

SATA uses full-duplex linksSATA uses full-duplex links– Protocol only permits frame transfer in one Protocol only permits frame transfer in one

direction at a timedirection at a time– Each link consists of a transmit and a receive Each link consists of a transmit and a receive

pairpair

SATA uses low voltage levelsSATA uses low voltage levels– Nominal voltage +/-250mV differentialNominal voltage +/-250mV differential

Power ManagementPower ManagementSATA has SATA has – Phy ReadyPhy Ready – Capable of sending and receiving data. – Capable of sending and receiving data.

Main phase locked loop are on and activeMain phase locked loop are on and active– PartialPartial – Physical layer is powered but in a reduced – Physical layer is powered but in a reduced

state. Must be able to return to Phy Ready within 10 state. Must be able to return to Phy Ready within 10 us.us.

– SlumberSlumber – Physical layer is powered but in a reduced – Physical layer is powered but in a reduced state. Must be able to return to Phy Ready within 10 state. Must be able to return to Phy Ready within 10 ms.ms.

ATA also defines IDLE, STANDBY, and SLEEPATA also defines IDLE, STANDBY, and SLEEP

Necessary for newer laptop & mobile devicesNecessary for newer laptop & mobile devices

SATA Architectural ModelSATA Architectural ModelDevice Control SoftwareDevice Control Software

Buffer MemoryBuffer Memory

DMA managementDMA management

Serial digital transport Serial digital transport controlcontrol

Serial digital link controlSerial digital link control

Serial physical interfaceSerial physical interface

Device LayersDevice Layers

Host Control SoftwareHost Control Software



Host LayersHost Layers



Serial physical interface Serial physical interface

ApplicationApplication

TransportTransport

LinkLink

PhysicalPhysical

Physical LayerPhysical Layer

Transmission (Tx) and Reception (Rx) of a Transmission (Tx) and Reception (Rx) of a 1.5Gb/s serial stream1.5Gb/s serial streamPerform power on sequencingPerform power on sequencingPerform speed negotiationPerform speed negotiationProvide status to link layerProvide status to link layerSupport power management requestsSupport power management requestsOut-of-Band (OOB) signal generation and Out-of-Band (OOB) signal generation and detectiondetection

Out of BandOut of Band

Part of normal power on sequencePart of normal power on sequence

Allows host to issue a device hard resetAllows host to issue a device hard reset

Allows device to request a hard resetAllows device to request a hard reset

Brings device out of low power stateBrings device out of low power state

Out of Band SignalsOut of Band Signals

COMRESETCOMRESET– Always originated by the hostAlways originated by the host– Forces a hard reset in the deviceForces a hard reset in the device– Used to start link initializationUsed to start link initialization

COMINITCOMINIT– Always originated by the deviceAlways originated by the device– Requests a link resetRequests a link reset– Issued by device in response to COMRESETIssued by device in response to COMRESET

Out of Band Signals (cont.)Out of Band Signals (cont.)

COMWAKECOMWAKE– Can be originated by either host or deviceCan be originated by either host or device– Used as final phase of OOB initializationUsed as final phase of OOB initialization– Used to bring out of low power & test statesUsed to bring out of low power & test states

Exit PartialExit PartialExit SlumberExit SlumberExit BISTExit BIST

Out of Band Signal FormsOut of Band Signal Forms

COMRESET / COMINITCOMRESET / COMINIT

COMWAKECOMWAKE

106.7 ns106.7 ns

106.7 ns106.7 ns 106.7 ns106.7 ns

320 ns320 ns

Out of Band Signaling ProtocolOut of Band Signaling Protocol

COMRESETCOMRESET

COMWAKECOMWAKE

COMINITCOMINIT

COMWAKECOMWAKE

HostHost DeviceDevice

SATA Port ModelSATA Port Model

Clock & Data Clock & Data RecoveryRecovery

SerializerSerializer

DeserializerDeserializer

Analog Front E

ndA

nalog Front End

OOB DetectOOB Detect

COMRESET / COMRESET / COMINITCOMINIT

COMWAKECOMWAKE

Data OutData Out

RX ClockRX Clock

Port Control Port Control

LogicLogic

Tx ClockTx ClockAlign GeneratorAlign Generator

Data InData In

Phy ResetPhy ResetPhy ReadyPhy ReadySlumberSlumberPartialPartial

SPD ModeSPD ModeSystem ClockSystem Clock

SPD SelectSPD Select

Tx +Tx +

Tx -Tx -

Rx -Rx -

Rx +Rx +
















TransportTransport

LinkLink

PhysicalPhysical

Link LayerLink Layer

8b / 10b encoding8b / 10b encodingScrambles and descrambles data and Scrambles and descrambles data and control wordscontrol wordsConverts data from transport layer into Converts data from transport layer into framesframesConduct CRC generation and checkingConduct CRC generation and checkingProvides frame flow control Provides frame flow control

Encoding ConceptsEncoding Concepts

All 32 bit Dwords are encoded for SATAAll 32 bit Dwords are encoded for SATA– 32 bits data = 40 bits of transmission32 bits data = 40 bits of transmission

Provides sufficient transition densityProvides sufficient transition density– Guarantees transition (0s and 1s) even if data Guarantees transition (0s and 1s) even if data

is 0x00 or 0xFFis 0x00 or 0xFF

Provides an easy way to detect Provides an easy way to detect transmission errortransmission error

Current Running Disparity (CRDCurrent Running Disparity (CRD))

As each character is encoded a count is As each character is encoded a count is maintained of the number of 0’s and 1’s being maintained of the number of 0’s and 1’s being transmittedtransmitted– More 1’s than 0’s give positive disparityMore 1’s than 0’s give positive disparity– More 0’s than 1’s gives negative disparityMore 0’s than 1’s gives negative disparity– Same number gives neutral disparitySame number gives neutral disparity

Only valid values of CRD are -1 and 1Only valid values of CRD are -1 and 1– Any other value indicates that a transmission error Any other value indicates that a transmission error

has occurredhas occurred

CRD+ & CRD- Encoded CharactersCRD+ & CRD- Encoded Characters

0 0 1 1 1 1 1 10 0 1 1 1 1 1 1

1 0 1 0 1 1 1 0 0 11 0 1 0 1 1 1 0 0 1 0 1 0 1 0 0 1 0 0 10 1 0 1 0 0 1 0 0 1

8b Character 0x3F8b Character 0x3F

This 10b Character transmitted This 10b Character transmitted when CRD negativewhen CRD negative

This 10b Character transmitted This 10b Character transmitted when CRD positivewhen CRD positive

This characterThis character

6 ones6 ones

4 zeros4 zeros

Disparity +2Disparity +2

This characterThis character

4 ones4 ones

6 zeros6 zeros

Disparity -2Disparity -2

SATA PrimitivesSATA Primitives

Convey real-time state informationConvey real-time state information

Control transfer of information between Control transfer of information between host and devicehost and device

Provide host/device coordinationProvide host/device coordination


ALIGN – Speed negotiation and at least ALIGN – Speed negotiation and at least every 256 Dwordevery 256 Dword

SYNC – Used when in idle to maintain bit SYNC – Used when in idle to maintain bit synchronizationsynchronization

CONT – Used to suppress repeated CONT – Used to suppress repeated primitivesprimitives


X_RDYX_RDY

R_RDYR_RDY

R_IPR_IP

R_OKR_OK

R_ERR R_ERR

SOFSOF

EOFEOF

HOLDHOLD

HOLDAHOLDA

SATA Frame StructureSATA Frame Structure

All SATA frames consist of:All SATA frames consist of:– A start of frame (SOF) delimiterA start of frame (SOF) delimiter– A payload – transport layer informationA payload – transport layer information– A Cyclic Redundancy Check (CRC)A Cyclic Redundancy Check (CRC)– An end of frame (EOF) delimiterAn end of frame (EOF) delimiter

SOFSOF CRCCRC EOFEOFPayload DataPayload Data

Link Layer Protocol (1)Link Layer Protocol (1)

SYNCSYNC SYNCSYNC SYNCSYNC SYNCSYNC SYNCSYNC SYNCSYNC




SYNCSYNC SYNCSYNCX_RDYX_RDYX_RDYX_RDYX_RDYX_RDYX_RDYX_RDY




X_RDYX_RDYX_RDYX_RDYX_RDYX_RDYX_RDYX_RDYX_RDYX_RDYX_RDYX_RDY

SYNCSYNC R_RDYR_RDYR_RDYR_RDYR_RDYR_RDYR_RDYR_RDY SYNCSYNC



X_RDYX_RDYX_RDYX_RDY SOFSOF DATADATA DATADATA DATADATA

R_RDYR_RDY R_RDYR_RDYR_RDYR_RDYR_RDYR_RDYR_RDYR_RDYR_RDYR_RDY



DATADATA DATADATA DATADATA DATADATA DATADATA DATADATA

R_RDYR_RDY R_IPR_IP R_IPR_IP R_IPR_IP R_IPR_IPR_RDYR_RDY



DATADATA DATADATA CRCCRC EOFEOF WTRMWTRM WTRMWTRM

R_IPR_IP R_IPR_IP R_IPR_IP R_IPR_IP R_IPR_IP R_IPR_IP



CRCCRC EOFEOF WTRMWTRM WTRMWTRM WTRMWTRM WTRMWTRM

R_IPR_IP R_IPR_IP R_IPR_IP R_IPR_IP R_IPR_IP R_IPR_IP



WTRMWTRM WTRMWTRM WTRMWTRM WTRMWTRM WTRMWTRM WTRMWTRM

R_IPR_IP R_OKR_OK R_OKR_OK R_OKR_OK R_OKR_OK R_IPR_IP



WTRMWTRM WTRMWTRM SYNCSYNC SYNCSYNC SYNCSYNC SYNCSYNC

R_OKR_OK R_OKR_OK R_OKR_OK R_OKR_OK R_OKR_OK R_OKR_OK


Link Layer Protocol (last)Link Layer Protocol (last)


R_OKR_OK SYNCSYNC SYNCSYNC SYNCSYNC SYNCSYNC R_OKR_OK

















TransportTransport

LinkLink

PhysicalPhysical

Transport LayerTransport Layer

Responsible for the management of Responsible for the management of Frame Information Structures (FIS)Frame Information Structures (FIS)

At the command of Application layer:At the command of Application layer:– Format the FISFormat the FIS– Make frame transmission request to Link layerMake frame transmission request to Link layer– Pass FIS contents to Link layerPass FIS contents to Link layer– Receive transmission status from Link layer Receive transmission status from Link layer

and reports to Application layerand reports to Application layer

Frame Information Structure (FIS)Frame Information Structure (FIS)

A FIS is a mechanism to transfer information A FIS is a mechanism to transfer information between host and device application layersbetween host and device application layers

– Shadow Register Block contentsShadow Register Block contents– ATA commandsATA commands– Data movement setup informationData movement setup information– Read and write dataRead and write data– Self test activationSelf test activation– Unique FIS Type CodeUnique FIS Type Code

FIS typesFIS typesFIS TYPE FIS TYPE

CODECODEDescriptionDescription DirectionDirection

27h27h Register transfer host to deviceRegister transfer host to device H DH D34h34h Register transfer device to hostRegister transfer device to host D HD HA1hA1h Set Device bitsSet Device bits D HD H39h39h DMA ActivateDMA Activate D HD H41h41h DMA SetupDMA Setup D HD H58h58h BIST ActivateBIST Activate D HD H5Fh5Fh PIO SetupPIO Setup D H D H 46h46h DataData D HD H

Register – Host to Device FISRegister – Host to Device FISByte 3Byte 3 Byte 2Byte 2 Byte 1Byte 1 Byte 0Byte 0

Dword 0Dword 0 FeaturesFeatures CommandCommand ReservedReserved FIS TYPE FIS TYPE (27h)(27h)

Dword 1Dword 1 Dev/HeadDev/Head Cyl HighCyl High Cyl LowCyl Low Sector Sector NumberNumber

Dword 2Dword 2 Features Features (exp)(exp)

Cyl High Cyl High (exp)(exp)

Cyl Low Cyl Low (exp)(exp)

Sector Sector NumberNumber

Dword 3Dword 3 ControlControl ReservedReserved Sector Sector CountCount

Sector Sector CountCount

Dword 4Dword 4 ReservedReserved ReservedReserved ReservedReserved ReservedReserved

BIST Activate FISBIST Activate FIS

Byte 3Byte 3 Byte 2Byte 2 Byte 1Byte 1 Byte 0Byte 0

00 ReservedReserved [ TASLFPRV ][ TASLFPRV ] ReservedReserved FIS Type 58hFIS Type 58h

11 Data [31:24]Data [31:24] Data [23:16]Data [23:16] Data [15:8]Data [15:8] Data [7:0]Data [7:0]

22 Data [31:24]Data [31:24] Data [23:16]Data [23:16] Data [15:8]Data [15:8] Data [7:0]Data [7:0]

T - Far end transmit only – transmit Dwords defined in words 1 & 2T - Far end transmit only – transmit Dwords defined in words 1 & 2A - No ALIGN transmission (valid only with T)A - No ALIGN transmission (valid only with T)S - Bypass scrambling (valid only with T)S - Bypass scrambling (valid only with T)L - Far end retimed loopback with ALIGN insertionL - Far end retimed loopback with ALIGN insertionF - Far end analog loopbackF - Far end analog loopbackP - Transmit primitives defined in words 1 & 2 of the FISP - Transmit primitives defined in words 1 & 2 of the FISR - ReservedR - ReservedV - Vendor Unique Test Mode – other bits undefinedV - Vendor Unique Test Mode – other bits undefined

Data FISData FISByte 3Byte 3 Byte 2Byte 2 Byte 1Byte 1 Byte 0Byte 0

Dword 0Dword 0 ReservedReserved ReservedReserved ReservedReserved FIS TYPE FIS TYPE (46h)(46h)

Dword 1Dword 1

N Dwords of DataN Dwords of DataMinimum 1 DwordMinimum 1 Dword

Maximum 2048 DwordsMaximum 2048 Dwords

Dword 2Dword 2

. . .. . .

Dword NDword N
















TransportTransport

LinkLink

PhysicalPhysical

Command / Application LayerCommand / Application Layer

Defined using a series of state diagramsDefined using a series of state diagrams– Register H Register H D D – Register D Register D H H– DMA data inDMA data in– DMA data outDMA data out

Host command layer may be the same but Host command layer may be the same but may only support legacy commandsmay only support legacy commands

Completed !!Completed !!

Any Question? Comments? Any Question? Comments?

Serial ATA Technology Final 9-27-06

Documents