SequentialCircuits.doc

8/14/2019 SequentialCircuits.doc

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Experiment #1: Flip Flops and Sequential Circuits


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Section I

Simulation

Figure 1 sho,s the 8atch circuit that ,as implemented on /ulti.im The :ord0enerator generated the + and ! inputs ,hile the 8ogic naly;er monitored outputsand inputs

igure = + 8atch Timing +iagram

s it can be seen infigure 2( ,henever the cloc? pulse is high cloc?@


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stays the same This behavior is e'pected( since the circuit uses a +-type edge triggeredflip-flopFigure 3sho,s the B-bit .ynchronous !ounter that ,as implemented on /ulti.im 7273)- flip-flop I!s ,ere used in order to count from 5 C 7 modulo D

igure B= B-bit .ynchronous !ounter

/ulti.im"s :ord 0enerator produced cloc? pulses ,hile the 8ogic naly;er monitoredthe cloc? pulses and outputs A5( A

The simulation of this B-bit .ynchronous !ounter produced the follo,ing timing diagramsho,n infigure 4:

igure 2= B-bit .ynchronous !ounter


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.imilarly( Figure 5 sho,s the B-bit synchronous !ounter that ,as implemented on/ulti.im 7273 )- flip-flop I!s ,ere used in order to count from 5 C 7 modulo DEnli?e the circuit for the .ynchronous counter( the use of a 66+ gate ,as not

necessary and the previous bit of each counter ,as used to control the ne't bit( only thecloc? of the first counter ,as connected to the function generator

igure F= synchronous !ounter

The simulation of the B-bit synchronous !ounter produced the follo,ing timingdiagram sho,n infigure 6:


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igure 3= Timing +iagram for the synchronous !ounter

Figure 7sho,s a 2-bit .hift Gegister that implemented on /ulti.im T,o 7272 + flip-flop I!s ,ere used in order to count from 5 C


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Figure 8= 2-bit .hift Gegister"s Timing +iagram

The timing diagram sho,n inFigure 8represents the cloc? inputs produced the/ulti.im"s :ord 0enerator and the outputs A5( A( AB that ,ere monitored by the8ogic naly;er


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Section II

Experimental !esults

In this section( the results obtained from implementing the circuits of figures 3, 5,and 7on the protoboard are reported

The .ynchronous !ounter sho,n infigure 3,as built on the protoboard The inputs ,ereproduced by the unction 0enerator

In order to reduce noise( a 5< micro capacitor could have been placed across the 9!!and 0round pin for each of the I!s( but that ,asn"t done here lso(


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Figure 9: Oscilloscope Image for Syc!roous "ou#er $ %&

Figure 1&: Oscilloscope Image for Syc!roous "ou#er $ %1


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Fiure 12: S!if# 'egis#er O (ro#o)oar*

+a)le 1sho,s the .hift Gegister built on the protoboard counting as e'pected=

+a)le 1: S!if# 'egis#er Ou#pu#

Conclusion


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This e'periment allo,ed students to understand ho, seuential circuits ,or? throughsimulations and e'perimental analysis4'perimental results of .ection > matched the simulation results obtained in .ection

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