1 1 Sequential Circuits CS 217 2 Combinational circuit • Directed acyclic graph (no loops) • Outputs, at any given time, dependent only on inputs at that time (after signal propagation) • Equivalent to one boolean formula per output x 2 y 2 z 2 c 1 c 2
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Sequential Circuits - cs.princeton.edu · 1 1 Sequential Circuits CS 217 2 Combinational circuit • Directed acyclic graph (no loops) • Outputs, at any given time, dependent only
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Sequential Circuits
CS 217
2
Combinational circuit• Directed acyclic graph (no loops)
• Outputs, at any given time, dependent only on inputs at that time (after signal propagation)
• Equivalent to one boolean formula per output
x2 y2
z2
c1c2
2
3
Cycles in the circuit• What happens if there are cycles?
4
Cycles in the circuit• Simulate . . .
0
3
5
Cycles in the circuit• Simulate . . .
0 1
6
Cycles in the circuit• Simulate . . .
0 1 0
4
7
Cycles in the circuit• Simulate . . .
1 1 0
8
Cycles in the circuit• Simulate . . .
1 0 0
5
9
Cycles in the circuit• Simulate . . .
1 0 1
10
Cycles in the circuit• Simulate . . .
0 0 1
0
1
time
Outputs, at any given time, dependent not only on inputs at that time;
also dependent on history. A “sequential” circuit.
6
11
Another circuit with cyclesThree inverters:
astable 0 0 1
0
1
time
0 1
Two inverters:
bistable 1 0
0
1
time
0
1
time
12
R-S Latch
= NOR gate
Reset
Set
Q
Q
7
13
R-S Latch
= NOR gate
Reset
Set
Q
Q
0
0
0
1
R
S
Q
Q
14
R-S Latch
= NOR gate
Reset
Set
Q
Q
0
1
1
0
R
S
Q
Q
8
15
R-S Latch
= NOR gate
Reset
Set
Q
Q
0
0
1
0
R
S
Q
Q
16
R-S Latch
= NOR gate
Reset
Set
Q
Q
1
0
0
1
R
S
Q
Q
9
17
R-S Latch
= NOR gate
Reset
Set
Q
Q
0
0
0
1
R
S
Q
Q
18
R-S Latch
= NOR gate
Reset
Set
Q
Q
1
0
0
1
R
S
Q
Q
10
19
R-S Latch
= NOR gate
Reset
Set
Q
Q
0
0
0
1
R
S
Q
Q
20
Clocked flipflop
Q
Clock
D
Q
D
ClockClock high:
copy D to Q
Clock low:
ignore D, remember Q
11
21
Master/Slave flipflop
Clock
D
Q
D
ClockClock high:
copy D to X; keep Q
Clock low:
copy X to Q; keep X
Q
X
22
Master/Slave flipflop
D
Clock
Q
X
D QCircuit symbol:
12
23
Synchronous sequential circuits
D Q
D Q
D Q D0
D1
D2
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Clock
Q0
Q1
Q2
• Flipflops all clocked simultaneously
• Combinational circuit determines next flipflop values (calculates D’s from Q’s).