SEPIC Project Report

A Project report on

POWER FACTOR CORRECTION WITH A NEW MODIFIED SEPIC

CONVERTER

Project report submitted to

Shanmugha Arts, Science, Technology & Research Academy

SASTRA UNIVERISTY

in partial fulfillment of the requirements for the award of the Degree of B.Tech

(Part-time) in ELECTRICAL & ELECTRONICS ENGINEERING

Submitted by

BALAMURUGAN P 010983003

MUSARRAF HOSSIAN SEKH 010983009

SATHIYA SEELAN S 010983017

GUIDED BY

Mr. S.Mohamed Ghouse,

Assistant Professor-II, EEE/ SEEE, SASTRA University, Thanjavur

Department of Electrical & Electronics Engineering School of Electrical & Electronics Engineering

Shanmugha Arts, Science, Technology & Research Academy SASTRA UNIVERSITY

Thirumalaisamudram, Thanjavur - 613 403

SCHOOL OF ELECTRICAL & ELECTRONICS ENGINEERING

SASTRA UNIVERSITY

BONAFIDE CERTIFICATE

This is to certify that the project work entitled “POWER FACTOR CORRECTION

WITH A NEW MODIFIED SEPIC CONVERTER” is the bonafide work done by

Balamurugan P (010983003), Musarraf Hossain Sekh (010983009), Sathiya Seelan S

(010983017) Students of VII Semester, B.Tech (Part-time) in Electrical & Electronics

Engineering during the academic year 2008-2009 in partial fulfillment of the requirement for

the award of Degree of Bachelor of Technology in Electrical and Electronics (Part-time) at

SASTRA University.

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Project Guide Dean, SEEE Submitted for the University Exam held on _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Internal Examiner External Examiner

SCHOOL OF ELECTRICAL & ELECTRONICS ENGINEERING

SASTRA UNIVERSITY

DECLARATION

We submit this project entitled “POWER FACTOR CORRECTION WITH A NEW

MODIFIED SEPIC CONVERTER” to SASTRA University, Tirumalaisamudram-613401,

in partial fulfillment of the award of B.Tech., Degree in ELECTRICAL & ELECTRONICS

ENGINEERING and we in full consciousness, declare this dissertation as our original and

independent work carried out under the guidance of Mr. S.Mohamed Ghouse, Assistant

Professor II, School of Electrical & Electronics Engineering, SASTRA University.

Date : _ _ _ _ _ _ _ _ _ Signature : 1. _ _ _ _ _ _ _ _ _ _ _ _ _ _ Place : _ _ _ _ _ _ _ _ _ 2. _ _ _ _ _ _ _ _ _ _ _ _ _ _ 3. _ _ _ _ _ _ _ _ _ _ _ _ _ _

ACKNOWLEDGEMENT

We would like to thank the management, our honorable Vice-Chancellor,

Prof. R.SETHURAMAN, Dean, Planning and Development,

Dr. S.VAIDHYASUBRAMANIAM and our esteemed Registrar,

Dr.S.N.SRIVASTAVA, for giving us this opportunity to develop our knowledge and

sharpen our technical skills.

We are also grateful to the Dean, School of Electrical & Electronics

Engineering, Prof. P.S. SRINIVASAN, for giving us an invaluable support on how

to proceed with the project. We are extremely thankful to our Project coordinator

Prof. R. MURALI SACHITHANANDAM, Senior Assistant Professor, School of

Electrical & Electronics Engineering for lending us support in completing the project.

We would like to convey our heartfelt thanks to our internal guide

Mr. S.MOHAMED GHOUSE, Assistant Professor II, School of Electrical &

Electronics Engineering, for guiding us in the best possible manner all through the

project.

Lastly, we are thankful to our parents and other family members for the

encouragement and moral support which they have been giving us in abundance.

CONTENTS

1. OVERVIEW

1

1.1 Abstract 2 1.2 Goal 2 1.3 Objective 2 1.4 Project plan 3 1.5 Main components used

4

2. INTRODUCTION 5

3. NEED FOR THIS PROJECT AND ITS ADVANTAGES

7

3.1 What is power factor? 8 3.2 Need for power factor correction 9 3.3 Various methods for power factor correction 9 3.4 What is a SEPIC? 10 3.5 Why SEPIC converter for power factor correction? 10 3.6 Problems of conventional SEPIC PFC 10 3.7 Proposed modified SEPIC PFC 11 3.8 Soft switching 11 3.9 Soft switching benefits

11

4. CIRCUIT DIAGRAM AND WORKING PRINCIPLE

12

4.1 Power circuit configuration 13

4.2 Conceptual waveforms 15

4.3 Working principle of the proposed PFC

15

5. DESIGNE OF THE PROPOSED PFC

22

5.1 DESIGN OF MODIFED SEPIC PFC

23

5.1.1 Selection of duty cycle 23 5.1.2 Selection of inductor 23 5.1.3 Selection of MOSFET 25 5.1.4 Selection of diodes 26 5.1.5 Selection of tank inductor 26 5.1.6 Selection of tank capacitor 27 5.1.7 Selection of load

27

5.2 DESIGN OF GATE CONTROL CIRCUIT

27

5.2.1 Selection of control voltage 28

5.2.2 Selection of Op-Amp 28

5.2.3 Selection of NOT gate 28

5.2.4 Selection of MOSFET gate driver circuit 28

6. SOFTWARE SIMULATION

29

6.1 Simulation software 31 6.2 Simulation results

32

7. HARDWARE PROTO TYPE IMPLEMENTATION AND TESTINGS

35

7.1 Measurements of key waveforms 37

7.2 Measurements of power factor 40

7.3 Measurements of efficiency

40

8. CONCLUSION

41

9. APPENDIX

43

9.1 Datasheet for LM 7812 44 9.2 Datasheet for LM 347 52 9.3 Datasheet for IRFP 460 64 9.4 Datasheet for CD4049 72 9.5 Datasheet for MIC 6a4 78 9.6 Datasheet for IR 2110

92

10. REFERENCES

93

1. OVERVIEW

Page 1

1.1 ABSTRACT:

Power electronic devices with front-end rectifier are widely used in industry,

commerce and transportation, which generate current harmonics, produce power

pollution and result in low power factor. Though there are several proposed

solutions to this, SEPIC converter was the most successful one. But the

conventional SEPIC converters suffer from high switching losses. Hence in this

project, a new modified SEPIC converter is proposed to achieve unity power

factor at the mains side with greater efficiency. The switching loss is reduced by

applying soft switching topology i.e. zero voltage switching (ZVS). A prototype

will be designed, analyzed and implemented along with required software

simulations to establish the thought.

1.2 GOAL:

Design and Implementation of a modified SEPIC based PFC to achieve unity

power factor with higher efficiency.

1.3 OBJECTIVE:

1. Analyze and compare the characteristic of a conventional SEPIC PFC versus

our modified SEPIC based PFC.

2. Software Modelling and Simulation of the modified SEPIC based PFC to

achieve unity power factor with lower switching losses using soft switching

topology.

3. Implementing a prototype the hardware model of the same to establish the

thought

Page 2

1.4 PROJECT PLAN:

Phase 1: Description of Activity:

1. Literature Survey – IEEE , Reference Books and International conference

papers

2. Study of Buck, Boost, Buck-Boost and SEPIC converters

3. Study and analysis of conventional SEPIC based PFC

4. Study of Soft switching Topologies

5. Study and analysis of proposed modified SEPIC based PFC

6. Presentation on first review meet


1. Designing the model of proposed modified SEPIC based PFC

2. Simulation and performance analysis of the proposed model

3. Comparison of conventional SEPIC based PFC vs proposed modified SEPIC

based PFC

4. Presentation on second review meet


1. Designing the hardware prototype of the proposed modified SEPIC based PFC

2. Implementation and performance analysis of the hardware prototype

3. Observation and Inferences

4. Presentation on final review meet

5. Submission of final report

Page 3

1.5 MAIN COMPONENTS USED:

1.5.1 GATE CONTROL CIRCUIT:

1. LM 7812 – A linear Voltage regulator

2. LM 347 – An OP-AMP

3. CD 4049U – A CMOS INVERTER

4. IR 2110 – A High Frequency MOSFET GATE DRIVER

5. 1A , 230/12V Step down transformer

1.5.2 SEPIC PFC CIRCUIT:

1. IRFP 460 – POWER MOSFET

2. INDUCTOR–20mH

3. INDUCTOR–22µH

4. COUPLING CAPACITOR

5. FILTER CAPACITOR

6. MIC 6A4 – POWER DIODE

Page 4

2. INTRODUCTION

Page 5

Power electronic devices with front-end rectifier are widely used in industry,

commerce and transportation, which generate current harmonics, produce power

pollution and result in low power factor. Therefore, there are international harmonic

standards (such as: IEC-1000 and IEC-555) to confine power pollution. In order to

meet the requirements of the standards, the input current waveforms of a device have

to be shaped by a PFC to eliminate current harmonics and improve power factor.

The PFCs can be briefly classified into two types. One is passive PFC,

the other is active one. Passive-type PFC is mainly constructed by inductors and

capacitors. Low efficiency, heavy weight and large volume are its major

disadvantages. Besides, power factor merely is improved to around 0.8. For active

type, active switch, diode and energy-stored component are used to achieve near

unity power factor, of which topologies have Buck, Boost, Buck-Boost, Cuk, ZETA,

SEPIC and Fly back. The Buck-type PFC can obtain an output voltage smaller than

ac input voltage. However, only a power factor of 0.95 is met. The Boost structure

attains better power factor correction feature but its output voltage is higher than ac-

side voltage and power components withstand high voltage stresses. The Buck-Boost

PFC can obtain an output voltage magnitude either larger or smaller than the input.

Nevertheless, there is a polarity reversal on the output and an isolation driver for

active switch is required. Among the Cuk, ZETA, SEPIC and Fly back PFC

topologies, the SEPIC type possesses better performance in total harmonics

distortion (THD), efficiency and power factor correction. Therefore, a modified

SEPIC-type PFC, which is feasible to operate in discontinuous conduction mode,

boundary conduction mode, or continuous conduction mode, is proposed for low

output-voltage applications. In addition, a soft-switching cell is embedded into the

converter to achieve ZVS for efficiency improvement.

Page 6

3. NEED FOR THIS PROJECT

AND ITS ADVANTAGES

Page 7

3.1 WHAT IS POWER FACTOR?

There are several ways to define power factor of a load. Such as

1. It is the cosine of the phase angel (Φ) between the load voltage and load

current.

Fig1: The voltage and current wave form of an Inductive load with Phase angle (Φ)

2. It is also the ratio of the real power or true power to the apparent power

of the load.

Fig2: Power Triangle of an Inductive load

APPARENT POWER (S) in KVA

TRUE POWER (P) in KW

POWER FACTOR OR IMPEDANCE ANGLE

Φ

Page 8

3.2 NEED FOR POWER FACTOR CORRECTION: There are The power drawn by a load from AC Mains depends not only on

Mains Voltage and Current but also on the Power Factor of the load.

Power drawn by a single phase load, W=VICosΦ

Where, V = Mains Voltage across the load

I =Load current

CosΦ = Power factor of the load i.e. the Cosine of the phase angle (Φ)

between the load Voltage and the load current

As our supply mains voltage is maintained constant, power drawn by the load

only depends on the load current and power factor from the above equation , it is

clear that for a particular load if the power falls, the load current increases which

results in higher current from supply mains and higher line loss. Higher line loss

reduces the transmission efficiency. Power electronic devices with front end

rectifier which is widely used in industry takes high pulsating current from mains

and produces severe current harmonics. This causes line pollution and reduces the

power factor. Hence in order to meet the international standards we must prevent

the line harmonics and improve the power factor. That is why there always a need

of power factor correction and power factor correction circuit.

3.3 VARIOUS METHODS FOR POWER FACTOR CORRECTION:

There are two types of power factor correction (PFC) circuits. One is passive

power factor correction circuit and the other is active power factor correction

circuit. Passive-type PFC is mainly constructed by inductors and capacitors. Low

efficiency, heavy weight and large volume are its major disadvantages. Besides,

power factor merely is improved to around 0.8. For active type, active switch,

diode and energy-stored component are used to achieve near unity power factor,

of which topologies have Buck, Boost, Buck-Boost, Cuk, ZETA, SEPIC and Fly

back.

Page 9

3.4 WHAT IS A SEPIC?

A single ended primary inductance converter or SEPIC is basically a DC-DC

converter which can operate in continuous, discontinuous, or boundary

conduction mode. The output voltage can be lesser, equal or higher than the input

voltage. The voltage can be controlled by adjusting the duty cycle of the switch.

The output voltage is also non-inverted with respect to the input voltage.

3.5 WHY SEPIC AS POWER FACTOR CORRECTION?

The Buck-type PFC can obtain an output voltage smaller than ac input voltage.

However, only a power factor of 0.95 is met. The Boost structure attains better

power factor correction feature but its output voltage is higher than ac-side

voltage and power components withstand high voltage stresses. The Buck-Boost

PFC can obtain an output voltage magnitude either larger or smaller than the

input. Nevertheless, there is a polarity reversal on the output and an isolation

driver for active switch is required. Among the Cuk, ZETA, SEPIC and Fly back

PFC topologies, the SEPIC type possesses better performance in total harmonics

distortion (THD), efficiency and power factor correction.

3.6 PROBLEMS OF CONVENTIONAL SEPIC PFC:

The conventional SEPIC suffers from high switching losses as in the normal

switching method (i.e. hard switching), power switches (MOSFETs) has to cut

off the current within turn off period while the full DC rail voltage applied across

it.

Therefore the switch has to withstand high voltage as well as current stresses

resulting in high switching losses and limiting the switching frequency.

Page 10

3.7 PROPOSED MODIFIED SEPIC PFC:

Therefore in this project we propose a modified SEPIC PFC which is feasible

to work in discontinuous, continuous, or boundary conduction mode for low

output voltage applications. In addition to this a soft switching cell is embedded

into the circuit to achieve Zero Voltage Switching. The soft switching will reduce

the switching losses thereby improving the efficiency.

3.8 SOFT SWITCHING:

In soft switching, it is ensured that the voltage across the switch or current

through the switch is zero or very low when they receive turns on signal or gate

signal. In 1980s the concept of resonant tank circuit was developed for switching.

By suitable introducing a resonant tank circuit along with the switch the

oscillatory voltage or current waves are created across the switch. By this zero

voltage or zero current conditions are created and the switching is performed at

either zero voltage or zero current.

3.9 SOFT SWITCHING BENEFITS:

There are several benefits of soft switching as compared to the conventional hard

switching. Such as

1. The switching losses are reduced.

2. The switching frequency can be increased to hundreds of Kilo Hertz

3. Magnetic components (such as inductor and its core) sizes are reduced.

4. The power density of converters are increased

Page 11

4. CIRCUITS AND

WORKING PRINCIPLE

Page 12

.1 POWER CIRCUIT CONFIGURATION:

nd a capacitor Cr is embedded into the PFC

stage for ZVS, as illustrated in Fig6.

4

For high line voltage or low output voltage applications, a PFC stage is

cascaded with a full-wave rectifier in input and a step-down dc/dc converter in

output, as shown in Fig. 3. The PFC stage shapes a high-crest-factor current

caused by the full-wave rectifier into a purely sinusoidal waveform to being in

phase with line voltage. However, the input voltage also is boosted. Therefore, it

is required that a dc/dc converter is added to drop voltage for dc load. Power is

processed by two stages, a PFC and a dc/dc converter, lowering overall efficiency

and increasing cost. To release the aforementioned drawbacks, a single-stage step-

down PFC is adopted, as shown in Fig. 4, in which the PFC stage performs power

factor correcting and steps down its input voltage to a desired level. In this paper,

a modified SEPIC configuration shown in Fig.5 is presented to serve as step-

down PFC stage. In Fig. 5, both diodes D5 and D6 prevent opposite current from

flowing through inductor L1 and L2, respectively. A soft-switching cell including

an active switch Q2, an inductor Lr a

Page 13

Page 14

4.2 CONCEPTUAL WAVEFORMS:

4.3 WORKING PRINCIPLE OF THE PROPOSED PFC

While the modified soft-switching SEPIC PFC operates in boundary conduction

mode (BCM) and with constant turn-on control, a high power factor can readily be

achieved. As a result, the envelope of the input current will follow the shape of line

voltage to be sinusoidal, which leads to unity power factor. When the resonant

frequency of the soft-switching cell is much higher than switching frequency of main

power circuit, over a switching cycle the operation of the PFC can be divided into

eight modes. Fig. 8 is the corresponding circuits and the related conceptual key

waveforms are shown in Fig. 7. The eight operation modes during a switching period

are discussed as following.

Page 15

Mode 1 [t0 ≤ t < t1, Fig8 (a)]:

During this time interval, switch Q1 is turned on and Q2 off. The inductor

currents of iL1 and iLr are linearly built and the capacitor C2 dumps energy to

inductor L2 by the way of Lr, Q1and D6. At the same time, the capacitor C3 supplies

power for dc load. The time constant determined by capacitance of C3 and dc-load

resistance is much larger than switching period so that output voltage vo can be

regarded as an constant. At time t=t1, this mode is ended and Q2 is turned off.

Mode 2 [t1 ≤ t < t2, Fig8 (b)]:

The inductor L1 discharges through the path of D5, resonant inductor Lr and

parasitical capacitor Cb1. Meanwhile, the capacitor C2 still dumps energy to L2 and

dc load draws power from C3. Since typical value of Cb1 is far smaller than

capacitance of C2, the voltage vDS1 across Cb1 increases rapidly. At t=t2, the voltage

vDS1 reaches vC2+vo and this mode is terminated.

Page 16

Mode 3 [t2 ≤ t < t3, Fig8 (c)]:

During this time interval, inductors L1 and Lr still discharge energy and

voltage vDS1 increases. The diode D7 starts conducting and the voltage across L2 is

equal to output voltage vo. Therefore, L2 dumps energy to output. At t=t3, the

voltage vDS1 attains to vCr+vC1-vL1 and this mode is ended.

Page 17

Mode 4 [t3 ≤ t < t4, Fig8 (d)]:

Inductors L1 and L2 releases energy continuously but capacitor C2 charges.

The parasitical capacitor of switch Q2 starts dumping energy by the way of Cr and Lr

until vDS2 drops to zero.

Mode 5 [t4≤ t < t5, Fig8 (e)]:

The body diode of Q2 is on and inductor Lr resonates with Cr. During this

time interval, switch Q2 is tuned on with ZVS. Operation of the PFC enters to next

mode as the current iLr decreases to zero.

Page 18

Mode 6 [t5 ≤ t < t6, Fig (f)]:

The energy stored in resonant capacitor Cr is dumped to Lr via Q2. As a result,

the current iLr increases negatively. In this time period, inductors L1 and L2 release

energy but C2 charges. At t=t6, Q2 is turned off and this mode is terminated.

Page 19

Mode 7 [t6 ≤ t < t7, Fig (g)]:

Switches Q1 and Q2 are off. The stored energy in the parasitical capacitor Cb1

is drawn by inductor Lr and vDS1 decreases. This mode ends when vDS1 drops to zero.

Mode 8 [t7 ≤ t < t8]:

The energy stored in Lr is discharges by the way of C2, D7, C3 and Db1. In

this time interval, switch Q1 is triggered. This mode is terminated while iLr equals

zero. A complete switching cycle is ended at t=t8, at which switch Q1 is turned on

again.

Page 20

During each switching period, the peak value of the inductor current iL1 can

be expressed as follows:

1

oPeakL1

t2 π sinL

)(= enP,

iTV(t)i

Where Vp is the amplitude of line voltage, TON stands for on time of switch Q1 and fl

presents line frequency. The average input current in each line period can be

expressed as follows:

∫π2

0PeakL1avL1

π21 (t)dti(t)i ,, =

=1

t2π 2 SinL

)(on ePs iTVf

In addition the input power can be found by

∫=π2

0S

π21 (t)dt(t)iVP S

12

22

LonP TfV s

=

Page 21

5. DESIGNE OF THE

PROPOSED MODIFIED PFC

Page 22

5.1 DESIGN OF MODIFIED PFC:

5.1.1 SELCTION OF DUTY CYCLE:

For a SEPIC converter operating in a continuous conduction mode

(CCM) or Boundary conduction mode, the duty cycle is given by:

Doutin

DoutD VVVVV++

+=

VD is the forward voltage drop of the output diode. The maximum duty cycle

is:

Doutin

DoutD VVVVV

+++

=(min)

max

For our application , we have chosen the input voltage is 60V and the output

voltage is 40V, the forward voltage drop across the output diode as 1V, Hence

the duty cycle can be found as,

14050140++

+=D = (41/91) = 0.45

And the maximum duty cycle can be found as

14045140

max +++

=D = (41/86) = 0.476,

considering the fall in input voltage @ 10 %, i.e. Vin (min)=(50-50*10%) = 45V

5.1.2 SELECTION OF INDUCTOR:

A good rule for determining the inductance is to allow the peak-to-peak

ripple current to be approximately 40% of the maximum input current at the

Page 23

minimum input voltage. The ripple current flowing in equal value inductors

L1 and L2 is given by:

%40(min)

%40 ××=×=∆in

outV

Viii outinL

In our application, we have chosen the total output is 80Watt and as the output

voltage has been selected as 40V, therefore,

output current , iout = 80/40= 2 Amp.

Hence,

71.010045

40402%40(min)

%40 =×××

=××=×=∆in

outV

Viii outinL

The inductor value is calculated by :

max(min)21 DfsiVinLLL ×===

×∆

Where, fs is the switching frequency and Dmax is the duty cycle at the

minimum Vin. (The switching frequency has been chosen as 50 KHz)

476.21 5000071.045

×===∴ ×LLL = 0.6 mH

As the standard nearest size is 1 miliHenry therefore L = 1 mH is chosen. The

peak current in the inductor, to ensure the inductor does not saturate, is given

by:

)(2%401

(min),1 +××=+

inDoutoutPeakL V

VVii

)(2%401,2 +×= outPeakL ii

Hence,

A186.22.145

1402)(2%401

(min),1 =×+×=+

+××=in

DoutoutPeakL VVVii

A4.22.12)(2%401,2 =×=+×= outPeakL ii

Page 24

5.1.3 SELECTION OF MOSFET :

The parameters governing the selection of MOSFET are the minimum

threshold voltage Vth(min), the on-resistance Rds(on), gate-drain charge QGD, and

the maximum drain to source voltage, VDS(max). Logic level or sub logic level

threshold MOSFETs should be used based on the gate drive voltage.

The peak switch voltage is equal to Vin+Vout. The peak switch current is

given by:

AVVVii

inDoutoutPeakL 186.22.1

451402)(

2%401

(min),1 =×+×=+

+××=

A586.44.2186.2, ,2,1 =+=+= PeakLPeakL iii PeakQ

The RMS current through the switch is given by:

245)140()14540(22(min)

)()(min)(,1

+×++×=

+×++=

in

DoutDinoutoutRMSQ VVVVVVii

= 2.64 A

For our application, we have chosen IRFP460 as it has the following

parameters which suits our requirement.

Drain to source Voltage, VDS = 500V

Drain to Gate Voltage, VDGR = 500V

Continuous Drain Current, ID = 20 A at normal temperature

Continuous Drain Current, ID = 12 A at 100o C temperature

Gate to Source Voltage, VGS = ±20V

Gate threshold Voltage, VGS(TH) = 2V

Drain to Source On Resistance, RDS(ON) = 0.24Ω

Gate to Drain “Miller” Charge, QGD = 62 nC.

Page 25

5.1.4 SELECTION OF DIODES:

The output diode must be selected to handle the peak current and the

reverse voltage. In a SEPIC, the diode peak current is the same as the switch

peak current IQ,Peak. The minimum peak reverse voltage the diode must

withstand is:

V904050(max)(max)1 =+=+= outinRD VVV

Similar to boost converter, the average output diode current is equal to

the output current. The power dissipation of the diode is equal to the output

current multiplied by the forward voltage drop of the diode. For very high

frequency operation Schottky diodes are recommended in order to minimize

the efficiency loss.

In our application, we have chosen the 6A4 MIC diode which is having

a current ratting of 6A and the forward voltage drop is less than 1 V. This is

not a Schottky diode. Due to unavailability of Schottky diode, we have used

this diode.

5.1.5 SELECTION OF TANK INDUCTOR:

The selection of SEPIC coupling capacitor Cs depends on the RMS

current which is given by:

A90.145

1402(min)

)(,1 =+×== +

inDoutoutRMSQ V

VVii

The SEPIC coupling capacitor must be rated for large RMS current

relative to the output power. The voltage ratting of the coupling capacitor must

be greater than the maximum input voltage. Tantalum and ceramic capacitors

are the best choice. Electrolytic capacitors work well for through-hole

applications where the size is not limited and they can accommodate the

required RMS current rating.

In our application, we have chosen a 0.47micro Farad/ 250 V.

Page 26

5.1.6 SELECTION OF TANK CAPACITOR:

As the resonance frequency of the tank circuit must be much higher

than switching frequency, we have chosen the following components.

fS = 50KHz, Lr = 22µH, Cr = 0.001 µF. Therefore, the resonance

frequency of the tank circuit can be found as:

KHz107301.0222

12

1 =×

==µµππ LrCr

fr

5.1.7 SELECTION OF LOAD:

The load has been chosen as 60W resistive. In fact a 60W incandescent

filament lamp is chosen for simplicity.

5.2 DESIGN OF GATE CONTROL CIRCUIT:

The gate control circuit has two PWM generators with same frequency.

In fact analog PWM generation technique has been used using Operational

amplifier (LF347). The PWM generation has two stages. The first stage

generates a rectangular wave which is integrated and a triangular wave is

achieved. In the second stage, the triangular wave is compared with a variable

voltage in an Op-amp comparator. The comparator output is the required

PWM signal whose duty cycle is controlled by the comparator base value i.e.

the analog voltage. It is done by a simple voltage divider circuit.

Two comparators have been used to create two independent PWM

signal with different duty cycle but having same frequency. The generated

PWM signal is buffered with the help of a CMOS NOT gate (CD 4049).Phase

of one PWM signal is inverted also in the buffer stage. The MOSFETs are

finally driven by the gate driver IC IR2110. It is a very high frequency two

channel gate driver. The output of the driver is in phase with the input voltage.

The upper channel output is with respect to a floating point which is helpful

for our circuit.

Page 27

5.2.1 SELCTION OF CONTROL VOLTAGE :

As the VGS of the MOSFETs IRFP460 is 20V and the threshold

voltage VTH is 4V, the control voltage is selected as 12V. The power

supply stage contains a rectifier with output voltage 15V which is

regulated to 12V with the linear voltage regulator LM7812. The output

is filtered with an electrolytic capacitor 220µF.

5.2.2 SELECTION OF OP-AMP:

To generate the PWM of frequency 50 KHz, the Op-amp

response must be very first i.e. the time to reach the output from zero to

saturation has to be extremely low. And we need 5 Op-amp. Therefore

LF347 has been chosen. It is a quad Op-amp and very fast acting. The

other specification can be found from its datasheet which is available in

the appendix at the end of this document. A virtual ground has been

created with the help of Op-amp and used to make the circuit with

single power supply operated instead of using two equal and opposite

power supply for the Op-amp.

5.2.3 SELECTION OF NOT GATE:

The NOT gate required here must have the Vcc = 12V to 15V.

The normal digital NOT gates are having the Vcc as 5V which is

incompatible with our logic level. Hence CMOS NOT gate was

required for our application which logic levels are suitable. Therefore,

CD4049 has been chosen which a versatile CMOS Hex NOT gate.

5.2.4 SELCTION OF MOSFET GATE DRIVER CIRCUIT

The gate driver required for our application must be very fast and

should have two channels. IR2110 suits best for our application. IR

2110 is made by International rectifier. It is an industrial standard, very

reliable high frequency gate driver DIP package. It also has enable and

automatic shutdown inputs. The shutdown input can be configured as

overload protection also.

Page 28

6. SOFTWARE SIMULATION

Page 29

Software Simulation is based on the process of imitating a real phenomenon

with a set of mathematical formulas. It is, essentially, a program that allows the user

to observe an operation through simulation without actually performing that

operation. Simulation software is used widely to design equipment so that the final

product will be as close to design specs as possible without expensive in process

modification. Electronics simulation software utilizes mathematical models to

replicate the behavior of an actual electronic device or circuit. Essentially, it is a

software program that converts a computer into a fully functioning electronics

laboratory.

Electronics simulators such as Circuit Logix integrate a schematic editor

SPICE simulator and on-screen waveforms and make “what-if” scenarios easy and

instant. By simulating a circuit’s behavior before actually building it greatly improves

efficiency and provides insights into the behavior and stability of electronics circuit

designs. Most simulators use a SPICE engine that simulates analog, digital and mixed

A/D circuits for exceptional power and accuracy. They also typically contain

extensive model and device libraries. While these simulators typically have printed

circuit board (PCB) export capabilities, they are not essential for design and testing

of circuits, which is the primary application of electronic circuit simulation.

The software simulation of the proposed PFC was one of the objective our

project and we have tried our level best to achieve the correct simulation result. For

this purpose we have used PSPICE software which is very helpful and convenient for

power electronic simulation.

Page 30

6.1 SIMULATION SOFTWARE:

PSPICE is a SPICE analog circuit and digital logic simulation software

that runs on personal computers, hence the first letter "P" in its name. It was

developed by MicroSim and is used in electronic design automation. MicroSim

was bought by OrCAD which was subsequently purchased by Cadence Design

Systems. The name is an acronym for Personal Simulation Program with

Integrated Circuit Emphasis. Today it has evolved into an analog mixed signal

simulator.

PSPICE was the first version of UC Berkeley SPICE available on a PC,

having been released in January 1984 to run on the original IBM PC. This initial

version ran from two 360KB floppy disks and later included a waveform viewer

and analyzer program called Probe. Subsequent versions improved in

performance and moved to DEC/VAX minicomputers, Sun workstations, the

Apple Macintosh, and the Microsoft Windows platform.

PSPICE, now developed towards more complex industry requirements, is

integrated in the complete systems design flow from OrCAD and Cadence

Allegro. It also supports many additional features, which were not available in the

original Berkeley code like Advanced Analysis with automatic optimization of a

circuit, encryption, a Model Editor, support of parameterized models, has several

internal solvers, auto-convergence and checkpoint restart, magnetic part editor

and Tabrizi core model for non-linear cores.

Page 31

6.2 SIMULATION RESULTS:

The following figure shows the schematic arrangement of the modified

SEPIC PFC which is drawn by OrCAD schematic capture for simulation.

Fig9: Modified SEPIC PFC with Gate driver

Page 32

Fig10: Simulated output of Gate control voltage

Fig11: Simulated output of drain to source current and voltage of main MOSFET

Page 33

Fig12: Simulated output of drain to source current and voltage of aux. MOSFET

Fig13:Simulated output of input line voltage and current; they are in same phase

Page 34

7. HARDWARE PROTO TYPE

IMPLEMENTATION AND

TESTINGS

Page 35

Fig14: The Gate Driver Circuit

Fig15: The Modified SEPIC PFC

Page 36

7.1 MEASUREMENTS OF KEY WAVEFORMS:

Fig16: The Gate voltage without load

Fig17: The Gate voltage with load

Page 37

Fig18: The drain to source voltage of main MOSFET

Fig19: The drain to source voltage of auxiliary MOSFET

Page 38

Fig20: The line voltage and line current

Fig21: The line voltage and line current

Page 39

7.2 MEASUREMENTS OF POWER FACTOR:

As from the waveforms of input line voltage and current it is evident that

they are exactly in same phase , the power factor is unity. Hence as whole, we

can comment the concept can be used for the real world rectifier driven loads to

improve the power factor.

7.3 MEASUREMENTS OF EFFICIENCY:

In the test condition the following parameters are measured as follows.

Vout= 40 V, Iout = 0.76 A , Vin= 50 V, Iin= 0.67 A

Hence, the Output power = 40×0.76=30.4 Watt.

The Input power = VICosΦ = 50×0.67×1= 33.5 Watt

Therefore efficiency,

%7.905.334.30 ===

InputOutputη

Page 40

8. CONCLUSION

Page 41

This paper has proposed a modified SEPIC-type soft-switching converter, which can

perform power factor correcting and achieve zero-voltage switching feature. As a result,

a unity power factor is obtained and efficiency is improved significantly. The output

voltage of the PFC can be smaller than ac-side voltage, reducing component stresses.

Therefore, the PFC is suitable for the applications of high line voltage and/or low output

voltage. The PFC configuration can be applied to DCM, BCM, or CCM operation for

power factor correction and ZVS. A prototype of the designed PFC for 40W 135V dc

load has been successfully implemented. The simulations and practical measurements

have verified the feasibility of the PFC.

Page 42

9. APPENDIX

Page 43

LM78XXSeries Voltage RegulatorsGeneral DescriptionThe LM78XX series of three terminal regulators is availablewith several fixed output voltages making them useful in awide range of applications. One of these is local on cardregulation, eliminating the distribution problems associatedwith single point regulation. The voltages available allowthese regulators to be used in logic systems, instrumenta-tion, HiFi, and other solid state electronic equipment. Al-though designed primarily as fixed voltage regulators thesedevices can be used with external components to obtain ad-justable voltages and currents.

The LM78XX series is available in an aluminum TO-3 pack-age which will allow over 1.0A load current if adequate heatsinking is provided. Current limiting is included to limit thepeak output current to a safe value. Safe area protection forthe output transistor is provided to limit internal power dissi-pation. If internal power dissipation becomes too high for theheat sinking provided, the thermal shutdown circuit takesover preventing the IC from overheating.

Considerable effort was expanded to make the LM78XX se-ries of regulators easy to use and minimize the number ofexternal components. It is not necessary to bypass the out-

put, although this does improve transient response. Input by-passing is needed only if the regulator is located far from thefilter capacitor of the power supply.

For output voltage other than 5V, 12V and 15V the LM117series provides an output voltage range from 1.2V to 57V.

Featuresn Output current in excess of 1An Internal thermal overload protectionn No external components requiredn Output transistor safe area protectionn Internal short circuit current limitn Available in the aluminum TO-3 package

Voltage RangeLM7805C 5V

LM7812C 12V

LM7815C 15V

Connection Diagrams

Metal Can PackageTO-3 (K)

Aluminum

DS007746-2

Bottom ViewOrder Number LM7805CK,LM7812CK or LM7815CK

See NS Package Number KC02A

Plastic PackageTO-220 (T)

DS007746-3

Top ViewOrder Number LM7805CT,LM7812CT or LM7815CT

See NS Package Number T03B

May 2000LM

78XX

Series

VoltageR

egulators

© 2000 National Semiconductor Corporation DS007746 www.national.com

Schematic

DS007746-1

LM78

XX

www.national.com 2

Absolute Maximum Ratings (Note 3)

If Military/Aerospace specified devices are required,please contact the National Semiconductor Sales Office/Distributors for availability and specifications.

Input Voltage(VO = 5V, 12V and 15V) 35V

Internal Power Dissipation (Note 1) Internally LimitedOperating Temperature Range (TA) 0˚C to +70˚C

Maximum Junction Temperature(K Package) 150˚C(T Package) 150˚C

Storage Temperature Range −65˚C to +150˚CLead Temperature (Soldering, 10 sec.)

TO-3 Package K 300˚CTO-220 Package T 230˚C

Electrical Characteristics LM78XXC (Note 2)0˚C ≤ TJ ≤ 125˚C unless otherwise noted.

Output Voltage 5V 12V 15V

Input Voltage (unless otherwise noted) 10V 19V 23V Units

Symbol Parameter Conditions Min Typ Max Min Typ Max Min Typ Max

VO Output Voltage Tj = 25˚C, 5 mA ≤ IO ≤ 1A 4.8 5 5.2 11.5 12 12.5 14.4 15 15.6 V

PD ≤ 15W, 5 mA ≤ IO ≤ 1A 4.75 5.25 11.4 12.6 14.25 15.75 V

VMIN ≤ VIN ≤ VMAX (7.5 ≤ VIN ≤ 20) (14.5 ≤ VIN ≤27)

(17.5 ≤ VIN ≤30)

V

∆VO Line Regulation IO = 500mA

Tj = 25˚C 3 50 4 120 4 150 mV

∆VIN (7 ≤ VIN ≤ 25) 14.5 ≤ VIN ≤ 30) (17.5 ≤ VIN ≤30)

V

0˚C ≤ Tj ≤ +125˚C 50 120 150 mV

∆VIN (8 ≤ VIN ≤ 20) (15 ≤ VIN ≤ 27) (18.5 ≤ VIN ≤30)

V

IO ≤ 1A Tj = 25˚C 50 120 150 mV

∆VIN (7.5 ≤ VIN ≤ 20) (14.6 ≤ VIN ≤27)

(17.7 ≤ VIN ≤30)

V

0˚C ≤ Tj ≤ +125˚C 25 60 75 mV

∆VIN (8 ≤ VIN ≤ 12) (16 ≤ VIN ≤ 22) (20 ≤ VIN ≤ 26) V

∆VO Load Regulation Tj = 25˚C 5 mA ≤ IO ≤ 1.5A 10 50 12 120 12 150 mV

250 mA ≤ IO ≤750 mA

25 60 75 mV

5 mA ≤ IO ≤ 1A, 0˚C ≤ Tj ≤+125˚C

50 120 150 mV

IQ Quiescent Current IO ≤ 1A Tj = 25˚C 8 8 8 mA

0˚C ≤ Tj ≤ +125˚C 8.5 8.5 8.5 mA

∆IQ Quiescent Current 5 mA ≤ IO ≤ 1A 0.5 0.5 0.5 mA

Change Tj = 25˚C, IO ≤ 1A 1.0 1.0 1.0 mA

VMIN ≤ VIN ≤ VMAX (7.5 ≤ VIN ≤ 20) (14.8 ≤ VIN≤ 27) (17.9 ≤ VIN ≤30)

V

IO ≤ 500 mA, 0˚C ≤ Tj ≤ +125˚C 1.0 1.0 1.0 mA

VMIN ≤ VIN ≤ VMAX (7 ≤ VIN ≤ 25) (14.5 ≤ VIN≤ 30) (17.5 ≤ VIN ≤30)

V

VN Output NoiseVoltage

TA =25˚C, 10 Hz ≤ f ≤ 100 kHz 40 75 90 µV

Ripple Rejection IO ≤ 1A, Tj = 25˚Cor

62 80 55 72 54 70 dB

f = 120 Hz IO ≤ 500 mA 62 55 54 dB

0˚C ≤ Tj ≤ +125˚C

VMIN ≤ VIN ≤ VMAX (8 ≤ VIN ≤ 18) (15 ≤ VIN ≤ 25) (18.5 ≤ VIN ≤28.5)

V

RO Dropout Voltage Tj = 25˚C, IOUT = 1A 2.0 2.0 2.0 V

Output Resistance f = 1 kHz 8 18 19 mΩ

LM78X

X

www.national.com3

Electrical Characteristics LM78XXC (Note 2) (Continued)

0˚C ≤ TJ ≤ 125˚C unless otherwise noted.

Output Voltage 5V 12V 15V

Input Voltage (unless otherwise noted) 10V 19V 23V Units

Symbol Parameter Conditions Min Typ Max Min Typ Max Min Typ Max

Short-CircuitCurrent

Tj = 25˚C 2.1 1.5 1.2 A

Peak OutputCurrent

Tj = 25˚C 2.4 2.4 2.4 A

Average TC ofVOUT

0˚C ≤ Tj ≤ +125˚C, IO = 5 mA 0.6 1.5 1.8 mV/˚C

VIN Input Voltage

Required toMaintain

Tj = 25˚C, IO ≤ 1A 7.5 14.6 17.7 V

Line Regulation

Note 1: Thermal resistance of the TO-3 package (K, KC) is typically 4˚C/W junction to case and 35˚C/W case to ambient. Thermal resistance of the TO-220 package(T) is typically 4˚C/W junction to case and 50˚C/W case to ambient.

Note 2: All characteristics are measured with capacitor across the input of 0.22 µF, and a capacitor across the output of 0.1µF. All characteristics except noise voltageand ripple rejection ratio are measured using pulse techniques (tw ≤ 10 ms, duty cycle ≤ 5%). Output voltage changes due to changes in internal temperature mustbe taken into account separately.

Note 3: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. For guaranteed specifications and the test conditions, see Elec-trical Characteristics.

LM78

XX

www.national.com 4

Typical Performance Characteristics

Maximum Average Power Dissipation

DS007746-5

Maximum Average Power Dissipation

DS007746-6

Peak Output Current

DS007746-7

Output Voltage (Normalized to 1V at T J = 25˚C)

DS007746-8

Ripple Rejection

DS007746-9

Ripple Rejection

DS007746-10

LM78X

X

www.national.com5

Typical Performance Characteristics (Continued)

Output Impedance

DS007746-11

Dropout Voltage

DS007746-12

Dropout Characteristics

DS007746-13

Quiescent Current

DS007746-14

Quiescent Current

DS007746-15

LM78

XX

www.national.com 6

Physical Dimensions inches (millimeters) unless otherwise noted

Aluminum Metal Can Package (KC)Order Number LM7805CK, LM7812CK or LM7815CK

NS Package Number KC02A

LM78X

X

www.national.com7

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORTDEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERALCOUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices orsystems which, (a) are intended for surgical implantinto the body, or (b) support or sustain life, andwhose failure to perform when properly used inaccordance with instructions for use provided in thelabeling, can be reasonably expected to result in asignificant injury to the user.

2. A critical component is any component of a lifesupport device or system whose failure to performcan be reasonably expected to cause the failure ofthe life support device or system, or to affect itssafety or effectiveness.

National SemiconductorCorporationAmericasTel: 1-800-272-9959Fax: 1-800-737-7018Email: [email protected]

National SemiconductorEurope

Fax: +49 (0) 180-530 85 86Email: [email protected]

Deutsch Tel: +49 (0) 69 9508 6208English Tel: +44 (0) 870 24 0 2171Français Tel: +33 (0) 1 41 91 8790

National SemiconductorAsia Pacific CustomerResponse GroupTel: 65-2544466Fax: 65-2504466Email: [email protected]

National SemiconductorJapan Ltd.Tel: 81-3-5639-7560Fax: 81-3-5639-7507

www.national.com

TO-220 Package (T)Order Number LM7805CT, LM7812CT or LM7815CT

NS Package Number T03B

LM78

XX

Ser

ies

Volta

geR

egul

ator

s

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.

TL/H/5647

LF147/LF347

Wid

eB

andw

idth

Quad

JFET

InputO

pera

tionalA

mplifie

rs

December 1994

LF147/LF347 Wide BandwidthQuad JFET Input Operational Amplifiers

General DescriptionThe LF147 is a low cost, high speed quad JFET input opera-

tional amplifier with an internally trimmed input offset volt-

age (BI-FET IITM technology). The device requires a low

supply current and yet maintains a large gain bandwidth

product and a fast slew rate. In addition, well matched high

voltage JFET input devices provide very low input bias and

offset currents. The LF147 is pin compatible with the stan-

dard LM148. This feature allows designers to immediately

upgrade the overall performance of existing LF148 and

LM124 designs.

The LF147 may be used in applications such as high speed

integrators, fast D/A converters, sample-and-hold circuits

and many other circuits requiring low input offset voltage,

low input bias current, high input impedance, high slew rate

and wide bandwidth. The device has low noise and offset

voltage drift.

FeaturesY Internally trimmed offset voltage 5 mV maxY Low input bias current 50 pAY Low input noise current 0.01 pA/0HzY Wide gain bandwidth 4 MHzY High slew rate 13 V/msY Low supply current 7.2 mAY High input impedance 1012XY Low total harmonic distortion AVe10, k0.02%

RLe10k, VOe20 Vp-p, BWe20 Hzb20 kHzY Low 1/f noise corner 50 HzY Fast settling time to 0.01% 2 ms

Simplified Schematic

(/4 Quad

TL/H/5647–13

Connection Diagram

Dual-In-Line Package

TL/H/5647–1

Top View

Order Number LF147J, LF347M, LF347BN,

LF347N, LF147D/883 or LF147J/883*See NS Package Number D14E, J14A, M14A or N14A

*Available per SMD Ý8102306, JM38510/11906.

BI-FET IITM is a trademark of National Semiconductor Corporation.

C1995 National Semiconductor Corporation RRD-B30M115/Printed in U. S. A.

Absolute Maximum RatingsIf Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales

Office/Distributors for availability and specifications.

LF147 LF347B/LF347

Supply Voltage g22V g18V

Differential Input Voltage g38V g30V

Input Voltage Range g19V g15V

(Note 1)

Output Short Circuit Continuous Continuous

Duration (Note 2)

Power Dissipation 900 mW 1000 mW

(Notes 3 and 9)

Tj max 150§C 150§CijA

Cavity DIP (D) Package 80§C/W

Ceramic DIP (J) Package 70§C/W

Plastic DIP (N) Package 75§C/W

Surface Mount Narrow (M) 100§C/W

Surface Mount Wide (WM) 85§C/W

LF147 LF347B/LF347

Operating Temperature (Note 4) (Note 4)

Range

Storage Temperature

Range b65§CsTAs150§CLead Temperature

(Soldering, 10 sec.) 260§C 260§CSoldering Information


Soldering (10 seconds) 260§CSmall Outline Package

Vapor Phase (60 seconds) 215§CInfrared (15 seconds) 220§C

See AN-450 ‘‘Surface Mounting Methods and Their Effect

on Product Reliability’’ for other methods of soldering sur-

face mount devices.

ESD Tolerance (Note 10) 900V

DC Electrical Characteristics (Note 5)

Symbol Parameter ConditionsLF147 LF347B LF347

UnitsMin Typ Max Min Typ Max Min Typ Max

VOS Input Offset Voltage RSe10 kX, TAe25§C 1 5 3 5 5 10 mV

Over Temperature 8 7 13 mV

DVOS/DT Average TC of Input Offset RSe10 kX 10 10 10 mV/§CVoltage

IOS Input Offset Current Tje25§C, (Notes 5, 6) 25 100 25 100 25 100 pA

Over Temperature 25 4 4 nA

IB Input Bias Current Tje25§C, (Notes 5, 6) 50 200 50 200 50 200 pA

Over Temperature 50 8 8 nA

RIN Input Resistance Tje25§C 1012 1012 1012 X

AVOL Large Signal Voltage Gain VSeg15V, TAe25§C 50 100 50 100 25 100 V/mV

VOeg10V, RLe2 kX

Over Temperature 25 25 15 V/mV

VO Output Voltage Swing VSeg15V, RLe10 kX g12 g13.5 g12 g13.5 g12 g13.5 V

VCM Input Common-Mode VoltageVSeg15V g11

a15g11

a15g11

a15 V

Range b12 b12 b12 V

CMRR Common-Mode Rejection Ratio RSs10 kX 80 100 80 100 70 100 dB

PSRR Supply Voltage Rejection Ratio (Note 7) 80 100 80 100 70 100 dB

IS Supply Current 7.2 11 7.2 11 7.2 11 mA

2

AC Electrical Characteristics (Note 5)

Symbol Parameter ConditionsLF147 LF347B LF347

UnitsMin Typ Max Min Typ Max Min Typ Max

Amplifier to Amplifier Coupling TAe25§C, b120 b120 b120 dB

fe1 Hzb20 kHz

(Input Referred)

SR Slew Rate VSeg15V, TAe25§C 8 13 8 13 8 13 V/ms

GBW Gain-Bandwidth Product VSeg15V, TAe25§C 2.2 4 2.2 4 2.2 4 MHz

en Equivalent Input Noise Voltage TAe25§C, RSe100X, 20 20 20 nV/0Hz

fe1000 Hz

in Equivalent Input Noise Current Tje25§C, fe1000 Hz 0.01 0.01 0.01 pA/0Hz

Note 1: Unless otherwise specified the absolute maximum negative input voltage is equal to the negative power supply voltage.

Note 2: Any of the amplifier outputs can be shorted to ground indefinitely, however, more than one should not be simultaneously shorted as the maximum junction

temperature will be exceeded.

Note 3: For operating at elevated temperature, these devices must be derated based on a thermal resistance of ijA.

Note 4: The LF147 is available In the military temperature range b55§CsTAs125§C, while the LF347B and the LF347 are available in the commercial temperature

range 0§CsTAs70§C. Junction temperature can rise to Tj max e 150§C.

Note 5: Unless otherwise specified the specifications apply over the full temperature range and for VSeg20V for the LF147 and for VSeg15V for the LF347B/

LF347. VOS, IB, and IOS are measured at VCMe0.

Note 6: The input bias currents are junction leakage currents which approximately double for every 10§C increase in the junction temperature, Tj. Due to limited

production test time, the input bias currents measured are correlated to junction temperature. In normal operation the junction temperature rises above the ambient

temperature as a result of internal power dissipation, PD. TjeTAaijA PD where ijA is the thermal resistance from junction to ambient. Use of a heat sink is

recommended if input bias current is to be kept to a minimum.

Note 7: Supply voltage rejection ratio is measured for both supply magnitudes increasing or decreasing simultaneously in accordance with common practice from

VS e g 5V to g15V for the LF347 and LF347B and from VS e g20V to g5V for the LF147.

Note 8: Refer to RETS147X for LF147D and LF147J military specifications.

Note 9: Max. Power Dissipation is defined by the package characteristics. Operating the part near the Max. Power Dissipation may cause the part to operate

outside guaranteed limits.

Note 10: Human body model, 1.5 kX in series with 100 pF.

3

Typical Performance Characteristics

Input Bias Current Input Bias Current Supply Current

Positive Common-Mode

Input Voltage Limit

Negative Common-Mode

Input Voltage Limit Positive Current Limit

Negative Current Limit Output Voltage Swing Output Voltage Swing

Gain Bandwidth Bode Plot Slew Rate

TL/H/5647–2

4

Typical Performance Characteristics (Continued)

Distortion vs Frequency

Undistorted Output Voltage

Swing

Open Loop Frequency

Response

Common-Mode Rejection

Ratio

Power Supply Rejection

Ratio

Equivalent Input Noise

Voltage

Open Loop Voltage Gain Output Impedance Inverter Settling Time

TL/H/5647–3

5

Pulse Response RLe2 kX, CLe10 pF

Small Signal Inverting

TL/H/5647–4

Small Signal Non-Inverting

TL/H/5647–5

Large Signal Inverting

TL/H/5647–6

Large Signal Non-Inverting

TL/H/5647–7

Current Limit (RLe100X)

TL/H/5647–8

Application HintsThe LF147 is an op amp with an internally trimmed input

offset voltage and JFET input devices (BI-FET IITM). These

JFETs have large reverse breakdown voltages from gate to

source and drain eliminating the need for clamps across the

inputs. Therefore, large differential input voltages can easily

be accommodated without a large increase in input current.

The maximum differential input voltage is independent of

the supply voltages. However, neither of the input voltages

should be allowed to exceed the negative supply as this will

cause large currents to flow which can result in a destroyed

unit.

Exceeding the negative common-mode limit on either input

will force the output to a high state, potentially causing a

reversal of phase to the output. Exceeding the negative

common-mode limit on both inputs will force the amplifier

6

Application Hints (Continued)

output to a high state. In neither case does a latch occur

since raising the input back within the common-mode range

again puts the input stage and thus the amplifier in a normal

operating mode.

Exceeding the positive common-mode limit on a single input

will not change the phase of the output; however, if both

inputs exceed the limit, the output of the amplifier will be

forced to a high state.

The amplifiers will operate with a common-mode input volt-

age equal to the positive supply; however, the gain band-

width and slew rate may be decreased in this condition.

When the negative common-mode voltage swings to within

3V of the negative supply, an increase in input offset voltage

may occur.

Each amplifier is individually biased by a zener reference

which allows normal circuit operation on g4.5V power sup-

plies. Supply voltages less than these may result in lower

gain bandwidth and slew rate.

The LF147 will drive a 2 kX load resistance to g10V over

the full temperature range. If the amplifier is forced to drive

heavier load currents, however, an increase in input offset

voltage may occur on the negative voltage swing and finally

reach an active current limit on both positive and negative

swings.

Precautions should be taken to ensure that the power sup-

ply for the integrated circuit never becomes reversed in po-

larity or that the unit is not inadvertently installed backwards

in a socket as an unlimited current surge through the result-

ing forward diode within the IC could cause fusing of the

internal conductors and result in a destroyed unit.

As with most amplifiers, care should be taken with lead

dress, component placement and supply decoupling in or-

der to ensure stability. For example, resistors from the out-

put to an input should be placed with the body close to the

input to minimize ‘‘pick-up’’ and maximize the frequency of

the feedback pole by minimizing the capacitance from the

input to ground.

A feedback pole is created when the feedback around any

amplifier is resistive. The parallel resistance and capaci-

tance from the input of the device (usually the inverting in-

put) to AC ground set the frequency of the pole. In many

instances the frequency of this pole is much greater than

the expected 3 dB frequency of the closed loop gain and

consequently there is negligible effect on stability margin.

However, if the feedback pole is less than approximately 6

times the expected 3 dB frequency a lead capacitor should

be placed from the output to the input of the op amp. The

value of the added capacitor should be such that the RC

time constant of this capacitor and the resistance it parallels

is greater than or equal to the original feedback pole time

constant.

Detailed Schematic

TL/H/5647–9

7

Typical ApplicationsDigitally Selectable Precision Attenuator

All resistors 1% tolerance

TL/H/5647–10

# Accuracy of better than 0.4% with standard 1% value resistors

# No offset adjustment necessary

# Expandable to any number of stages

# Very high input impedance

Long Time Integrator with Reset, Hold and Starting Threshold Adjustment

TL/H/5647–11

# VOUT starts from zero and is equal to the integral of the input voltage with respect to the threshold voltage:

VOUTe

1

RC#t

0(VINbVTH)dt

# Output starts when VINtVTH

# Switch S1 permits stopping and holding any output value

# Switch S2 resets system to zero

A1 A2 A3VO

Attenuation

0 0 0 0

0 0 1 b1 dB

0 1 0 b2 dB

0 1 1 b3 dB

1 0 0 b4 dB

1 0 1 b5 dB

1 1 0 b6 dB

1 1 1 b7 dB

8

Typical Applications (Continued)

Universal State Variable Filter

TL/H/5647–12

For circuit shown:

foe3 kHz, fNOTCHe9.5 kHz

Qe3.4

Passband gain:

HighpassÐ0.1

BandpassÐ1

LowpassÐ1

NotchÐ10

# focQs200 kHz

# 10V peak sinusoidal output swing without slew limiting to 200 kHz

# See LM148 data sheet for design equations

9

Physical Dimensions inches (millimeters)

Hermetic Dual-In-Line Package (D)

Order Number LF147D/883

NS Package Number D14E

10

Physical Dimensions inches (millimeters) (Continued)

Ceramic Dual-In-Line Package (J)

Order Number LF147J or LF147J/883

NS Package Number J14A

S.O. Package (M)

Order Number LF347M

NS Package Number M14A

11

LF147/LF347

Wid

eB

andw

idth

Quad

JFET

InputO

pera

tionalA

mplifiers

Physical Dimensions inches (millimeters) (Continued)

Molded Dual-In-Line Package (N)

Order Number LF347BN or LF347N

NS Package Number N14A

LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL

SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or 2. A critical component is any component of a life

systems which, (a) are intended for surgical implant support device or system whose failure to perform can

into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life

failure to perform, when properly used in accordance support device or system, or to affect its safety or

with instructions for use provided in the labeling, can effectiveness.

be reasonably expected to result in a significant injury

to the user.

National Semiconductor National Semiconductor National Semiconductor National SemiconductorCorporation Europe Hong Kong Ltd. Japan Ltd.1111 West Bardin Road Fax: (a49) 0-180-530 85 86 13th Floor, Straight Block, Tel: 81-043-299-2309Arlington, TX 76017 Email: cnjwge@ tevm2.nsc.com Ocean Centre, 5 Canton Rd. Fax: 81-043-299-2408Tel: 1(800) 272-9959 Deutsch Tel: (a49) 0-180-530 85 85 Tsimshatsui, KowloonFax: 1(800) 737-7018 English Tel: (a49) 0-180-532 78 32 Hong Kong

Fran3ais Tel: (a49) 0-180-532 93 58 Tel: (852) 2737-1600Italiano Tel: (a49) 0-180-534 16 80 Fax: (852) 2736-9960


This datasheet has been download from:

www.datasheetcatalog.com

Datasheets for electronics components.

http://www.datasheetcatalog.com



Document Number: 91237 www.vishay.comS-81360-Rev. A, 28-Jul-08 1

Power MOSFET

IRFP460, SiHFP460Vishay Siliconix

FEATURES• Dynamic dV/dt Rating

• Repetitive Avalanche Rated

• Isolated Central Mounting Hole

• Fast Switching

• Ease of Paralleling

• Simple Drive Requirements

• Lead (Pb)-free Available

DESCRIPTIONThird generation Power MOSFETs from Vishay provide thedesigner with the best combination of fast switching,ruggedized device design, low on-resistance andcost-effectiveness. The TO-247 package is preferred for commercial-industrialapplications where higher power levels preclude the use ofTO-220 devices. The TO-247 is similar but superior to theearlier TO-218 package because its isolated mounting hole.It also provides greater creepage distances between pins tomeet the requirements of most safety specifications.

Notesa. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).b. VDD = 50 V, starting TJ = 25 °C, L = 4.3 mH, RG = 25 Ω, IAS = 20 A (see fig. 12).c. ISD ≤ 20 A, dI/dt ≤ 160 A/µs, VDD ≤ VDS, TJ ≤ 150 °C.d. 1.6 mm from case.

PRODUCT SUMMARYVDS (V) 500

RDS(on) (Ω) VGS = 10 V 0.27

Qg (Max.) (nC) 210

Qgs (nC) 29

Qgd (nC) 110

Configuration Single

N-Channel MOSFET

G

D

S

TO-247

GD

S

Available

RoHS*COMPLIANT

ORDERING INFORMATIONPackage TO-247

Lead (Pb)-freeIRFP460PbFSiHFP460-E3

SnPbIRFP460SiHFP460

ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise notedPARAMETER SYMBOL LIMIT UNIT

Drain-Source Voltage VDS 500V

Gate-Source Voltage VGS ± 20

Continuous Drain Current VGS at 10 VTC = 25 °C

ID20

ATC = 100 °C 13Pulsed Drain Currenta IDM 80Linear Derating Factor 2.2 W/°C Single Pulse Avalanche Energyb EAS 960 mJ Repetitive Avalanche Currenta IAR 20 A Repetitive Avalanche Energya EAR 28 mJ Maximum Power Dissipation TC = 25 °C PD 280 W Peak Diode Recovery dV/dtc dV/dt 3.5 V/ns Operating Junction and Storage Temperature Range TJ, Tstg - 55 to + 150

°C Soldering Recommendations (Peak Temperature) for 10 s 300d

Mounting Torque 6-32 or M3 screw10 lbf · in1.1 N · m

* Pb containing terminations are not RoHS compliant, exemptions may apply

www.vishay.com Document Number: 912372 S-81360-Rev. A, 28-Jul-08


Notesa. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).b. Pulse width ≤ 300 µs; duty cycle ≤ 2 %.

THERMAL RESISTANCE RATINGSPARAMETER SYMBOL TYP. MAX. UNIT

Maximum Junction-to-Ambient RthJA - 40

°C/WCase-to-Sink, Flat, Greased Surface RthCS 0.24 -

Maximum Junction-to-Case (Drain) RthJC - 0.45

SPECIFICATIONS TJ = 25 °C, unless otherwise notedPARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT

Static

Drain-Source Breakdown Voltage VDS VGS = 0 V, ID = 250 µA 500 - - V

VDS Temperature Coefficient ΔVDS/TJ Reference to 25 °C, ID = 1 mA - 0.63 - V/°C

Gate-Source Threshold Voltage VGS(th) VDS = VGS, ID = 250 µA 2.0 - 4.0 V

Gate-Source Leakage IGSS VGS = ± 20 V - - ± 100 nA

Zero Gate Voltage Drain Current IDSS VDS = 500 V, VGS = 0 V - - 25

µA VDS = 400 V, VGS = 0 V, TJ = 125 °C - - 250

Drain-Source On-State Resistance RDS(on) VGS = 10 V ID = 12 Ab - - 0.27 Ω

Forward Transconductance gfs VDS = 50 V, ID = 12 Ab 13 - - S

Dynamic

Input Capacitance Ciss VGS = 0 V, VDS = 25 V,

f = 1.0 MHz, see fig. 5

- 4200 -

pFOutput Capacitance Coss - 870 -

Reverse Transfer Capacitance Crss - 350 -

Total Gate Charge Qg

VGS = 10 V ID = 20 A, VDS = 400 V see fig. 6 and 13b

- - 210

nC Gate-Source Charge Qgs - - 29

Gate-Drain Charge Qgd - - 110

Turn-On Delay Time td(on)

VDD = 250 V, ID = 20 A ,RG = 4.3 Ω, RD = 13 Ω, see fig. 10b

- 18 -

nsRise Time tr - 59 -

Turn-Off Delay Time td(off) - 110 -

Fall Time tf - 58 -

Internal Drain Inductance LD Between lead,6 mm (0.25") from package and center of die contact

- 5.0 -nH

Internal Source Inductance LS - 13 -

Drain-Source Body Diode Characteristics

Continuous Source-Drain Diode Current ISMOSFET symbolshowing the integral reversep - n junction diode

- - 20A

Pulsed Diode Forward Currenta ISM - - 80

Body Diode Voltage VSD TJ = 25 °C, IS = 20 A, VGS = 0 Vb - - 1.8 V

Body Diode Reverse Recovery Time trrTJ = 25 °C, IF = 20A, dI/dt = 100 A/µsb

- 570 860 ns

Body Diode Reverse Recovery Charge Qrr - 5.7 8.6 µC

Forward Turn-On Time ton Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)

D

S

G

S

D

G



TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted

Fig. 1 - Typical Output Characteristics, TC = 25 °C

Fig. 2 - Typical Output Characteristics, TC = 150 °C

Fig. 3 - Typical Transfer Characteristics

Fig. 4 - Normalized On-Resistance vs. Temperature

VDS, Drain-to-Source Voltage (V)

I D, D

rain

Cur

rent

(A

)

20 µs Pulse WidthTC = 25 °C

4.5 V

101

100

100 101

Bottom

TopVGS 15 V 10 V8.0 V7.0 V6.0 V5.5 V5.0 V4.5 V

91237_01

4.5 V

Bottom

TopVGS

15 V10 V8.0 V7.0 V6.0 V5.5 V5.0 V4.5 V

20 µs Pulse WidthTC = 150 °C

101

100

100 101

I D, D

rain

Cur

rent

(A

)

91237_02 VDS, Drain-to-Source Voltage (V)

91237_03

25 °C

150 °C

20 µs Pulse WidthVDS = 50 V

101

100

I D, D

rain

Cur

rent

(A

)

VGS, Gate-to-Source Voltage (V)

5 6 7 8 9 104

91237_04

ID = 20 AVGS = 10 V

3.5

0.0

0.5

1.0

1.5

2.0

2.5

- 60 - 40 - 20 0 20 40 60 80 100 120 140 160

TJ, Junction Temperature (°C)

RD

S(o

n), D

rain

-to-

Sou

rce

On

Res

ista

nce

(Nor

mal

ized

)

3.0



Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage

Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage

Fig. 7 - Typical Source-Drain Diode Forward Voltage

Fig. 8 - Maximum Safe Operating Area

91237_05

10 000

8000

6000

4000

0

2000

100 101

Cap

acita

nce

(pF

)


Ciss

Crss

Coss

VGS = 0 V, f = 1 MHzCiss = Cgs + Cgd, Cds ShortedCrss = CgdCoss = Cds + Cgd

91237_06

ID = 20 A

VDS = 250 V

For test circuitsee figure 13

VDS = 100 V

VDS = 400 V

QG, Total Gate Charge (nC)

VG

S, G

ate-

to-S

ourc

e V

olta

ge (

V)

20

16

12

8

0

4

0 40 20016012080

91237_07

102

VSD, Source-to-Drain Voltage (V)

I SD, R

ever

se D

rain

Cur

rent

(A

)

0.6 1.21.00.8 1.61.4

25 °C

150 °C

VGS = 0 V101

1.8 2.0

91237_08

10 µs

100 µs

1 ms

10 ms

Operation in this area limitedby RDS(on)

TC = 25 °CTJ = 150 °CSingle Pulse

I D, D

rain

Cur

rent

(A

)

103

2

5

2

5

2

5


1 10 102 1032 5 2 5 2 5

1

10

102



Fig. 9 - Maximum Drain Current vs. Case Temperature

Fig. 10a - Switching Time Test Circuit

Fig. 10b - Switching Time Waveforms

Fig. 11a - Maximum Effective Transient Thermal Impedance, Junction-to-Case

Fig. 12a - Unclamped Inductive Test Circuit Fig. 12b - Unclamped Inductive Waveforms

I D, D

rain

Cur

rent

(A

)

TC, Case Temperature (°C)

0

8

12

16

20

25 1501251007550

4

91237_09

Pulse width ≤ 1 µsDuty factor ≤ 0.1 %

RD

VGS

RG

D.U.T.

10 V

+-

VDS

VDD

VDS

90 %

10 %VGS

td(on) tr td(off) tf

91237_11

0 - 0.5

0.2

0.1

0.05

0.01

Single Pulse(Thermal Response)

PDM

t1t2

Notes:1. Duty Factor, D = t1/t22. Peak Tj = PDM x ZthJC + TC

0.02

The

rmal

Res

pons

e (Z

thJC

)

1

0.1

10-3

t1, Rectangular Pulse Duration (S)

10-5 10-4 10-3 10-2 0.1 1 10

10-2

RG

IAS

0.01 Ωtp

D.U.T

LVDS

+

-VDD

A10 V

Vary tp to obtainrequired IAS

IAS

VDS

VDD

VDS

tp



Fig. 12c - Maximum Avalanche Energy vs. Drain Current

Fig. 13a - Basic Gate Charge Waveform

Fig. 13b - Gate Charge Test Circuit

91237_12c

Bottom

TopID

8.9 A 13 A 20 A

VDD = 50 V

2400

0

400

800

1200

1600

2000

25 1501251007550

Starting TJ, Junction Temperature (°C)

EA

S, S

ingl

e P

ulse

Ene

rgy

(mJ)

QGS QGD

QG

VG

Charge

10 V

D.U.T.

3 mA

VGS

VDS

IG ID

0.3 µF0.2 µF

50 kΩ

12 V

Current regulator

Current sampling resistors

Same type as D.U.T.

+

-



Fig. 14 - For N-Channel

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for SiliconTechnology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, andreliability data, see http://www.vishay.com/ppg?91237.

P.W.Period

dI/dt

Diode recoverydV/dt

Ripple ≤ 5 %

Body diode forward dropRe-appliedvoltage

Reverserecoverycurrent

Body diode forwardcurrent

VGS = 10 V*

VDD

ISD

Driver gate drive

D.U.T. ISD waveform

D.U.T. VDS waveform

Inductor current

D = P.W.Period

+

-

+

+

+-

-

-

* VGS = 5 V for logic level devices

Peak Diode Recovery dV/dt Test Circuit

VDD

• dV/dt controlled by RG• Driver same type as D.U.T.• ISD controlled by duty factor "D"• D.U.T. - device under test

D.U.T. Circuit layout considerations • Low stray inductance

• Ground plane • Low leakage inductance

current transformer

RG

Document Number: 91000 www.vishay.comRevision: 18-Jul-08 1

Disclaimer

Legal Disclaimer NoticeVishay

All product specifications and data are subject to change without notice.

Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf(collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained hereinor in any other disclosure relating to any product.

Vishay disclaims any and all liability arising out of the use or application of any product described herein or of anyinformation provided herein to the maximum extent permitted by law. The product specifications do not expand orotherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressedtherein, which apply to these products.

No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by thisdocument or by any conduct of Vishay.

The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications unlessotherwise expressly indicated. Customers using or selling Vishay products not expressly indicated for use in suchapplications do so entirely at their own risk and agree to fully indemnify Vishay for any damages arising or resultingfrom such use or sale. Please contact authorized Vishay personnel to obtain written terms and conditions regardingproducts designed for such applications.

Product names and markings noted herein may be trademarks of their respective owners.

TL/F/5971

CD

4049U

BM

/C

D4049U

BC

Hex

Invertin

gB

uffe

rC

D4050B

M/C

D4050B

CH

ex

Non-In

vertin

gB

uffe

r

March 1988

CD4049UBM/CD4049UBC Hex Inverting BufferCD4050BM/CD4050BC Hex Non-Inverting Buffer

General DescriptionThese hex buffers are monolithic complementary MOS

(CMOS) integrated circuits constructed with N- and P-chan-

nel enhancement mode transistors. These devices feature

logic level conversion using only one supply voltage (VDD).

The input signal high level (VIH) can exceed the VDD supply

voltage when these devices are used for logic level conver-

sions. These devices are intended for use as hex buffers,

CMOS to DTL/TTL converters, or as CMOS current drivers,

and at VDD e 5.0V, they can drive directly two DTL/TTL

loads over the full operating temperature range.

FeaturesY Wide supply voltage range 3.0V to 15VY Direct drive to 2 TTL loads at 5.0V over full tempera-

ture rangeY High source and sink current capabilityY Special input protection permits input voltages greater

than VDD

ApplicationsY CMOS hex inverter/bufferY CMOS to DTL/TTL hex converterY CMOS current ‘‘sink’’ or ‘‘source’’ driverY CMOS high-to-low logic level converter

Connection Diagrams

CD4049UBM/CD4049UBC


TL/F/5971–1

Top View

Order Number CD4049UB or CD4049B

CD4050BM/CD4050BC


TL/F/5971–2

Top View

Order Number CD4050UB or CD4050B

C1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.

Absolute Maximum Ratings (Notes 1 & 2)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales

Office/Distributors for availability and specifications.

Supply Voltage (VDD) b0.5V to a18V

Input Voltage (VIN) b0.5V to a18V

Voltage at Any Output Pin (VOUT) b0.5V to VDD a 0.5V

Storage Temperature Range (TS) b65§C to a150§CPower Dissipation (PD)

Dual-In-Line 700 mW

Small Outline 500 mW

Lead Temperature (TL)

(Soldering, 10 seconds) 260§C

Recommended OperatingConditions (Note 2)

Supply Voltage (VDD) 3V to 15V

Input Voltage (VIN) 0V to 15V

Voltage at Any Output Pin (VOUT) 0 to VDD

Operating Temperature Range (TA)

CD4049UBM, CD4050BM b55§C to a125§CCD4049UBC, CD4050BC b40§C to a85§C

DC Electrical Characteristics CD4049M/CD4050BM (Note 2)

Symbol Parameter Conditionsb55§C a25§C a125§C

UnitsMin Max Min Typ Max Min Max

IDD Quiescent Device Current VDD e 5V 1.0 0.01 1.0 30 mA

VDD e 10V 2.0 0.01 2.0 60 mA

VDD e 15V 4.0 0.03 4.0 120 mA

VOL Low Level Output Voltage VIH e VDD, VIL e 0V,

lIOl k 1 mA

VDD e 5V 0.05 0 0.05 0.05 V

VDD e 10V 0.05 0 0.05 0.05 V

VDD e 15V 0.05 0 0.05 0.05 V

VOH High Level Output Voltage VIH e VDD, VIL e 0V,

lIOl k 1 mA

VDD e 5V 4.95 4.95 5 4.95 V

VDD e 10V 9.95 9.95 10 9.95 V

VDD e 15V 14.95 14.95 15 14.95 V

VIL Low Level Input Voltage lIOl k 1 mA

(CD4050BM Only) VDD e 5V, VO e 0.5V 1.5 2.25 1.5 1.5 V

VDD e 10V, VO e 1V 3.0 4.5 3.0 3.0 V

VDD e 15V, VO e 1.5V 4.0 6.75 4.0 4.0 V


(CD4049UBM Only) VDD e 5V, VO e 4.5V 1.0 1.5 1.0 1.0 V

VDD e 10V, VO e 9V 2.0 2.5 2.0 2.0 V

VDD e 15V, VO e 13.5V 3.0 3.5 3.0 3.0 V

VIH High Level Input Voltage lIOl k 1 mA

(CD4050BM Only) VDD e 5V, VO e 4.5V 3.5 3.5 2.75 3.5 V

VDD e 10V, VO e 9V 7.0 7.0 5.5 7.0 V

VDD e 15V, VO e 13.5V 11.0 11.0 8.25 11.0 V


(CD4049UBM Only) VDD e 5V, VO e 0.5V 4.0 4.0 3.5 4.0 V

VDD e 10V, VO e 1V 8.0 8.0 7.5 8.0 V

VDD e 15V, VO e 1.5V 12.0 12.0 11.5 12.0 V

IOL Low Level Output Current VIH e VDD, VIL e 0V

(Note 3) VDD e 5V, VO e 0.4V 5.6 4.6 5 3.2 mA

VDD e 10V, VO e 0.5V 12 9.8 12 6.8 mA

VDD e 15V, VO e 1.5V 35 29 40 20 mA

Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed; they are not meant to imply that the devices

should be operated at these limits. The table of ‘‘Recommended Operating Conditions’’ and ‘‘Electrical Characteristics’’ provides conditions for actual device

operation.

Note 2: VSS e 0V unless otherwise specified.

Note 3: These arepeak output current capabilities. Continuous output current is rated at 12 mA maximum. The output current should not be allowed to exceed this

value for extended periods of time. IOL and IOH are tested one output at a time.

2

DC Electrical Characteristics CD4049M/CD4050BM (Note 2) (Continued)



IOH High Level Output Current VIH e VDD, VIL e 0V

(Note 3) VDD e 5V, VO e 4.6V b1.3 b1.1 b1.6 b0.72 mA

VDD e 10V, VO e 9.5V b2.6 b2.2 b3.6 b1.5 mA

VDD e 15V, VO e 13.5V b8.0 b7.2 b12 b5.0 mA

IIN Input Current VDD e 15V, VIN e 0V b0.1 b10b5 b0.1 b1.0 mA

VDD e 15V, VIN e 15V 0.1 10b5 0.1 1.0 mA



operation.




DC Electrical Characteristics CD4049UBC/CD4050BC (Note 2)



IDD Quiescent Device Current VDD e 5V 4 0.03 4.0 30 mA

VDD e 10V 8 0.05 8.0 60 mA

VDD e 15V 16 0.07 16.0 120 mA

VOL Low Level Output Voltage VIH e VDD, VIL e 0V,

lIOl k 1 mA

VDD e 5V 0.05 0 0.05 0.05 V

VDD e 10V 0.05 0 0.05 0.05 V

VDD e 15V 0.05 0 0.05 0.05 V

VOH High Level Output Voltage VIH e VDD, VIL e 0V,

lIOl k 1 mA

VDD e 5V 4.95 4.95 5 4.95 V

VDD e 10V 9.95 9.95 10 9.95 V

VDD e 15V 14.95 14.95 15 14.95 V


(CD4050BC Only) VDD e 5V, VO e 0.5V 1.5 2.25 1.5 1.5 V

VDD e 10V, VO e 1V 3.0 4.5 3.0 3.0 V

VDD e 15V, VO e 1.5V 4.0 6.75 4.0 4.0 V


(CD4049UBC Only) VDD e 5V, VO e 4.5V 1.0 1.5 1.0 1.0 V

VDD e 10V, VO e 9V 2.0 2.5 2.0 2.0 V

VDD e 15V, VO e 13.5V 3.0 3.5 3.0 3.0 V


(CD4050BC Only) VDD e 5V, VO e 4.5V 3.5 3.5 2.75 3.5 V

VDD e 10V, VO e 9V 7.0 7.0 5.5 7.0 V

VDD e 15V, VO e 13.5V 11.0 11.0 8.25 11.0 V


(CD4049UBC Only) VDD e 5V, VO e 0.5V 4.0 4.0 3.5 4.0 V

VDD e 10V, VO e 1V 8.0 8.0 7.5 8.0 V

VDD e 15V, VO e 1.5V 12.0 12.0 11.5 12.0 V



operation.




3

DC Electrical Characteristics CD4049UBC/CD4050BC (Note 2) (Continued)



IOL Low Level Output Current VIH e VDD, VIL e 0V

(Note 3) VDD e 5V, VO e 0.4V 4.6 4.0 5 3.2 mA

VDD e 10V, VO e 0.5V 9.8 8.5 12 6.8 mA

VDD e 15V, VO e 1.5V 29 25 40 20 mA

IOH High Level Output Current VIH e VDD, VIL e 0V

(Note 3) VDD e 5V, VO e 4.6V b1.0 b0.9 b1.6 b0.72 mA

VDD e 10V, VO e 9.5V b2.1 b1.9 b3.6 b1.5 mA

VDD e 15V, VO e 13.5V b7.1 b6.2 b12 b5 mA

IIN Input Current VDD e 15V, VIN e 0V b0.3 b0.3 b10b5 b1.0 mA

VDD e 15V, VIN e 15V 0.3 0.3 10b5 1.0 mA

AC Electrical Characteristics* CD4049UBM/CD4049UBC

TA e 25§C, CL e 50 pF, RL e 200k, tr e tf e 20 ns, unless otherwise specified

Symbol Parameter Conditions Min Typ Max Units

tPHL Propagation Delay Time VDD e 5V 30 65 ns

High-to-Low Level VDD e 10V 20 40 ns

VDD e 15V 15 30 ns

tPLH Propagation Delay Time VDD e 5V 45 85 ns

Low-to-High Level VDD e 10V 25 45 ns

VDD e 15V 20 35 ns

tTHL Transition Time VDD e 5V 30 60 ns


VDD e 15V 15 30 ns

tTLH Transition Time VDD e 5V 60 120 ns


VDD e 15V 25 45 ns

CIN Input Capacitance Any Input 15 22.5 pF

*AC Parameters are guaranteed by DC correlated testing.

AC Electrical Characteristics* CD4050BM/CD4050BC

TA e 25§C, CL e 50 pF, RL e 200k, tr e tf e 20 ns, unless otherwise specified

Symbol Parameter Conditions Min Typ Max Units

tPHL Propagation Delay Time VDD e 5V 60 110 ns


VDD e 15V 20 30 ns

tPLH Propagation Delay Time VDD e 5V 60 120 ns


VDD e 15V 25 45 ns

tTHL Transition Time VDD e 5V 30 60 ns


VDD e 15V 15 30 ns

tTLH Transition Time VDD e 5V 60 120 ns


VDD e 15V 25 45 ns

CIN Input Capacitance Any Input 5 7.5 pF

*AC Parameters are guaranteed by DC correlated testing.

4

Schematic DiagramsCD4049UBM/CD4049UBC

1 of 6 Identical Units

TL/F/5971–3

CD4050BM/CD4050BC

1 of 6 Identical Units

TL/F/5971–4

Switching Time Waveforms

TL/F/5971–5

Typical Applications

CMOS to TTL or CMOS at a Lower VDD

TL/F/5971–6Note: VDD1 t VDD2

Note: In the case of the CD4049UBM/CD4049UBC

the output drive capability increases with increasing

input voltage. E.g., If VDD1 e 10V the CD4049UBM/

CD4049UBC could drive 4 TTL loads.

5

CD

4049U

BM

/C

D4049U

BC

Hex

Invert

ing

Buff

er

CD

4050B

M/C

D4050B

CH

ex

Non-Invert

ing

Buff

er

Physical Dimensions inches (millimeters)

Ceramic Dual-In-Line Package (J)

Order Number CD4049UBMJ, CD4049UBCJ, CD4049BMJ or CD4049BCJ

NS Package Number J16A

Molded Dual-In-Line Package (N)

Order Number CD4050BMN, CD4050BCN, CD4050BMN or CD4050BCN

NS Package Number N16E

LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL

SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or 2. A critical component is any component of a life

systems which, (a) are intended for surgical implant support device or system whose failure to perform can

into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life

failure to perform, when properly used in accordance support device or system, or to affect its safety or

with instructions for use provided in the labeling, can effectiveness.

be reasonably expected to result in a significant injury

to the user.

National Semiconductor National Semiconductor National Semiconductor National SemiconductorCorporation Europe Hong Kong Ltd. Japan Ltd.1111 West Bardin Road Fax: (a49) 0-180-530 85 86 13th Floor, Straight Block, Tel: 81-043-299-2309Arlington, TX 76017 Email: cnjwge@ tevm2.nsc.com Ocean Centre, 5 Canton Rd. Fax: 81-043-299-2408Tel: 1(800) 272-9959 Deutsch Tel: (a49) 0-180-530 85 85 Tsimshatsui, KowloonFax: 1(800) 737-7018 English Tel: (a49) 0-180-532 78 32 Hong Kong

Fran3ais Tel: (a49) 0-180-532 93 58 Tel: (852) 2737-1600Italiano Tel: (a49) 0-180-534 16 80 Fax: (852) 2736-9960


AXIAL SILASTIC GUARD JUNCTION STANDARD RECTIFIER

VOLTAGE RANGE 50 to 1000 Volts 6A05 THRU 6A10 CURRENT 6.0 Ampere

E-mail: [email protected] Web Site: www.cnmic.com

FEATURES • Low coat construction • Low forward voltage drop • Low reverse leakage • High forward surge current capability • High temperature soldering guaranteed:

260/10 secods/.375”(9.5mm)lead length at 5 lbs(2.3kg) tension MECHANICAL DATA

• Case: Transfer molded plastic • Epoxy: UL94V-O rate flame retardant • Polarity: Color band denotes cathode end • Lead: Plated axial lead, solderable per MIL-STD-202E method 208C • Mounting position: Any • Weight: 0.07 ounce, 2.0 grams MAXIMUM RATINGS AND ELECTRICAL CHARACTERISTICS

• Ratings at 25OC ambient temperature unless otherwise specified • Single Phase, half wave, 60Hz, resistive or inductive load • For capacitive load derate current by 20%

SYMBOLS 6A05 6A1 6A2 6A4 6A6 6A8 6A10 UNITS

Maximum Repetitive Peak Reverse Voltage VRRM 50 100 200 400 600 800 1000 Volts Maximum RMS Voltage VRMS 35 70 140 280 420 560 700 Volts Maximum DC Blocking Voltage VDC 50 100 200 400 600 800 1000 Volts Maximum Average Forward Rectified Current 0.375”(9.5mm) lead length at TA= 60 I(AV) 6.0 Amps Peak Forward Surge Current 8.3mS single half sine wave superimposed on rated load (JEDEC method)

IFSM 300 Amps

Maximum Instantaneous Forward Voltage @ 6.0A VF 0.95 Volts TA = 25 10 Maximum DC Reverse Current at Rated

DC Blocking Voltage per element TA = 100 IR

1.0 µAmps mAmps

Maximum Full Load Reverse Current, full cycle average 0.375”(9.5mm)lead length at TL=105 IR(AV) 1.0 mAmps

Typical Junction Capacitance (Note 1) CJ 150 pF Typical Thermal Resistance (Note 2) RθJA 10 /W Operating Junction Temperature Range TJ，TSTG -55 to +150

Notes: 1. Measured at 1.0MHz and Applied Reverse Voltage of 4.0V Volts. 2. Thermal Resistance from junction to Ambient at .375”(9.5mm)lead length, P.C.board mounted with 1.1”× 1.1”(30×

30mm)copper heatsink .

DIA.360(9.1).340(8.6)

1.0(25.4)MIN.

DIA.052(1.3).048(1.2)

.360(9.1)

.340(8.6)

1.0(25.4)MIN.

Dimensions in inches and (millimeters)

mailto:[email protected]

http://www.cnmic.com

AXIAL SILASTIC GUARD JUNCTION STANDARD RECTIFIER

VOLTAGE RANGE 50 to 1000 Volts 6A05 THRU 6A10 CURRENT 6.0 Ampere

E-mail: [email protected] Web Site: www.cnmic.com

1.0

FIG.2-MAXIMUM NON-REPETITIVE PEAK

100

T j jmax

502010

jT =100° C

CHARACTERISTICS

852

300

200

100

10

CU

RR

EN

T, (A

)

PEA

K F

OR

WA

RD

SU

RG

E

10

NUMBER OF CYCLES AT 60 Hz

8.3ms Single Half Sine-Wave(JEDEC Method) =T

FORWARD SURGE CURRENT

FIG.4-TYPICAL REVERSE

DERATING CURVEFIG.1-TYPICAL FORWARD CURRENT

150 17512575 100500

0

P.C. Board

25AV

ER

AG

E F

OR

WA

RD

CU

RR

EN

T,(A

)

10

FIG.3-TYPICAL INSTANTANEOUS FORWARD CHARACTERISTICS

AMBIENT TEMPERATURE, (° C)

jT =25° C

8040 60 100

1.0

0.1

200.01

0

(mA)

PERCENT OF RATED PEAK

REVERSE VOLTAGE,(%)

100

1.4

jT =25° C

1.21.00.80.6

1% Duty Cycle

Pulse Width=300us

1

0.1

(A)

(A)

1000

100

INSTANTANEOUS FORWARD VOLTAGE,(V)

FIG.5-TYPICAL JUNCTION CAPACITANCE

10.01.0 4.00.1

10

REVERSE VOLTAGE,(VOLTS)

TJ=25° C F=1MHz

CA

PA

CIT

AN

CE

,(pF)

INS

TAN

TAN

EO

US

FO

RW

AR

D C

UR

RE

NT,

INS

TAN

TAN

EO

US

RE

VER

SE

CU

RR

EN

T,

1.6 1.8 2.0

140120

2.0

3.0

4.0

5.0

6.0

60

Standard P.C. BoardMounting

60 Hz Resistive orInductive loadsGroup Plane

1" X 1" CopperSurface Area

Recommended P.C. BoardMounting

100

100020

RATING AND CHRACTERISTIC CURVES 6A05 Thur 6A10

mailto:[email protected]

http://www.cnmic.com

Typical Connection

Featuresn Floating channel designed for bootstrap operation

Fully operational to +500VTolerant to negative transient voltagedV/dt immune

n Gate drive supply range from 10 to 20Vn Undervoltage lockout for both channelsn Separate logic supply range from 5 to 20V

Logic and power ground ±5V offsetn CMOS Schmitt-triggered inputs with pull-downn Cycle by cycle edge-triggered shutdown logicn Matched propagation delay for both channelsn Outputs in phase with inputs

Description The IR2110 is a high voltage, high speed powerMOSFET and IGBT driver with independent high andlow side referenced output channels. ProprietaryHVIC and latch immune CMOS technologies enableruggedized monolithic construction. Logic inputs arecompatible with standard CMOS or LSTTL outputs.The output drivers feature a high pulse current bufferstage designed for minimum driver cross-conduc-tion. Propagation delays are matched to simplifyuse in high frequency applications. The floatingchannel can be used to drive an N-channel powerMOSFET or IGBT in the high side configurationwhich operates up to 500 volts.

Packages

Data Sheet No. PD-6.011E

IR2110HIGH AND LOW SIDE DRIVER

Product Summary

VOFFSET 500V max.

IO+/- 2A / 2A

VOUT 10 - 20V

ton/off (typ.) 120 & 94 ns

Delay Matching 10 ns

HIN

up to 500V

TOLOAD

VDD VB

VS

HO

LO

COM

HIN

LIN

VSS

SD

VCCLIN

VDD

SD

VSS

VCC

CONTROL INTEGRATED CIRCUIT DESIGNERS MANUAL B-25

IR2110

B-26 CONTROL INTEGRATED CIRCUIT DESIGNERS MANUAL

Parameter Value

Symbol Definition Min. Max. UnitsVB High Side Floating Supply Voltage -0.3 525

VS High Side Floating Supply Offset Voltage VB - 25 VB + 0.3

VHO High Side Floating Output Voltage VS - 0.3 VB + 0.3

VCC Low Side Fixed Supply Voltage -0.3 25

VLO Low Side Output Voltage -0.3 VCC + 0.3

VDD Logic Supply Voltage -0.3 VSS + 25

VSS Logic Supply Offset Voltage VCC - 25 VCC + 0.3

VIN Logic Input Voltage (HIN, LIN & SD) VSS - 0.3 VDD + 0.3

dVs/dt Allowable Offset Supply Voltage Transient (Figure 2) — 50 V/ns

PD Package Power Dissipation @ TA ≤ +25°C (14 Lead DIP) — 1.6

(14 Lead DIP w/o Lead 4) — 1.5

(16 Lead DIP w/o Leads 5 & 6) — 1.6

(16 Lead SOIC) — 1.25

RθJA Thermal Resistance, Junction to Ambient (14 Lead DIP) — 75

(14 Lead DIP w/o Lead 4) — 85

(16 Lead DIP w/o Leads 5 & 6) — 75

(16 Lead SOIC) — 100

TJ Junction Temperature — 150

TS Storage Temperature -55 150 °C

TL Lead Temperature (Soldering, 10 seconds) — 300

Parameter ValueSymbol Definition Min. Max. Units

VB High Side Floating Supply Absolute Voltage VS + 10 VS + 20

VS High Side Floating Supply Offset Voltage Note 1 500

VHO High Side Floating Output Voltage VS VB

VCC Low Side Fixed Supply Voltage 10 20

VLO Low Side Output Voltage 0 VCC

VDD Logic Supply Voltage VSS + 5 VSS + 20

VSS Logic Supply Offset Voltage -5 5

VIN Logic Input Voltage (HIN, LIN & SD) VSS VDD

TA Ambient Temperature -40 125 °C

Absolute Maximum RatingsAbsolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters areabsolute voltages referenced to COM. The Thermal Resistance and Power Dissipation ratings are measured under boardmounted and still air conditions. Additional information is shown in Figures 28 through 35.

Recommended Operating ConditionsThe Input/Output logic timing diagram is shown in Figure 1. For proper operation the device should be used within therecommended conditions. The VS and VSS offset ratings are tested with all supplies biased at 15V differential. Typicalratings at other bias conditions are shown in Figures 36 and 37.

Note 1: Logic operational for VS of -4 to +500V. Logic state held for VS of -4V to -VBS.

°C/W

W

V

V

IR2110


Parameter ValueSymbol Definition Figure Min. Typ. Max. Units Test Conditions

ton Turn-On Propagation Delay 7 — 120 150 VS = 0V

toff Turn-Off Propagation Delay 8 — 94 125 VS = 500V

tsd Shutdown Propagation Delay 9 — 110 140 VS = 500V

tr Turn-On Rise Time 10 — 25 35

tf Turn-Off Fall Time 11 — 17 25

MT Delay Matching, HS & LS Turn-On/Off — — — 10 Figure 5

Parameter ValueSymbol Definition Figure Min. Typ. Max. Units Test Conditions

VIH Logic “1” Input Voltage 12 9.5 — —

VIL Logic “0” Input Voltage 13 — — 6.0

VOH High Level Output Voltage, VBIAS - VO 14 — — 1.2 IO = 0A

VOL Low Level Output Voltage, VO 15 — — 0.1 IO = 0A

ILK Offset Supply Leakage Current 16 — — 50 VB = VS = 500V

IQBS Quiescent VBS Supply Current 17 — 125 230 VIN = 0V or VDD

IQCC Quiescent VCC Supply Current 18 — 180 340 VIN = 0V or VDD

IQDD Quiescent VDD Supply Current 19 — 15 30 VIN = 0V or VDD

IIN+ Logic “1” Input Bias Current 20 — 20 40 VIN = VDD

IIN- Logic “0” Input Bias Current 21 — — 1.0 VIN = 0V

VBSUV+ VBS Supply Undervoltage Positive Going 22 7.5 8.6 9.7Threshold

VBSUV- VBS Supply Undervoltage Negative Going 23 7.0 8.2 9.4Threshold

VCCUV+ VCC Supply Undervoltage Positive Going 24 7.4 8.5 9.6Threshold

VCCUV- VCC Supply Undervoltage Negative Going 25 7.0 8.2 9.4Threshold

IO+ Output High Short Circuit Pulsed Current 26 2.0 2.5 — VO = 0V, VIN = VDDPW ≤ 10 µs

IO- Output Low Short Circuit Pulsed Current 27 2.0 2.5 — VO = 15V, VIN = 0VPW ≤ 10 µs

ns

Dynamic Electrical CharacteristicsVBIAS (VCC, VBS, VDD) = 15V, CL = 1000 pF, TA = 25°C and VSS = COM unless otherwise specified. The dynamicelectrical characteristics are measured using the test circuit shown in Figure 3.

Static Electrical CharacteristicsVBIAS (VCC, VBS, VDD) = 15V, TA = 25°C and VSS = COM unless otherwise specified. The VIN, VTH and IIN parametersare referenced to VSS and are applicable to all three logic input leads: HIN, LIN and SD. The VO and IO parameters arereferenced to COM and are applicable to the respective output leads: HO or LO.

V

µA

V

A

IR2110


LeadSymbol DescriptionVDD Logic supply

HIN Logic input for high side gate driver output (HO), in phase

SD Logic input for shutdown

LIN Logic input for low side gate driver output (LO), in phase

VSS Logic ground

VB High side floating supply

HO High side gate drive output

VS High side floating supply return

VCC Low side supply

LO Low side gate drive output

COM Low side return

VB

SD

LIN

VDD

PULSEGEN

RS

Q

VSS

UVDETECT

DELAY

HVLEVELSHIFT

VCC

PULSEFILTER

UVDETECT

VDD/VCCLEVELSHIFT

VDD

/VCC

LEVELSHIFT

LO

VS

COM

RS

Q R

S

R Q

HIN

HO

Functional Block Diagram

Lead Definitions

Lead Assignments

14 Lead DIP 14 Lead DIP w/o Lead 4 16 Lead DIP w/o Leads 4 & 5 16 Lead SOIC (Wide Body)

IR2110 IR2110-1 IR2110-2 IR2110SPart Number

IR2110


Thickness of Gate Oxide 800ÅConnections Material Poly Silicon

First Width 4 µmLayer Spacing 6 µm

Thickness 5000ÅMaterial Al - Si (Si: 1.0% ±0.1%)

Second Width 6 µmLayer Spacing 9 µm

Thickness 20,000ÅContact Hole Dimension 8 µm X 8 µmInsulation Layer Material PSG (SiO2)

Thickness 1.5 µmPassivation Material PSG (SiO2)(1) Thickness 1.5 µmPassivation Material Proprietary*(2) Thickness Proprietary*Method of Saw Full CutMethod of Die Bond Ablebond 84 - 1Wire Bond Method Thermo Sonic

Material Au (1.0 mil / 1.3 mil)Leadframe Material Cu

Die Area AgLead Plating Pb : Sn (37 : 63)

Package Types 14 & 16 Lead PDIP / 16 Lead SOICMaterials EME6300 / MP150 / MP190

Remarks: * Patent Pending

Device Information

Process & Design Rule HVDCMOS 4.0 µmTransistor Count 220Die Size 100 X 117 X 26 (mil)Die Outline

IR2110


Figure 1. Input/Output Timing Diagram Figure 2. Floating Supply V oltage Transient Test Circuit

Figure 3. Switc hing Time Test Circuit Figure 4. Switc hing Time Wavef orm Definition

Figure 6. Delay Matc hing Wave form DefinitionsFigure 3. Shutdown Waveform Definitions

SD

tsd

HOLO

50%

90%

HINLIN

trton tftoff

HOLO

50% 50%

90% 90%

10% 10%

HINLIN

HO

50% 50%

10%

LO

90%

MT

HOLO

MT

IR2110


Figure 9B. Shutdown Time vs. Voltage

Figure 8A. Turn-Off Time vs. Temperature Figure 8B. Turn-Off Time vs. V oltage

Figure 7A. Turn-On Time vs. Temperature Figure 7B. Turn-On Time vs. V oltage

Figure 9A. Shutdown Time vs. Temperature

0

50

100

150

200

250

10 12 14 16 18 20

VBIAS Supply Voltage (V)

Turn

-On

Del

ay T

ime

(ns)

Max.

Typ.

0

50

100

150

200

250

-50 -25 0 25 50 75 100 125

Temperature (°C)

Turn

-On

Del

ay T

ime

(ns)

Max.

Typ.

0

50

100

150

200

250

-50 -25 0 25 50 75 100 125

Temperature (°C)

Turn

-Off

Del

ay T

ime

(ns)

Max.

Typ.

0

50

100

150

200

250

10 12 14 16 18 20


Turn

-Off

Del

ay T

ime

(ns)

Max.

Typ.

0

50

100

150

200

250

10 12 14 16 18 20


Shut

dow

n D

elay

tim

e (n

s)

Max.

Typ.

0

50

100

150

200

250

-50 -25 0 25 50 75 100 125

Temperature (°C)

Shut

dow

n D

elay

Tim

e (n

s)

Max.

Typ.

IR2110


Figure 12A. Logic “1” Input Threshold vs. Temperature Figure 12B. Logic “1” Input Threshold vs. Voltage

Figure 10A. Turn-On Rise Time vs. Temperature

Figure 11A. Turn-Off F all Time vs. Temperature Figure 11B. Turn-Off F all Time vs. Voltage

Figure 10B. Turn-On Rise Time vs. V oltage

0

20

40

60

80

100

-50 -25 0 25 50 75 100 125

Temperature (°C)

Turn

-On

Ris

e Ti

me

(ns)

Max.

Typ.

0

20

40

60

80

100

10 12 14 16 18 20


Turn

-On

Ris

e Ti

me

(ns)

Max.

Typ.

0

10

20

30

40

50

-50 -25 0 25 50 75 100 125

Temperature (°C)

Turn

-Off

Fall

Tim

e (n

s)

Max.

Typ.

0

10

20

30

40

50

10 12 14 16 18 20


Turn

-Off

Fall

Tim

e (n

s)

Max.

Typ.

0.0

3.0

6.0

9.0

12.0

15.0

-50 -25 0 25 50 75 100 125

Temperature (°C)

Logi

c "1

" Inp

ut T

hres

hold

(V)

Min.

0.0

3.0

6.0

9.0

12.0

15.0

5 7.5 10 12.5 15 17.5 20

VDD Logic Supply Voltage (V)

Logi

c "1

" Inp

ut T

hres

hold

(V)

Min.

IR2110


Figure 13A. Logic “0” Input Threshold vs. Temperature Figure 13B. Logic “0” Input Threshold vs. Voltage

Figure 14A. High Level Output vs. Temperature Figure 14B. High Level Output vs. Voltage

Figure 15B. Low Level Output vs. VoltageFigure 15A. Low Level Output vs. Temperature

0.0

3.0

6.0

9.0

12.0

15.0

-50 -25 0 25 50 75 100 125

Temperature (°C)

Logi

c "0

" Inp

ut T

hres

hold

(V)

Max.

0.0

3.0

6.0

9.0

12.0

15.0

5 7.5 10 12.5 15 17.5 20


Logi

c "0

" Inp

ut T

hres

hold

(V)

Max.

0.00

1.00

2.00

3.00

4.00

5.00

-50 -25 0 25 50 75 100 125

Temperature (°C)

Hig

h Le

vel O

utpu

t Vol

tage

(V)

Max.

0.00

0.20

0.40

0.60

0.80

1.00

-50 -25 0 25 50 75 100 125

Temperature (°C)

Low

Lev

el O

utpu

t Vol

tage

(V)

Max.

0.00

1.00

2.00

3.00

4.00

5.00

10 12 14 16 18 20


Hig

h Le

vel O

utpu

t Vol

tage

(V)

Max.

0.0

3.0

6.0

9.0

12.0

15.0

5 7.5 10 12.5 15 17.5 20


Logi

c "1

" Inp

ut T

hres

hold

(V)

Min.

IR2110


Figure 16B. Offset Supply Current vs. VoltageFigure 16A. Offset Supply Current vs. Temperature

Figure 18A. V CC Supply Current vs. Temperature Figure 18B. V CC Supply Current vs. V oltage

Figure 17A. V BS Supply Current vs. Temperature Figure 17B. V BS Supply Current vs. V oltage

0

125

250

375

500

625

10 12 14 16 18 20

VCC Fixed Supply Voltage (V)

V CC S

uppl

y C

urre

nt (µ

A)

Max.

Typ.

0

125

250

375

500

625

-50 -25 0 25 50 75 100 125

Temperature (°C)

V CC S

uppl

y C

urre

nt (µ

A)

Max.

Typ.

0

100

200

300

400

500

-50 -25 0 25 50 75 100 125

Temperature (°C)

VBS

Sup

ply

Cur

rent

(µA)

Max.

Typ.

0

100

200

300

400

500

10 12 14 16 18 20

VBS Floating Supply Voltage (V)

VBS

Sup

ply

Cur

rent

(µA)

Max.

Typ.

0

100

200

300

400

500

0 100 200 300 400 500

VB Boost Voltage (V)

Offs

et S

uppl

y Le

akag

e C

urre

nt (µ

A)

Max.

0

100

200

300

400

500

-50 -25 0 25 50 75 100 125

Temperature (°C)

Offs

et S

uppl

y Le

akag

e C

urre

nt (µ

A)

Max.

IR2110


Figure 21A. Logic “0” Input Current vs. Temperature Figure 21B. Logic “0” Input Current vs. Voltage

Figure 19A. V DD Supply Current vs. Temperature Figure 19B. V DD Supply Current vs. V oltage

Figure 20A. Logic “1” Input Current vs. Temperature Figure 20B. Logic “1” Input Current vs. Voltage

0

20

40

60

80

100

-50 -25 0 25 50 75 100 125

Temperature (°C)

V DD S

uppl

y C

urre

nt (µ

A)

Max.

Typ.

0

20

40

60

80

100

5 7.5 10 12.5 15 17.5 20


V DD S

uppl

y C

urre

nt (µ

A)

Max.

Typ.

0

20

40

60

80

100

-50 -25 0 25 50 75 100 125

Temperature (°C)

Logi

c "1

" Inp

ut B

ias

Cur

rent

(µA)

Max.

Typ.

0

20

40

60

80

100

5 7.5 10 12.5 15 17.5 20


Logi

c "1

" Inp

ut B

ias

Cur

rent

(µA)

Max.

T yp.

0.00

1.00

2.00

3.00

4.00

5.00

-50 -25 0 25 50 75 100 125

Temperature (°C)

Logi

c "0

" Inp

ut B

ias

Cur

rent

(µA)

Max.

0.00

1.00

2.00

3.00

4.00

5.00

5 7.5 10 12.5 15 17.5 20


Logi

c "0

" Inp

ut B

ias

Cur

rent

(µA)

Max.

IR2110


6.0

7.0

8.0

9.0

10.0

11.0

-50 -25 0 25 50 75 100 125

Temperature (°C)

V CC U

nder

volta

ge L

ocko

ut +

(V)

Max.

Typ.

Min.

6.0

7.0

8.0

9.0

10.0

11.0

-50 -25 0 25 50 75 100 125

Temperature (°C)

V BS

Und

ervo

ltage

Loc

kout

+ (V

)

Max.

Typ.

Min.

Figure 22. V BS Undervoltage (+) vs. Temperature Figure 23. V BS Undervoltage (-) vs. Temperature

Figure 24. V CC Undervoltage (+) vs. Temperature Figure 25. V CC Undervoltage (-) vs. Temperature

Figure 26A. Output Source Current vs. Temperature Figure 26B. Output Source Current vs. V oltage

6.0

7.0

8.0

9.0

10.0

11.0

-50 -25 0 25 50 75 100 125

Temperature (°C)

V BS

Und

ervo

ltage

Loc

kout

- (V

)

Max.

Typ.

Min.

6.0

7.0

8.0

9.0

10.0

11.0

-50 -25 0 25 50 75 100 125

Temperature (°C)

VCC

Und

ervo

ltage

Loc

kout

- (V

)

Max.

Typ.

Min.

0.00

1.00

2.00

3.00

4.00

5.00

10 12 14 16 18 20


Out

put S

ourc

e C

urre

nt (A

)

Min.

Typ.

0.00

1.00

2.00

3.00

4.00

5.00

-50 -25 0 25 50 75 100 125

Temperature (°C)

Out

put S

ourc

e C

urre

nt (A

)

Min.

Typ.

IR2110


Figure 28. IR2110 T J vs. Frequency (IRFBC20)RGATE = 33ΩΩΩΩΩ, VCC = 15V


Figure 27B. Output Sink Current vs. VoltageFigure 27A. Output Sink Current vs. Temperature

Figure 31. IR2110 T J vs. Frequency (IRFPE50)RGATE = 10ΩΩΩΩΩ, VCC = 15V


0.00

1.00

2.00

3.00

4.00

5.00

10 12 14 16 18 20


Out

put S

ink

Cur

rent

(A)

Min.

Typ.

0

25

50

75

100

125

150

1E+2 1E+3 1E+4 1E+5 1E+6

Frequency (Hz)

Junc

tion

Tem

pera

ture

(°C

)

320V

140V

10V

0

25

50

75

100

125

150

1E+2 1E+3 1E+4 1E+5 1E+6

Frequency (Hz)

Junc

tion

Tem

pera

ture

(°C

)

320V

140V

10V

0

25

50

75

100

125

150

1E+2 1E+3 1E+4 1E+5 1E+6

Frequency (Hz)

Junc

tion

Tem

pera

ture

(°C

)

320V 140V

10V

0

25

50

75

100

125

150

1E+2 1E+3 1E+4 1E+5 1E+6

Frequency (Hz)

Junc

tion

Tem

pera

ture

(°C

)

320V 140V

10V

0.00

1.00

2.00

3.00

4.00

5.00

-50 -25 0 25 50 75 100 125

Temperature (°C)

Out

put S

ink

Cur

rent

(A)

Min.

Typ.

IR2110


Figure 32. IR2110S T J vs. Frequency (IRFBC20)RGATE = 33ΩΩΩΩΩ, VCC = 15V


Figure 36. Maximum V S Negative Offset vs.VBS Supply Voltage

Figure 37. Maximum V SS Positive Offset vs.VCC Supply Voltage


Figure 35. IR2110S T J vs. Frequency (IRFPE50)RGATE = 10ΩΩΩΩΩ, VCC = 15V

0

25

50

75

100

125

150

1E+2 1E+3 1E+4 1E+5 1E+6

Frequency (Hz)

Junc

tion

Tem

pera

ture

(°C

)

320V 140V

10V

0

25

50

75

100

125

150

1E+2 1E+3 1E+4 1E+5 1E+6

Frequency (Hz)

Junc

tion

Tem

pera

ture

(°C

)

320V 140V

10V

0

25

50

75

100

125

150

1E+2 1E+3 1E+4 1E+5 1E+6

Frequency (Hz)

Junc

tion

Tem

pera

ture

(°C

)

320V 140V

10V

0

25

50

75

100

125

150

1E+2 1E+3 1E+4 1E+5 1E+6

Frequency (Hz)

Junc

tion

Tem

pera

ture

(°C

)

320V 140V 10V

-10.0

-8.0

-6.0

-4.0

-2.0

0.0

10 12 14 16 18 20

VBS Floating Supply Voltage (V)

V S O

ffset

Sup

ply

Volta

ge (V

) Typ.

0.0

4.0

8.0

12.0

16.0

20.0

10 12 14 16 18 20

VCC Fixed Supply Voltage (V)

V SS

Logi

c Su

pply

Offs

et V

olta

ge (V

)

Typ.

Page 93

10. REFERENCES

Page 94

[ 1 ] C.-L. Shen and Y.-E. Wu and M.-H. Chen, “A Modified Sepic Converter with Soft

Switching Technology”, IEEE/978-1-4244-1706-3/08.

[ 2 ] J.-M. Kwon, W.-Y. Choi, J.-J. Lee, E.-H. Kim and B.-H. Kwon, “Continuous-

conduction-mode SEPIC converter with low reverse-recovery loss for power factor

correction”, IEE Proc.-Electr. Power Appl., Vol. 153, No. 5, September 2006

[ 3 ] Ovidiu Pop, Gabriel Chindris, Alin Grama, Florin Hurgoi, “Power Factor Correction

Circuit with a New Modified SEPIC Converter”, 24th International Spring Seminar

on Electronics Technology, May 5-9,2001, Calimanesti-Caciulata, Romania.

[ 4 ] Oscar García, Member, IEEE, José A. Cobos, Member, IEEE, Roberto Prieto,

Member, IEEE, Pedro Alou, and Javier Uceda, Senior Member, IEEE, “Single Phase

Power Factor Correction: A Survey”, IEEE TRANSACTIONS ON POWER

ELECTRONICS, VOL. 18, NO. 3, MAY 2003

[ 5 ] Alenka Hren, Primoz Slibar, “Full order Dynamic Model of SEPIC Converter”,

IEEE ISIE 2005, June 20-23, 2005, Dubrovnik, Croatia

[ 6 ] Wei Gu, Dongbing Zhang, “Designing A SEPIC Converter”, National

Semiconductor Application Note 1484, April 30, 2008

SEPIC Project Report

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