Séminaire CNES : CI Logiques & Interfaces THALES RESEARCH & TECHNOLOGY FRANCE Information included in this document is the property of THALES. It must.

Séminaire CNES : CI Logiques & Interfaces

THALES RESEARCH & TECHNOLOGY FRANCE

09/10/01 1

Info

rmat

ion

incl

uded

in

th

is

docu

men

t is

th

e p

rope

rty

of

TH

ALE

S.

It m

ust

not

be d

iscl

osed

with

out

the

prio

r w

ritte

n co

nsen

t of

TH

ALE

S R

ES

EA

RC

H &

TE

CH

NO

LOG

Y.

Mod

èle

trtc

o V

5.0.

0 THE WORLD OF LOGIC FAMILIES

Source: TI

LVX

VCX

LCX

TinyLogic

VCXLCX

VCX

LCX

VHC/VHCT

FST



09/10/01 2

Info

rmat

ion

incl

uded

in

th

is

docu

men

t is

th

e p

rope

rty

of

TH

ALE

S.

It m

ust

not

be d

iscl

osed

with

out

the

prio

r w

ritte

n co

nsen

t of

TH

ALE

S R

ES

EA

RC

H &

TE

CH

NO

LOG

Y.

Mod

èle

trtc

o V

5.0.

0

Source: Insight Onsite

WORLDWIDE LOGIC TAM & MARKET SHARE

1998 1999

Fairchild16%

TI32%

ON12%

Philips13%

Toshiba11%

Others16%

Fairchild20%

TI29%

ON11%

Philips14%

Toshiba13%

Others13%



09/10/01 3

Info

rmat

ion

incl

uded

in

th

is

docu

men

t is

th

e p

rope

rty

of

TH

ALE

S.

It m

ust

not

be d

iscl

osed

with

out

the

prio

r w

ritte

n co

nsen

t of

TH

ALE

S R

ES

EA

RC

H &

TE

CH

NO

LOG

Y.

Mod

èle

trtc

o V

5.0.

0 PRODUCT LIFE CYCLE

Source: TI

LS/S

SCAN

TTL

ABT

VCX

VHC/VHCTFACTFAST/FASTr/ALS

HC/HCT

ECL

Introduction Growth Maturity Saturation Declining

CD4000/74C

AS

TinyLogic

LVX/LCX/LVT

ALVT

FST

Source: Fairchild



09/10/01 4

Info

rmat

ion

incl

uded

in

th

is

docu

men

t is

th

e p

rope

rty

of

TH

ALE

S.

It m

ust

not

be d

iscl

osed

with

out

the

prio

r w

ritte

n co

nsen

t of

TH

ALE

S R

ES

EA

RC

H &

TE

CH

NO

LOG

Y.

Mod

èle

trtc

o V

5.0.

0

T.I. Philips Hitachi ON Semi, Fairchild Toshiba I.D.T. Pericom STmBipolaire 5V

TTL Std X XS / LS X X (LS) X (LS) XFast X X X

AS/ALS X X (ALS) X

• Bipolar families : Saturation or decline phase

T.I. Philips Hitachi ON Semi, Fairchild Toshiba I.D.T. Pericom STmCMOS 5V

4000B (5V/12V) X X X X X XHC(T) X X X X X X XAC(T) X X X X X XFCT-T X X X

AHC(T) (5V/3,3V) X XVHC(T) (5V/3,3V) X X X X

• 5V CMOS families : maturity or saturation phase except for AHC/AHCT and VHC/VHCT

FAMILY RECOMMANDATION

Recently discontinued Recently discontinued (LTB = 30/04/01)(LTB = 30/04/01)

Not recommended for new designs

Not recommended for new designs

new designs



09/10/01 5

Info

rmat

ion

incl

uded

in

th

is

docu

men

t is

th

e p

rope

rty

of

TH

ALE

S.

It m

ust

not

be d

iscl

osed

with

out

the

prio

r w

ritte

n co

nsen

t of

TH

ALE

S R

ES

EA

RC

H &

TE

CH

NO

LOG

Y.

Mod

èle

trtc

o V

5.0.

0

•BiCMOS families : maturity phase for ABT growth phase for LVT (3.3V) and ALVT (2.5V).

T.I. Philips Hitachi ON Semi, Fairchild Toshiba I.D.T. Pericom STmBiCMOS

ABT (5V) X X X X XLVT (3,3V) X X X XALVT (2,5V) X X

T.I. Philips Hitachi ON Semi, Fairchild Toshiba I.D.T. Pericom STmCMOS 3,3V

LV X X XLVC X X X X

ALVC X X X X XFCT3 X X XLCX X X X X XLVQ X XLVX X X X X

FAMILY USED RECOMMANDATION

new designs

•3.3V CMOS families : growth phase. Pay attention with FCT3

New designs



09/10/01 6

Info

rmat

ion

incl

uded

in

th

is

docu

men

t is

th

e p

rope

rty

of

TH

ALE

S.

It m

ust

not

be d

iscl

osed

with

out

the

prio

r w

ritte

n co

nsen

t of

TH

ALE

S R

ES

EA

RC

H &

TE

CH

NO

LOG

Y.

Mod

èle

trtc

o V

5.0.

0 WHO MAKES WHAT ?

T.I. Philips Hitachi ON Semi, Fairchild Toshiba I.D.T. Pericom STmBipolaire 5V

TTL Std X XS / LS X X (LS) X (LS) XFast X X X

AS/ALS X X (ALS) XCMOS 5V

4000B (5V/12V) X X X X X XHC(T) X X X X X X XAC(T) X X X X X XFCT-T X X X

AHC(T) (5V/3,3V) X XVHC(T) (5V/3,3V) X X X X

BiCMOS

ABT (5V) X X X X XLVT (3,3V) X X X X

ALVT (2,5V) X XCMOS 3,3V

LV X X XLVC X X X X

ALVC X X X X XFCT3 X X XLCX X X X X XLVQ X XLVX X X X X

CMOS 2,5V

VCX

AVC X X X Xx x



09/10/01 7

Info

rmat

ion

incl

uded

in

th

is

docu

men

t is

th

e p

rope

rty

of

TH

ALE

S.

It m

ust

not

be d

iscl

osed

with

out

the

prio

r w

ritte

n co

nsen

t of

TH

ALE

S R

ES

EA

RC

H &

TE

CH

NO

LOG

Y.

Mod

èle

trtc

o V

5.0.

0 LOGIC VENDOR PARTNERSHIPS

Source: TI



09/10/01 8

Info

rmat

ion

incl

uded

in

th

is

docu

men

t is

th

e p

rope

rty

of

TH

ALE

S.

It m

ust

not

be d

iscl

osed

with

out

the

prio

r w

ritte

n co

nsen

t of

TH

ALE

S R

ES

EA

RC

H &

TE

CH

NO

LOG

Y.

Mod

èle

trtc

o V

5.0.

0 FAMILY PERFORMANCE POSITIONING

Source: Texas.Instr.



09/10/01 9

Info

rmat

ion

incl

uded

in

th

is

docu

men

t is

th

e p

rope

rty

of

TH

ALE

S.

It m

ust

not

be d

iscl

osed

with

out

the

prio

r w

ritte

n co

nsen

t of

TH

ALE

S R

ES

EA

RC

H &

TE

CH

NO

LOG

Y.

Mod

èle

trtc

o V

5.0.

0

Source: Fairchild.

FAMILY PERFORMANCE POSITIONING



09/10/01 10

Info

rmat

ion

incl

uded

in

th

is

docu

men

t is

th

e p

rope

rty

of

TH

ALE

S.

It m

ust

not

be d

iscl

osed

with

out

the

prio

r w

ritte

n co

nsen

t of

TH

ALE

S R

ES

EA

RC

H &

TE

CH

NO

LOG

Y.

Mod

èle

trtc

o V

5.0.

0 LOW-VOLTAGE LOGIC COMPARISON

Source: Fairchild

IDTHitachi, IDT TI

FSC, TOSHON, STm,Pericom

FSC, TOSHON, STm,Pericom

ON



09/10/01 11

Info

rmat

ion

incl

uded

in

th

is

docu

men

t is

th

e p

rope

rty

of

TH

ALE

S.

It m

ust

not

be d

iscl

osed

with

out

the

prio

r w

ritte

n co

nsen

t of

TH

ALE

S R

ES

EA

RC

H &

TE

CH

NO

LOG

Y.

Mod

èle

trtc

o V

5.0.

0 LOW-VOLTAGE MARKET COVERAGE

Source: TI



09/10/01 12

Info

rmat

ion

incl

uded

in

th

is

docu

men

t is

th

e p

rope

rty

of

TH

ALE

S.

It m

ust

not

be d

iscl

osed

with

out

the

prio

r w

ritte

n co

nsen

t of

TH

ALE

S R

ES

EA

RC

H &

TE

CH

NO

LOG

Y.

Mod

èle

trtc

o V

5.0.

0 LOGIC MIGRATION

Source: FairchildSource: Philips



09/10/01 13

Info

rmat

ion

incl

uded

in

th

is

docu

men

t is

th

e p

rope

rty

of

TH

ALE

S.

It m

ust

not

be d

iscl

osed

with

out

the

prio

r w

ritte

n co

nsen

t of

TH

ALE

S R

ES

EA

RC

H &

TE

CH

NO

LOG

Y.

Mod

èle

trtc

o V

5.0.

0 LOGIC MIGRATION

Source: Fairchild



09/10/01 14

Info

rmat

ion

incl

uded

in

th

is

docu

men

t is

th

e p

rope

rty

of

TH

ALE

S.

It m

ust

not

be d

iscl

osed

with

out

the

prio

r w

ritte

n co

nsen

t of

TH

ALE

S R

ES

EA

RC

H &

TE

CH

NO

LOG

Y.

Mod

èle

trtc

o V

5.0.

0

5-Volt Tolerant I/Os

ADVANCED-LOGIC FEATURE LIST

Output Series Termination Resistors(damping resistor)

Live Insertion (Power-up/Power-down 3-State, I OFF)

Bus Hold

LVC, LVT, ALVT, LCX

5 V

TT

L b

us

5 V

bu

s

ABT, ALVT, LVC, LVT

ABT, ALVC, ALVT, LVC, LVT, LCX

ABT, ALVC, ALVT, LVC, LVT, LCX, VCX



09/10/01 15

Info

rmat

ion

incl

uded

in

th

is

docu

men

t is

th

e p

rope

rty

of

TH

ALE

S.

It m

ust

not

be d

iscl

osed

with

out

the

prio

r w

ritte

n co

nsen

t of

TH

ALE

S R

ES

EA

RC

H &

TE

CH

NO

LOG

Y.

Mod

èle

trtc

o V

5.0.

0

• Small package options: Less board space needed

• Optimized PCB layout: Simplified routing

• Reduced EMI noise: Better routing possibilities

• Enhancing ASIC functionality: Quick fixes

• WCSP - smaller package: Enhanced thermal and electrical performance

Benefits

LITTLE LOGIC (SINGLE & DUAL GATE)

Source: TI



09/10/01 16

Info

rmat

ion

incl

uded

in

th

is

docu

men

t is

th

e p

rope

rty

of

TH

ALE

S.

It m

ust

not

be d

iscl

osed

with

out

the

prio

r w

ritte

n co

nsen

t of

TH

ALE

S R

ES

EA

RC

H &

TE

CH

NO

LOG

Y.

Mod

èle

trtc

o V

5.0.

0 TinyLogicTM

HS and HST families drop-in replacements for High-Speed (TC7Sxx)UHS is the fastest available single gate logic All 5-lead functions available in either SOT-23 or SC70 packagingSix lead latches, flip/flops and dual buffers in unique six lead SC70 pkg.

Tiny ’00

Quad-gate ’00

HS

VHC-like

CMOS inputs

5V designs

2mA Drive

<25ns max at 5v

HST

VHCT-like

TTL inputs

5V designs

2mA Drive

<30ns max at 5v

UHS

LCX-like

CMOS inputs

3V designs (1.65 - 5.5V Vcc)

24mA Drive

<5.2ns max at 5v

5v over-voltage tolerant I/O

FS

FST-like

3V designs (1.65 - 5.5V Vcc)

<6 ns enable and disable

Low Ron < 7 Ohms

High Bandwidth >250 MHz

Source: Fairchild



09/10/01 17

Info

rmat

ion

incl

uded

in

th

is

docu

men

t is

th

e p

rope

rty

of

TH

ALE

S.

It m

ust

not

be d

iscl

osed

with

out

the

prio

r w

ritte

n co

nsen

t of

TH

ALE

S R

ES

EA

RC

H &

TE

CH

NO

LOG

Y.

Mod

èle

trtc

o V

5.0.

0

† Symbol or red indicates C i = 30 pF

LITTLE LOGIC FEATURES

Source: TI



09/10/01 18

Info

rmat

ion

incl

uded

in

th

is

docu

men

t is

th

e p

rope

rty

of

TH

ALE

S.

It m

ust

not

be d

iscl

osed

with

out

the

prio

r w

ritte

n co

nsen

t of

TH

ALE

S R

ES

EA

RC

H &

TE

CH

NO

LOG

Y.

Mod

èle

trtc

o V

5.0.

0 FAIRCHILD’S LOW VOLTAGE LOGIC ROADMAP

74LVXxxx

74LCXxxx 74VCXxxx

Next Gen

74LVTxxx 74ALVTxxx

74HCxxx

Vcc : 2-6.0VTpd : 23nSIoh/Iol : 6mA

Vcc : 2-3.6VTpd : 7.0nSIoh/Iol : 4mA

Vcc : 2-3.6VTpd : 4.5nSIoh/Iol : 24mA

Vcc : 0.8-1.5VTpd : 4nSIoh/Iol : 2-4mA

Vcc : 1.8-3.6VTpd : 2.5nSIoh/Iol : 24mA

Vcc : 2.7-3.6VTpd : 3.5nSIoh/Iol : -32/64mA

Vcc : 1.8-3.6VTpd : 2.5nSIoh/Iol : -32/64mA

Cu

rren

t D

rive

(Io

h/I

ol)

0 m

A64

mA

Supply Voltage (Vcc)7.0 V 1.0 V

Source: Fairchild



09/10/01 19

Info

rmat

ion

incl

uded

in

th

is

docu

men

t is

th

e p

rope

rty

of

TH

ALE

S.

It m

ust

not

be d

iscl

osed

with

out

the

prio

r w

ritte

n co

nsen

t of

TH

ALE

S R

ES

EA

RC

H &

TE

CH

NO

LOG

Y.

Mod

èle

trtc

o V

5.0.

0

SOT23-5package outline

2.9 mm

2.84 mm

SC70pkg outline

2.0 mm

2.1 mm

Pitch Length Width Area Height SOT23-5 (M5) .95 2.9 2.8 8.1 1.1

SC70-5 (P5) .65 2.0 2.1 4.2 1.0

LITTLE LOGIC PACKAGES



09/10/01 20

Info

rmat

ion

incl

uded

in

th

is

docu

men

t is

th

e p

rope

rty

of

TH

ALE

S.

It m

ust

not

be d

iscl

osed

with

out

the

prio

r w

ritte

n co

nsen

t of

TH

ALE

S R

ES

EA

RC

H &

TE

CH

NO

LOG

Y.

Mod

èle

trtc

o V

5.0.

0 LOGIC PACKAGING LIFE CYCLE

Source: Fairchild



09/10/01 21

Info

rmat

ion

incl

uded

in

th

is

docu

men

t is

th

e p

rope

rty

of

TH

ALE

S.

It m

ust

not

be d

iscl

osed

with

out

the

prio

r w

ritte

n co

nsen

t of

TH

ALE

S R

ES

EA

RC

H &

TE

CH

NO

LOG

Y.

Mod

èle

trtc

o V

5.0.

0 PACKAGING OPTIONS

Source: TI



09/10/01 22

Info

rmat

ion

incl

uded

in

th

is

docu

men

t is

th

e p

rope

rty

of

TH

ALE

S.

It m

ust

not

be d

iscl

osed

with

out

the

prio

r w

ritte

n co

nsen

t of

TH

ALE

S R

ES

EA

RC

H &

TE

CH

NO

LOG

Y.

Mod

èle

trtc

o V

5.0.

0 SELECTING A LOGIC FAMILY

Source: TI



09/10/01 23

Info

rmat

ion

incl

uded

in

th

is

docu

men

t is

th

e p

rope

rty

of

TH

ALE

S.

It m

ust

not

be d

iscl

osed

with

out

the

prio

r w

ritte

n co

nsen

t of

TH

ALE

S R

ES

EA

RC

H &

TE

CH

NO

LOG

Y.

Mod

èle

trtc

o V

5.0.

0 LOW VOLTAGE DECISION TREE

Séminaire CNES : CI Logiques & Interfaces THALES RESEARCH & TECHNOLOGY FRANCE Information included in this document is the property of THALES. It must.

Documents

property of thales

sminaire cnes

modle trtco v5

ti slide

new designs new designs

fairchild slide

fct3 new designs slide

x x slide