Semiconductor to metallic transition in bulk accumulated amorphous indiumgallium-

Semiconductor to metallic transition in bulk accumulated amorphous indium-gallium-zinc-oxide dual gate thin-film transistorMinkyu Chun, Md Delwar Hossain Chowdhury, and Jin Jang Citation: AIP Advances 5, 057165 (2015); doi: 10.1063/1.4922005 View online: http://dx.doi.org/10.1063/1.4922005 View Table of Contents: http://scitation.aip.org/content/aip/journal/adva/5/5?ver=pdfcov Published by the AIP Publishing Articles you may be interested in A thermalization energy analysis of the threshold voltage shift in amorphous indium gallium zinc oxide thinfilm transistors under simultaneous negative gate bias and illumination J. Appl. Phys. 115, 134501 (2014); 10.1063/1.4870457 Threshold voltage dependence on channel length in amorphous-indium-gallium-zinc-oxide thin-film transistors Appl. Phys. Lett. 102, 083508 (2013); 10.1063/1.4793996 Light induced instabilities in amorphous indium–gallium–zinc–oxide thin-film transistors Appl. Phys. Lett. 97, 173506 (2010); 10.1063/1.3503971 Low-frequency noise in amorphous indium-gallium-zinc oxide thin-film transistors from subthreshold tosaturation Appl. Phys. Lett. 97, 122104 (2010); 10.1063/1.3491553 Role of order and disorder on the electronic performances of oxide semiconductor thin film transistors J. Appl. Phys. 101, 044505 (2007); 10.1063/1.2495754

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AIP ADVANCES 5, 057165 (2015)

Semiconductor to metallic transition in bulk accumulatedamorphous indium-gallium-zinc-oxide dual gatethin-film transistor

Minkyu Chun, Md Delwar Hossain Chowdhury, and Jin Janga

Advanced Display Research Center and Department of Information Display,Kyung Hee University, Seoul 130-701, Korea

(Received 27 March 2015; accepted 19 May 2015; published online 29 May 2015)

We investigated the effects of top gate voltage (VTG) and temperature (in the rangeof 25 to 70 oC) on dual-gate (DG) back-channel-etched (BCE) amorphous-indium-gallium-zinc-oxide (a-IGZO) thin film transistors (TFTs) characteristics. The incre-ment of VTG from -20V to +20V, decreases the threshold voltage (VTH) from 19.6Vto 3.8V and increases the electron density to 8.8 x 1018cm−3. Temperature dependentfield-effect mobility in saturation regime, extracted from bottom gate sweep, showa critical dependency on VTG. At VTG of 20V, the mobility decreases from 19.1to 15.4 cm2/V·s with increasing temperature, showing a metallic conduction. Onthe other hand, at VTG of - 20V, the mobility increases from 6.4 to 7.5cm2/V·swith increasing temperature. Since the top gate bias controls the position of Fermilevel, the temperature dependent mobility shows metallic conduction when theFermi level is above the conduction band edge, by applying high positive biasto the top gate. C 2015 Author(s). All article content, except where otherwisenoted, is licensed under a Creative Commons Attribution 3.0 Unported License.[http://dx.doi.org/10.1063/1.4922005]

INTRODUCTION

Amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs) are suitable forhigh resolution active-matrix organic light-emitting diode (AMOLED) displays because of theiroutstanding characteristics of high field-effect mobility (µFE) (> 10 cm2/V.s), low off current and lowsub-threshold swing (SS) (<0.2 V/decade).1 The device performances and reliabilities of a-IGZOTFTs are commonly studied with single gate (SG) inverted staggered TFTs.1–3 However, deviceuniformity, process repeatability and reliability under light illumination are still important issues.

The dual gate (DG) a-IGZO TFTs with bottom and top gates were investigated to control thethreshold voltage (VTH).4–8 In DG TFTs, the principal gate is the bottom-gate (BG) and secondarygate is top-gate (TG), both gates can be independently biased, while sweeping at BG terminal fromnegative bias to positive bias as conventional switching performance measurement.8 If two gates areelectrically tied together during sweeping, accumulation layer is not only confined to the a-IGZO/gateinsulator interfaces, but also spread out the entire depth of the a-IGZO, pointed as bulk accumulatedTFTs.4 It shows higher on-current (Ion), lower sub-threshold swing and better uniformity, comparedto SG a-IGZO TFTs.4 Higher current in DG TFTs can shrink the pixel sizes and increase the displayresolutions in AMOLED displays. Dual driving (during sweeping top and bottom gates were tiedtogether) can enhance the device uniformity and also help to suppress the negative bias illuminationinstabilities of a-IGZO TFTs.4,5 The source(S)/drain(D) overlap with TG is only the drawback in DGTFT structure, which can make a negative impact on switching speed due to large overlap capacitance.To solve this issue, top gate offset (spaced between S/D and TG) DG TFT structure was proposed,where the overlap capacitance is similar to that of a single gate TFT.9

aCorresponding author: [email protected]

2158-3226/2015/5(5)/057165/6 5, 057165-1 ©Author(s) 2015

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057165-2 Chun, Chowdhury, and Jang AIP Advances 5, 057165 (2015)

Following such advantages of DG a-IGZO TFTs, it is important to understand the physicalproperty of this devices. The temperature dependent characteristics of SG a-IGZO TFTs has beeninvestigated by many groups to understand the conduction mechanism.10–12

In this paper, we investigated the top gate voltage dependent transfer characteristics measuredat bottom gate terminal and temperature (from 25 to 70 oC) dependency in DG a-IGZO TFTs.The temperature dependent transfer characteristics were measured for top gate biased (VTG) -20,15,-10, -5, 0, +5, +10, +15 and +20V sequentially. Negative VTG shows an increment of saturationmobility with increasing temperature, due to the increment of free carrier concentrations by thermalexcitation to the conduction band from localized states.10,11,13 This trend is commonly observed inSG a-IGZO TFTs, while the Fermi level falls inside or below the tail states.11 On the other hand,positive VTG shows an opposite trend on temperature dependent saturation mobility. This can be ex-plained by carrier scattering with phonons under the condition that Fermi level is positioned abovethe conduction band (EF > EC).14,15 Such temperature dependent mobility under various TG biases(VTG’s) are well understood as the transition of semiconducting to metallic conduction behavior ina-IGZO TFTs.

EXPERIMENTAL

Amorphous-IGZO TFTs with the conventional back- channel- etch (BCE) structure and TGin Fig. 1(a) were fabricated according to the following process: A 60 nm thick molybdenum (Mo)layer was deposited on glass and patterned to form the BG. A bilayer of SiNX (100 nm) and SiO2

FIG. 1. Structure and characteristics of dual-gate a-IGZO TFTs with offset top-gates.(a) Schematic cross section; (b) opticalimage of a fabricated TFT with offsets of 1 µm at the source and drain electrode; (c) Transfer characteristics measured forVDS=0.1V at bottom gate (VBG) with sweeping from −20 to 20 V, while biasing the top gate (VTG) with various constantvoltage from -20V to +20V of 5V step (only VTG= -20V, sweep was measured from -20V to +30V); (d) Square root of thedrain current vs. VBG plots were obtained in the saturation regime (i.e., with VDS >VBG - VTH), while biasing the top gate(VTG) with various constant voltage from -20V to +20V of 5V step. The channel width (W) is 50 µm, and the channel length(L) is 20 µm.

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057165-3 Chun, Chowdhury, and Jang AIP Advances 5, 057165 (2015)

(150 nm) was deposited through plasma-enhanced chemical vapor deposition (PECVD) at 420 ◦Cas the bottom gate insulator, followed by the consecutive deposition of a 20 nm thick a-IGZO layerby sputtering at 200 ◦C, without breaking vacuum. After patterning the a-IGZO layer to form anactive island by wet etching with an indium tin oxide (ITO) etchant, a 150 nm thick Mo layer wasdeposited and patterned by a wet etch process to form the source and drain electrodes. To minimizedamage to the back channel of the active a-IGZO, a hydrogen peroxide (H2O2) based etchant wasused for the patterning of the source and drain electrodes.16 A 300 nm thick SiO2 layer was depos-ited as the TG insulator by PECVD at 300 ◦C. The TG insulator also plays a role as passivation ofthe a-IGZO layer and protect from exposure to air. Annealing was carried out at 250 ◦C in vacuumfor 4 hours to achieve a reproducible unstressed state. TG was formed by depositing a 120 nm thickMo by sputtering at 280 ◦C. Finally, a 200 nm SiO2 layer was deposited as a TFT passivation layerand additional 100 hours annealing was carried out at 250 ◦C in vacuum chamber.17

RESULTS AND DISCUSSION

The optical image of a-IGZO TFTs fabricated with TG length of 18 µm and offset of 1 µmbetween top gate and source/drain, is shown in Fig. 1(b). TFT size is defined with 20 µm channellength and 50 µm channel width. Transfer characteristics for drain voltage (VDS) of 0.1V, measuredfrom bottom gate terminal for various VTG biases from - 20 V to + 20 V with a step of 5V, are shownin Fig. 1(c). For all transfer characteristics bottom gate sweep was measured from -20V to +20V,except VTG= -20V, which was measured from -20V to +30V to extend visibility. Negative VTGdepletes the channel carriers, resulting in a positive shift of the threshold voltage in transfer charac-teristics.8 In contrast, the positive VTG induces a negative shift of VTH, owing to electron inductionin the channel.8 Fig. 1(d) shows square root of the drain current plot, obtained in the saturationregime (with VDS > VBG - VTH), for various VTG’s. The saturation mobility (µsat) is obtained using

µsat =IDS

1/2CoxBW/L(VBG − VTH)2 , (1)

where, CoxB is defined as bottom gate insulator capacitance, L is channel length and W is channelwidth. The extracted µsat for VTG = -20V is obtained 6.4 cm2/V·s, which gradually increased to19.1 cm2/V·s for VTG = +20V, as shown in Fig. 2(a). It is found that VTG (electron density is calcu-lated with the multiplication of top gate bias and top gate insulator capacitance) plays a critical roleon carrier concentration as well as Fermi level position in saturation regime. The slope of saturation

FIG. 2. (a) Saturation mobility and threshold voltage extracted from bottom gate seep in the saturation regime versus topgate induced electron density. The density is obtained with the multiplication of various top gate bias (from -20 to +20V) andtop gate insulator capacitance; (b) shows the changing of electron densities (∆n) with respect to top gate induced electrondensity.

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057165-4 Chun, Chowdhury, and Jang AIP Advances 5, 057165 (2015)

VTH (-3.5 x 10−12 V−1cm−1) and saturation mobility (+3.1 x 10−12 V−1s−1) with respect to top gatebias can be seen in Fig 2(a), pointing the correlation of VTH and mobility.

Fig. 2(b) show the changing of electron densities (∆n)18 in the channel with respect to varioustop gate biases, which is calculated using the equation (2),

∆n =C2

oxB

2qεsKBT∆VTH , (2)

where εs is the permittivity of a-IGZO, KB is the Boltzmann constant, T is the absolute temperatureand ∆VTH=VTH (VTG=-20V) - VTH (VTG=-15V to +20V). The electron density at VTG = 0V, isobserved ∼4.3 x 1018 cm−3, which gradually increases to ∼8.8 x 1018 cm−3 , when VTG increases to+20V and gradually decreases with decreasing VTG down to -20V.

In metal oxide based semiconductor based TFTs, the negative transfer shift under negative biasillumination stress is well understood by formation of positive charge (VO→VO

+/VO2+) from deep

level oxygen vacancy,12 which contribute free carriers in the channel. On the other hand, the positivetransfer shift during positive bias stress, is considered as the trapping of negative charges (freeelectrons) in the channel and interface.19

Top gate voltage dependent VTH shift and changing of carrier concentrations can be explainedby the movement of Fermi position by top gate bias.20 For negative VTG, EF gets dipper below EC,which move opposite direction with increasing the positive VTG amplitude. It is well known thata-IGZO contains broad range of subgap states due to the disorder of atoms and/or deficiency ofatoms.21 The decrement of carriers with respect to VTG from +20V to -20V shown in Fig. 2(b) isdue to the moving of EF from extended states to localized/midgap sates at back surface of IGZOchannel, thus free carrier localize and shifts the transfer positively.

To understand the top gate bias induced thermal activation, we plotted square root of thedrain current versus bottom gate voltage (VBG) characteristics, in the saturation regime at varioustemperatures from 25 to 70oC for a fixed VTG = +20, 0 and -20V, shown in Fig. 3(a), 3(b) and 3(c),respectively. The extracted saturation mobility at various temperatures is plotted in Fig. 4(a). ForVTG = -20V, µsat increases from 6.4 to 7.5 cm2/V·s with increasing the temperature from 25 to 70oC.The increment of saturation mobility with increasing temperature in SG a-IGZO TFTs is explainedas the thermal activation process with delocalization of free carriers from conduction band tailstates.14,15 In case of positive VTG = +20V, the mobility decreases from 19.1 to 15.4 cm2/V·s, withincreasing the temperature from 25 to 70 oC. The negative temperature coefficients are commonlyobserved in metal or degenerated semiconductors when EF > EC. To find the activation energy(Ea) for various top gate biases, we plotted the saturation mobility vs. T−1 in Fig. 4(a), using theArrhenius plot,

µsat = µsat0 exp(−Ea/KBT), (3)

where µsat0 is the prefactor of saturation mobility. For VTG = -20V, Ea = +32.5meV, which graduallydecreases to -37.2meV by increasing the top gate bias to VTG = +20V, shown in Fig. 4(b). The

FIG. 3. Square root of the drain current versus bottom gate voltage (VBG) characteristics were obtained in the saturationregime (i.e., with VDS >VBG - VTH) at various temperatures from 25 to 70oC. During temperature dependency measurementa constant bias was applied at top gate (VTG): (a) VTG=+20V, (b) VTG= 0V and (c) VTG=-20V.

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057165-5 Chun, Chowdhury, and Jang AIP Advances 5, 057165 (2015)

FIG. 4. (a) Plot of log saturation mobility (µsat) vs. 1/T at various constant top gate voltages (VTG’s) from -20V to +20Vwith a step of 5V; (b) activation energy of mobility as a function of electron density induced by top gate bias; (c) Plot of logµsat vs. 1/T for single (only bottom) gate a-IGZO TFT.

activation energy roughly defines the position of Fermi level and positive/negative polarity indicatesthe EF is below/above EC. From the position of EF, we see a clear evidence of electron conductionthrough the extended states/localized states, controlled by the top gate bias. The Fermi position forsingle gate TFT (without top gate) shown in Fig. 4(c), is found to be ∼11mev below the conductionband, which clarify the conduction mechanism in single gate devices are through band transportwith traps to the localized states below mobility edge.

It is well known that the carrier concentrations and Fermi position are correlated with eachother. A. Takagi et al. reported that the thermal activation in a-IGZO films are largely dependent onfree carrier concentrations and the degeneracy characteristics take place while the carrier concentra-tions are ≥1019cm−3.22 The electron conduction in a-IGZO is proposed by percolation conductiontheory, where the electrons need to pass through the Gaussian distribution of energy barriers withan average barrier height of 50meV.21,23 These barriers are originated by the disorder of Ga+/Zn+

cations, which make the Gaussian type distribution around EC in amorphous IGZO.21

The negative temperature coefficient of µsat observed for positive VTG (shown in Fig. 4(a)),can be explained by carrier scattering , while EF is within the extended states. Band mobility (atEF > EC) in a-IGZO is originated by cation scattering, phonon scattering, and ion scattering.24 Ifthe temperature (thermal energy) increases from 25 to 70 oC, the band mobility is assumed todecrease due to the domination of phonon scattering. When EF is above EC, the carrier concentrationgoes higher and the scattering from carriers-carriers, carriers-cations and carriers-phonons influenceto the saturation mobility in a-IGZO TFTs. This trend is clearly proposed as the transition fromsemiconducting to metallic behavior of a-IGZO TFTs, controlled by VTG.

CONCLUSION

In summary, we report the change in electron transport by controlling Fermi level by top gatebias in DG a-IGZO TFTs. Temperature dependent saturation mobility was measured in the BGterminal with a fixed top gate voltage. When the top gate bias is positive, a-IGZO TFTs show themetallic property, due to the position of EF above EC. On the other hand, applying negative TG biasplaced EF below EC and the mobility shows thermally activated process and thus saturation mobilityincreases with temperature, showing semiconductor property. The thermally activated conduction inextended states clearly reveals the existence of energy barrier which is greater than 37.2meV.

ACKNOWLEDGEMENTS

This work was supported by the Industrial Strategic Technology Development Program (10045269, Development of Soluble TFT and Pixel Formation Materials/Process Technologies forAMOLED TV) funded by MOTIE/KEIT.

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