Semiconductor Design Solutions for IMS 3 Agenda IMS goals and implications Network media processing requirement Semiconductor design solutions Conclusions.

Semiconductor Design Solutions for IMS

3

Agenda

• IMS goals and implications

• Network media processing requirement

• Semiconductor design solutions

• Conclusions

4

Media Compression & Transport

• Media compression standards have been tightly coupled with transport mechanism for telecommunications from inception

– TDM based PSTN is built on top of G.711 standard– GSM is tied to GSM FR compression standard– Rate-set 1 is built into the physical layer protocol of CDMA

system

• Standards are snapshots of past technology– G.729a/b was developed in 1995– GSM AMR (AMR-NB) was developed in 1998– Newer technologies available today can deliver better

performances and are more suitable for targeted applications

5

Issue With Current Systems

• Coupling of compression standard with transport mechanism prevents use of newer or other compression schemes, therefore limits market growth

– Physical layer changes are often required, resulting in unwanted equipment cost increase or even new upgrades

• Deployment of EVRC on CDMA networks caused large scale network equipment upgrade

• 3G wireless and NGN core network - IP based– It is logical to make access networks that support IP based

technologies and services in order to simplify network equipment

– Fix-Mobile Convergence (FMC) becomes possible and has many advantages to support new value-add services

6

IMS Objectives

• Deliver richer, more personalized IP based multi-media communication services

• Fully integrated real-time or non-real-time multi-media communication services

• Network Convergence (FMC): allowing seamless mobility across heterogeneous networks such as fixed, mobile, broadband, etc.

• Support for third-party content and services, therefore, a vastly expanded universe of potential revenue streams

• Improve user experience in setting up multiple services in one single session or multiple simultaneously synchronized sessions

7

Media Transport Characteristics

• Media transport over IP framework– Voice / video over IP– IP based content delivery

• Services become independent from access or transport technologies

– E.g. instant messenger service on a PC or on a cell-phone– Compression standards are no longer tied to physical layer

protocols• Seamless transition of media type in a single communication

session– Text, video, voice, audio

• Different QoS expectations based on purchased / used access technologies

– Users generally expect higher QoS on fixed line, especially with broadband access; while wireless users might accept a gracefully reduced QoS

• Services expansion– Ease of introduction of new media processing standards or DSP

functions

8

IMS Network Media Processing Requirement

• Simultaneous support of wireline / wireless media compression standards

– Due to IPR cost and associated complexity, it is unreasonable to assume end-points would support all media processing standards

• Transcoding / transrating to guarantee inter-operability– IMS core network equipment entities need to support transcoding /

transrating in order to bridge end-points that don’t have a common media compression scheme

• Multi-media conferencing• Rich contents

– Wide-band voice, high quality audio

• Different service quality grades– Chargeable and manageable

• Future proof– To support new services that might require introduction of new

media standards

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Manufacturers Challenges

• Cost effective support of large amounts of essential features– Voice:

• Wireline: G.711, G.726, G.728, G.729a/b, G.723.1/a, G.729e/g, G.722, G.722.1, G.722.2, G.729.1, iLBC

• W-CDMA/GSM: FR, HR, EFR, GSM AMR, AMR-NB, AMR-WB• CDMA: QCELP8K/13K, EVRC, EVRC-B, VMR, SMV

– Video:• H.263, H.264, MPEG-4, AVC, WMV, MJPEG, etc.

– Packet / Protocol processing:• TFO, TrFO, CSD, CTM, TTY/TTD, H.324M, Media Forking, Lawful

Interception, Encryption, etc.• Need non-standard based advanced DSP functions

– Multi-party, multi-standards, multi-interfaces (e.g. TDM, Packet side) conference bridge

– Transcoding between different standards / Transrating within a standard

– Synchronization amongst media streams, presumably processed by different HW elements

• Future proof– SW upgradeable architecture

10

IMS / FMC MGW Requirements

• VoIP / Wireless TDM-to-Packet capability– Wireline VoIP

• High density G.711 only Trunk GW & Low latency G.711 only Trunk GW

• PacketCable

– Wireless media GW or base-station base-band processing• W-CDMA / GSM• CDMA2000 / CDMA• TD-SCDMA

• Packet-to-Packet capability– Transcoding without pay-load format conversion, e.g.,

CDMA(EVRC)VoIP(EVRC)– Transcoding with pay-load format conversion, e.g., IuUP(AMR-

NB)VoIP(G.729AB), or IuUP(AMR-WB)VoIP(G.729.1-WB)– Packet-side conferencing

• Mixture of TDM-to-Packet and Packet-to-Packet capability– Multi-function media gateway– Network convergence MGW

11

Industry Solution Trends

• IMS ready SoC solutions– Simultaneous support of all media compression standards on the

same chip (eg. Mindspeed Comcerto® for voice)

– Future proof capability based on downloadable HW/SW architecture

– Often it is a clean and optimal design from ground up

• Manufacturer in-house development– Typically by established equipment manufacturers

– Evolved either from fixed-line MGW, or wireless MGW• Might be sub-optimal: optimized MGW for fixed-line NGN might not

have the right HW/SW architecture or resources mixture to also be optimized for wireless applications

– Future proof concern• E.g., existent HW processing capacity and memory space

Chip Technology Solutions

CMOS Scaling Limit Implications

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CMOS Scaling Limits

• “Electrical consequences of industry-trend scaling (points) are contrasted to classic scaling (dashed curves). While the inverter delay scales nearly the same as the classic case (as LGATE), the active-power density does not. Instead, the active-power density increases with decreasing LGATE because of the lag in VDD reduction, which is only partially mitigated by a reduction in GGATE. IDSAT is the drain current drawn with the gate and drain voltages set at the nominal power-supply voltage, VDD”.

• E.J. Nowak, IBM J. RES. & DEV. VOL. 46 NO. 2/3 MARCH/MAY 2002

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The Rise of Leakage Power

• “Active-power density and subthreshold-leakage-power density trends calculated from industry trends … are plotted vs. LGATE (points), for a junction temperature of 25C. Empirical extrapolations (dashed curves) suggest that subthreshold power will equal active power at LGATE 20 nm; this point is encountered closer to LGATE 50 nm when elevated temperatures, typically required of applications, are factored in. This collision, already encountered by applications that are more power-sensitive, will spur further circuit and technology design efforts to manage subthreshold leakages”.

15

CMOS Scaling Conclusions

• CMOS scaling continues to provide more transistors per die area

– Cost per transistor continues downward ~ square of gate length

• CMOS scaling continues to provide faster transistors

– Inverter delays decreasing ~ one over the gate length

• CMOS scaling is stalling on active power improvements

– About same switching power density (about same power per area)

• CMOS scaling is getting worse on in-active power

– High temperature can make this exponentially worse

The Predominate CMOS SoC Design Limits are Now Power and Thermal Density Costs

Chip Architecture Solutions

Increasing Thread Level Parallelism

17

Processor Architecture Trends (Multi-Core)

“Discovering Multi-Core: Extending the Benefits of Moore’s Law” - Intel Technology Magazine – July 2005.

• “First, memory speeds are not increasing as quickly as logic speeds.”• “As …interconnects stretch from hundreds to thousands of meters in

length on a single processor, path delays … cancel the speed increases of the transistors.”

• “A 1993-era Intel Pentium processor had around 3 million transistors while today’s Intel® Itanium® 2 processor has nearly 1 billion transistors.

– If this rate continued, Intel processors would produce more heat per square centimeter than the surface of the sun—which is why the problem of heat is already setting hard limits to frequency.”

Conclusion:“Multi-core chips do more work per clock cycle, and thus can be designed to operate at lower frequencies than their single-

core counterparts. Since power consumption goes up proportionally with frequency, multi-core architecture gives

engineers the means to address the problem of runaway power and cooling requirements.”

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Processor Architecture Trends (Large On-Chip Memory)

• Off-chip memory access performance hasn’t kept pace– DDR2-667MHz vs. 3GHz processors

• Trend is to incorporate larger & wider internal memories– 2MByte internal caches, etc.

– 256 bit wide access on chip access, etc.

• Simultaneous support of large number of media compression standards can only be possible by using external memories

– 64MBytes external memory capacity vs. 2-5MBytes internal memory capacity

19

Chip Architecture Conclusions

• Power and thermal density limits are driving chip architectures from frequency scaled single cores to area scaled multi-cores

– Intel Pentium 4 to Intel Pentium D (Dual)• 90nm 3.83GHz to 3.2GHz

– AMD Athlon FX to AMD Athlon X2 Dual• 90nm 2.8GHz to 2.6GHz

• Further power and performance gains come from incorporating application specific processors with multi-core general purpose processors

– X-Box 360 Xeon Processor – Three 3GHz Cores + Graphic Processor

Processor Architectures are Trending Away from Frequency Scaling of General Purpose Processors

to Multi-Core Scaling of General and Application Specific

Processors

VoIP Systems Solutions For IMS/FMC

Application (VoIP) Specific Systems

21

Multi-Core Solutions

• In VoIP SoC solutions, many identical VoIP threads are run– This application decomposes nicely to many low frequency parallel

threads

– The most optimum power, area, and cost solution is to provide many application optimized processors on a single die

• For IMS/FMC applications, efficient support of different VoIP threads is a must

– Multi-core architecture fits this need nicely

22

Infrastructure Multi-Core Solutions

• Comcerto 600– 150nm CMOS process

– 6 cores (2 RISCs, 4 DSPs) – 6 simultaneous “VoIP” threads


– 8 cores (2 RISCs, 6 DSPs) – 8 simultaneous “VoIP” threads


– 18 cores (2 RISCs, 8 DSPs, 8 DSP CPs) – 18 simultaneous “Voice-o-IP or Video-o-IP” threads

23

Comcerto 900 Architecture

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Comcerto 900 DSP Sub-System

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Comcerto 900 SW Architecture

Comcerto SW architecture from start was driven by flexible channel type strategy that is now fundamental for FMC, multi-function GW and SBC applications

1. HW resources allocation strategy• External SDRAM/DDRAM used for SW storage and packet / network processing, providing future upgradeability

• Embedded RAM used for active program codes and DSP context storage of active channels– All DSP cores run from the codes on E-RAM, so the SoC itself is not limited to any particular application

• DSP processing power and tightly coupled fast memories are used for active channels

2. Time division allocation of DSP resources• Each DSP core and associated tightly coupled fast memories are independently allocated from other DSP cores

• Time division allocation of DSP resources

3. Intelligent resources manager to optimize HW resources allocation and maximize efficiency

DSP core-0TC Mem 0

DSP core-1TC Mem 1

DSP core-2TC Mem 2

DSP core-7TC Mem 7

Time

20ms

AMR-NB channel G.729AB/20ms

Exam

ple

of M

atiss

e DS

P re

sour

ces

allo

catio

n

G.711/20ms

One AMR-NB channel with one frame processing every 20ms

EVRC-B channelEVRC Transcoding EVRCG.729G.729AB/10ms

26

Conclusions

• Telecommunication industry will move away from tightly coupled compression standards and access/transport networking. IMS seems to be a good next step

• FMC is an inevitable trend of the industry for many economical reasons, and IMS is a good framework for it

• More demanding IMS network infrastructure equipment– Support large amount of media compression standards and

processing functions

– Flexible and efficient use of HW resources

– Future proof requirement

• Advanced non-standard based DSP technologies are required to support future growth of IMS applications

• Semiconductor HW / SW architecture and design capability are keys to support this evolution of the telecom industry

Semiconductor Design Solutions for IMS 3 Agenda IMS goals and implications Network media processing requirement Semiconductor design solutions Conclusions.

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