Self-Balancing Supercapacitor Energy Storage System Based ...

Citation: Hernandez, F.D.;

Samanbakhsh, R.; Ibanez, F.M.;

Martin, F. Self-Balancing

Supercapacitor Energy Storage

System Based on a Modular

Multilevel Converter. Energies 2022,

15, 338. https://doi.org/10.3390/

en15010338

Academic Editors: João L. Afonso

and Francesco Lufrano

Received: 11 November 2021

Accepted: 20 December 2021

Published: 4 January 2022

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energies

Article

Self-Balancing Supercapacitor Energy Storage System Based ona Modular Multilevel ConverterFernando Davalos Hernandez 1,2,* , Rahim Samanbakhsh 1 , Federico Martin Ibanez 1 and Fernando Martin 3,4

1 Department of Electrical Engineering, Skolkovo Institute of Science and Technology, 143026 Moscow, Russia;[email protected] (R.S.); [email protected] (F.M.I.)

2 Facultad de Ingeniería, Universidad Panamericana, Aguascalientes 20296, Mexico3 CEIT-Basque Research and Technology Alliance (BRTA), Manuel Lardizabal 15, 20018 Donostia, Spain;

[email protected] Teoría do sinal e comunicacións, Universidad de Navarra, Tecnun, Manuel Lardizabal 13,

20018 Donostia, Spain* Correspondence: [email protected]; Tel.: +52-3951127190

Abstract: Energy Storage Systems (ESS) are an attractive solution in environments with a high amountof renewable energy sources, as they can improve the power quality in such places and if required,can extend the integration of more renewable sources of energy. If a large amount of power is needed,then supercapacitors are viable energy storage devices due to their specific power, allowing responsetimes that are in the range of milliseconds to seconds. This paper details the design of an ESS thatis based on a modular multilevel converter (MMC) with bidirectional power flow, which reducesthe number of cascaded stages and allows the supercapacitors SCs to be connected to the grid toperform high-power transfers. A traditional ESS has four main stages or subsystems: the energystorage device, the balancing system, and the DC/DC and DC/AC converters. The proposed ESS canperform all of those functions in a single circuit by adopting an MMC topology, as each submodule(SM) can self-balance during energy injection or grid absorption. This article analyses the structure inboth power flow directions and in the control loops and presents a prototype that is used to validatethe design.

Keywords: renewable energy sources; supercapacitors; energy storage system

1. Introduction

Supercapacitors (SCs) have the highest power density relative to Li-ion batteries,flywheels, fuel cells, and superconducting magnetic energy storage systems [1,2]. AlthoughSC technology is still maturing, this high-power density comes with a cost, namely thatSCs are usually low voltage devices, usually around 2.5 V to 3.0 V [3]. This problem canbe overcome by using series connections with passive or active balancing systems, thelatter being more efficient [4,5]. However, in terms of design, this added circuitry createsa more complex and expensive Energy Storage System (ESS) that is also susceptible tofailure because of the many parts that are involved in the system [6,7]. Typical applicationsof SC-based ESSs are related to fast energy injection or absorption [8,9]. For example, inisolated microgrids with a high penetration of renewables [10], SCs maintain the powerbalance between consumption and generation because inertia mechanisms are limited.SCs can also be used in conjunction with batteries to create a hybrid ESS, increasing thecapabilities of the system [11].

A basic SC-based ESS is composed of a balancing system, SC cells, a DC/DC converter,a DC link capacitor, and a DC/AC converter, as Figure 1 shows [8,12]. An ESS needs tokeep energy storage devices balanced, protect them from overvoltage, and create the outputvoltage using bidirectional DC/DC and DC/AC conversions. The SC voltage changeslinearly along with the state of charge, so a DC/DC converter with a wide input voltage

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Energies 2022, 15, 338 2 of 19

range and a constant DC output voltage tends to be needed [13]. A DC link connectsthe DC/DC converter to a traditional DC/AC converter, which creates an AC signal. Inaddition, as galvanic isolation is important when the ESS is connected to the grid, a bulky50Hz transformer must be used if none of the other stages has isolation, which increasesthe converter’s size. Each of these circuits or stages requires a careful design process inorder to accomplish the power budget.

Energies 2022, 15, x FOR PEER REVIEW 2 of 20

changes linearly along with the state of charge, so a DC/DC converter with a wide input voltage range and a constant DC output voltage tends to be needed [13]. A DC link con-nects the DC/DC converter to a traditional DC/AC converter, which creates an AC signal. In addition, as galvanic isolation is important when the ESS is connected to the grid, a bulky 50Hz transformer must be used if none of the other stages has isolation, which in-creases the converter’s size. Each of these circuits or stages requires a careful design pro-cess in order to accomplish the power budget.

Some authors have been studying different DC/DC converter topologies for ESS that can be used for DC microgrids or for AC grids. In [14,15], the proposed converter lacks isolation, limiting its applications. In [16], an optimized supercapacitor control strategy in combination with a Double Active Bridge (DAB) is proposed, but an active or passive balancing system as well as a DC/AC inverter are still required to interact with the grid. In [17,18], the proposed converters can directly interface the energy storage device with the AC grid; however, it still requires an additional balancing system.

Instead of the traditional approach, a Modular Multilevel Converter (MMC) can be used, which is based on a high-voltage DC source and a series of submodules (SMs). In this system, DC/DC and DC/AC conversions are performed in the SMs, which consist of DC/DC converters. These MMC topologies have been used for high-voltage DC transmis-sion [19,20]. One of the main advantages of MMCs is the simplicity of scaling up the volt-age of the system by adding more SMs to the MMC [21], as shown in Figure 2a.

The relevant aspect of this work is the integration of a single SC in each of the SMs, and therefore, no high voltage DC source is needed. In addition, each SM works in a volt-age range of 1.5–2.7 V, which allows the use of low-voltage switches with low conduction losses [22] and a low total harmonic distortion (THD) of the AC output voltage and cur-rent possible.

Other authors have studied low-voltage MMC [23], for example, for railway traction systems, in which each supercapacitor is integrated in every SM, but these applications have only been studied analytically [22]. Low-voltage MMC was also studied for its po-tential use in STATCOMs applications by incorporating the ESS into the MMC; however, this was only possible by adding an additional DC/DC converter [24]. The same occurs in power traction converters, where for adding SCs, a DC/DC converter was added [25]. In [26], the proposed MMC integrates the SCs in each SM, and a balancing strategy is pre-sented; however, the ESS requires a bulky transformer if isolation is required.

Figure 1. Traditional SC-based ESS block diagram; arrows indicate bidirectional current flow.

This paper proposes an SC-based ESS using an MMC in which each SM contains an energy storage device (a single SC) and a bidirectional isolated DC/DC converter. The proposed MMC diagram is shown in Figure 2b. The DC/DC converter acts a controllable DC voltage source. Thus, the MMC becomes a series chain of controllable voltage sources and, with the correct control strategy, the SMs can create an AC output signal: vMMC(t). Therefore, the main contribution of this research is the development of an ESS that is based on an MMC that can perform the functions of energy storage, voltage balancing, and bi-directional DC/DC and DC/AC conversion with galvanic isolation in a single block (or SM), resulting in a self-balancing MMC that is easily expandable to higher voltages and that is controllable with a central controller. A prototype validates the proposed ESS, and the prototype shows how the circuit works; however, the efficiency is not optimized and can be further improved through the use of GaN or SiC transistors.

Figure 1. Traditional SC-based ESS block diagram; arrows indicate bidirectional current flow.

Some authors have been studying different DC/DC converter topologies for ESS thatcan be used for DC microgrids or for AC grids. In [14,15], the proposed converter lacksisolation, limiting its applications. In [16], an optimized supercapacitor control strategyin combination with a Double Active Bridge (DAB) is proposed, but an active or passivebalancing system as well as a DC/AC inverter are still required to interact with the grid.In [17,18], the proposed converters can directly interface the energy storage device with theAC grid; however, it still requires an additional balancing system.

Instead of the traditional approach, a Modular Multilevel Converter (MMC) can beused, which is based on a high-voltage DC source and a series of submodules (SMs). Inthis system, DC/DC and DC/AC conversions are performed in the SMs, which consistof DC/DC converters. These MMC topologies have been used for high-voltage DC trans-mission [19,20]. One of the main advantages of MMCs is the simplicity of scaling up thevoltage of the system by adding more SMs to the MMC [21], as shown in Figure 2a.


This paper is structured as follows. Section 2 presents SM operation in both power flow directions. Section 3 details the MMC operational modes and the self-balancing con-trol that is embedded in each SM. Section 4 presents the simulations of the proposed SC-based MMC, which validates the described operational modes in Section 3. Section 5 de-scribes the experimental tests and a comparison with other converters in terms of effi-ciency and the stages that are involved. Finally, Section 6 concludes the paper.

(a) (b)

Figure 2. Block diagram for (a) traditional and (b) proposed MMC topology.

2. Submodule Operation The DC/DC converter in the SM is a bidirectional full-bridge topology with an active

clamp and a low pass filter (L1–C1), as shown in Figure 3. This topology has ease of control and design as well as galvanic isolation. It allows bidirectional current flow from/to the SC (𝑉 ) to/from the load (Vo). This converter offers soft-switching capabilities and uses synchronous rectification and an active clamp (Cc, Qc) to reduce the voltage stress in the switches. Figure 3a shows that the SC is attached to the 1st bridge (Q1 to Q4), isolation is provided by transformer T1, and Q5 to Q8 are used in the boost side (2nd bridge). This topology was first proposed in [27].

(a)

(b)

Figure 3. Submodule: (a) bidirectional full-bridge circuit, (b) inner control loop.


The relevant aspect of this work is the integration of a single SC in each of the SMs, andtherefore, no high voltage DC source is needed. In addition, each SM works in a voltagerange of 1.5–2.7 V, which allows the use of low-voltage switches with low conductionlosses [22] and a low total harmonic distortion (THD) of the AC output voltage andcurrent possible.

Other authors have studied low-voltage MMC [23], for example, for railway tractionsystems, in which each supercapacitor is integrated in every SM, but these applications haveonly been studied analytically [22]. Low-voltage MMC was also studied for its potentialuse in STATCOMs applications by incorporating the ESS into the MMC; however, this wasonly possible by adding an additional DC/DC converter [24]. The same occurs in powertraction converters, where for adding SCs, a DC/DC converter was added [25]. In [26],

Energies 2022, 15, 338 3 of 19

the proposed MMC integrates the SCs in each SM, and a balancing strategy is presented;however, the ESS requires a bulky transformer if isolation is required.

This paper proposes an SC-based ESS using an MMC in which each SM contains anenergy storage device (a single SC) and a bidirectional isolated DC/DC converter. Theproposed MMC diagram is shown in Figure 2b. The DC/DC converter acts a controllableDC voltage source. Thus, the MMC becomes a series chain of controllable voltage sourcesand, with the correct control strategy, the SMs can create an AC output signal: vMMC(t).Therefore, the main contribution of this research is the development of an ESS that isbased on an MMC that can perform the functions of energy storage, voltage balancing, andbidirectional DC/DC and DC/AC conversion with galvanic isolation in a single block (orSM), resulting in a self-balancing MMC that is easily expandable to higher voltages andthat is controllable with a central controller. A prototype validates the proposed ESS, andthe prototype shows how the circuit works; however, the efficiency is not optimized andcan be further improved through the use of GaN or SiC transistors.

This paper is structured as follows. Section 2 presents SM operation in both powerflow directions. Section 3 details the MMC operational modes and the self-balancing controlthat is embedded in each SM. Section 4 presents the simulations of the proposed SC-basedMMC, which validates the described operational modes in Section 3. Section 5 describesthe experimental tests and a comparison with other converters in terms of efficiency andthe stages that are involved. Finally, Section 6 concludes the paper.

2. Submodule Operation

The DC/DC converter in the SM is a bidirectional full-bridge topology with an activeclamp and a low pass filter (L1–C1), as shown in Figure 3. This topology has ease of controland design as well as galvanic isolation. It allows bidirectional current flow from/to theSC (VSC) to/from the load (Vo). This converter offers soft-switching capabilities and usessynchronous rectification and an active clamp (Cc, Qc) to reduce the voltage stress in theswitches. Figure 3a shows that the SC is attached to the 1st bridge (Q1 to Q4), isolation isprovided by transformer T1, and Q5 to Q8 are used in the boost side (2nd bridge). Thistopology was first proposed in [27].


This paper is structured as follows. Section 2 presents SM operation in both power flow directions. Section 3 details the MMC operational modes and the self-balancing con-trol that is embedded in each SM. Section 4 presents the simulations of the proposed SC-based MMC, which validates the described operational modes in Section 3. Section 5 de-scribes the experimental tests and a comparison with other converters in terms of effi-ciency and the stages that are involved. Finally, Section 6 concludes the paper.

(a) (b)


2. Submodule Operation The DC/DC converter in the SM is a bidirectional full-bridge topology with an active

clamp and a low pass filter (L1–C1), as shown in Figure 3. This topology has ease of control and design as well as galvanic isolation. It allows bidirectional current flow from/to the SC (𝑉 ) to/from the load (Vo). This converter offers soft-switching capabilities and uses synchronous rectification and an active clamp (Cc, Qc) to reduce the voltage stress in the switches. Figure 3a shows that the SC is attached to the 1st bridge (Q1 to Q4), isolation is provided by transformer T1, and Q5 to Q8 are used in the boost side (2nd bridge). This topology was first proposed in [27].

(a)

(b)

Figure 3. Submodule: (a) bidirectional full-bridge circuit, (b) inner control loop. Figure 3. Submodule: (a) bidirectional full-bridge circuit, (b) inner control loop.

Energies 2022, 15, 338 4 of 19

2.1. Buck-Mode (VSCC → Vo)

The circuit can be analyzed by taking five-time intervals (from t1 to t6) in one half of aswitching period (TS). The duty cycle for Q1, Q2, Q3, and Q4 is fixed at 50%, and the phaseshift (φ) between legs Q1, Q3 and Q2, Q4 is the control variable.

The main buck-mode waveforms are presented in Figure 4. Before the first-timeinterval (before t1), Q1 and Q2 are on, and Q3, Q4, and Qc are off. This means that thevoltage in the transformer’s primary winding is zero (vtp = 0). The 2nd bridge (Q5–Q8) isconducting at the same time. The diodes from Q5–Q8 are on, and the synchronous rectifiers(Q5 and Q6) are working, so the transformer’s secondary voltage (vts) is zero and v′c = 0,but VCc ≈ n·VSC, where n is the transformer turn ratio. Therefore, there is no energytransfer from the primary to the secondary winding of the transformer. In addition, iLlk = 0due to the previous cycle. The inductor current (iL1) flows through the 2nd bridge andthrough the load. As v′c = 0 and vCc > 0, iCc = 0 (diode of QC is blocking). This initialcondition is the final condition in the last time interval of the previous half-cycle.


Figure 4. Buck-mode waveforms.

In order to control the SM, a small-signal analysis is performed. Let us simplify the time-interval analysis to only two main intervals. One from t2 to t5, where 𝑣′ = 𝑛 · 𝑉 , called on-state, and the other with the rest of the intervals, where 𝑣′ = 0, which is called the off-state. The state model for the on-state is (t5 − t2) = 𝜙TS: 𝑖𝑣 = 0 −1/𝐿1/𝐶 −1/(𝑅𝐶 ) × 𝑖𝑣 + 1/𝐿0 . 𝑛 × 𝑣 . (9)

For the off-state, it is (1-𝜙)TS: 𝑖𝑣 = 0 −1/𝐿1/𝐶 −1/(𝑅𝐶 ) × 𝑖𝑣 + 1/𝐿0 . 0. (10)

Therefore, using the averaging approach during TS/2, the complete model is ob-tained: 𝑑𝑑𝑡 ⟨𝑖 ⟩⟨𝑣 ⟩ = ⎣⎢⎢

⎡ 0 −1𝐿1𝐶 1𝑅𝐶 ⎦⎥⎥⎤ × ⟨𝑖 ⟩⟨𝑣 ⟩ + 1𝐿0 . 2𝜙. ⟨𝑛 × 𝑣 ⟩, (11)

where the < > represents the average in one switching period, and 𝜙 is shown in Figure 4. In addition, to obtain the small signal model, the variables are: ⟨𝑥⟩ = 𝑋 + 𝑥, where X is the average value and 𝑥 is the small signal perturbation. Thus, the model in (11) becomes: 𝑑𝑑𝑡 𝐼 + 𝚤𝑉 + 𝑣 = ⎣⎢⎢

⎡ 0 −1𝐿1𝐶 1𝑅𝐶 ⎦⎥⎥⎤ × 𝐼 + 𝚤𝑉 + 𝑣 + 2𝐿0 . 𝜙 + 𝜙 . 𝑛(𝑉 + 𝑣 ), (12)

then, by considering the perturbations on their own and by linearizing the model, the following expression can be obtained: 𝑑𝑑𝑡 𝑖𝑣 = ⎣⎢⎢

⎡ 0 −1𝐿1𝐶 1𝑅𝐶 ⎦⎥⎥⎤ × 𝚤 + 1𝐿0 . 𝑛. 𝜙. 𝑣 + 𝑉 𝜙 , (13)

Finally, the Laplace transformation can be used as an output function of the control (control-to-output), and the input voltage can be obtained:

Figure 4. Buck-mode waveforms.

In the 1st time interval, [t1, t2], Q1, and Q4 are on, Q3 and Qc are off, and vLlk = VSC.As iLlk (t1) = 0, Q2 turns off at the zero current and Q4 also turns on at the zero current.Llk governs the current slope during the transition. Thus, both transitions occur duringsoft switching.

In the 2nd bridge, iL1 is still flowing through the 2nd bridge diodes and synchronizedrectifiers (Q5 and Q8), so v′c = 0. This is equivalent to the off-time in the continuous modefor a buck converter, so the L1 current follows:

iL1(t) = iL1(t1)−Vo

L1(t− t1), (1)

because v′c = 0, this is valid from t1 to t2. iLlk continues to increase until the current in thesecondary winding (its) reaches iL1 and the diodes of Q6 and Q7 turn off. Therefore, for the1st time interval, the iLlk current is governed by:

VSC = LlkdiLlk

dt, (2a)

Energies 2022, 15, 338 5 of 19

which can be rewritten as:iLlk =

VSCLlk

(t− t1). (2b)

The time interval ends when iLlk (t2) = n·iL1(t2). At that moment, the 2nd time intervalstarts [t2, t3]. Q2, Q3, and QC are still off and Q1 and Q4 are still on (so there are no switchingtransitions between the 1st and 2nd intervals). Q6 and Q7 and their diodes are already off,and Q5 and Q8 are on. The diode of QC starts conducting, so v′c jumps to vCc(t2), which isa value that is slightly lower than n·VSC, resulting in CC being charged. The equations thatgovern the 2nd time interval are (considering Lmag >> Llk and n2Llk << L1); for iLlk , we firstsubtract the charging voltage v′c/n:

VSC −v′cn

= LlkdiLlk

dt, (3a)

then iL1 starts to increase following:

v′c −Vo = L1diL1

dt, (3b)

The charging current iCc is described by:

iCc = Ccdv′cdt

, (3c)

Hence, the relationship between ilk, iCc, and iL1 is:

ilkn− iCc = iL1, (3d)

Finally, the solution for iL1 can be obtained:

iL1∼= iL1(t2) +

n·VSC −Vo

L1(t− t2) +

Llkn2

L1.Vo.(t− t2)−

n·VSC + Llkn2

L1.Vo − vCc(t2)

ω0L1sin(ω0(t− t2)), (4)

where the resonant frequency is ω0 =[Ccn2Llk

]−1. v′c, iCc, and iLlk can be derived from(3) using (4). Notice that if n·VSC − vCc(t2) is small, ω0(t3 − t2) << 1, and consideringn2Llk L1, the last two terms of (4) can be neglected. Thus (4) is the same as in the on-timeof a buck converter.

This time interval ends when Q1 is turned off and when the 3rd time interval, [t3, t4],starts. The iLlk flows through the diode of Q3 and Q4, and QC is on. Again consideringω0(t4 − t3) <<1):

iL1(t) ∼= iL1(t3) +vCc(t3)−Vo

L1(t− t3). (5)

As vCc(t3) ≈ n·VSC, (5) follows the on-state of a buck converter. CC delivers energyto reset Llk (iLlk = 0). Then, Cc should have at least enough energy to reset Llk. This puts alower limit on CC:

LLki2Lk(t3)

2<

Cc(v2Cc(t3)− v2

Cc(t4))

2, (6a)

which for design purposes is:

CC LLk I2

0maxV2

SCmin, (6b)

where the low current ripple (Io = iLlk (t3)/n) and vCc(t3) = n·VSC, and min and max are themaximum and minimum design values.

Energies 2022, 15, 338 6 of 19

In the 4th time interval, [t4, t5], QC, Q4 are on but iLlk = 0, so the diode of Q3 is off, andCC is feeding L1. As this interval is short, ω0(t5 − t3) << 1, so the v′c and iL1 are:

v′c(t) ∼= v′c(t4)−iL1(t4)

Cc(t− t4) (7a)

iL1(t) ∼= iL1(t4) +v′c(t4)−Vo

L1(t− t4). (7b)

Thus, if v′c(t4) ∼= n·VSC, the buck converter equation remains. To achieve that, CCshould be big enough to not be completely discharged by Llk, as proposed by (6).

In the 5th time interval, [t5, t6], QC is turned off, the diodes of Q5–Q8 turn on, andright after that, Q7 turns on at zero voltage. Then, Q3 can turn on when the current andvoltage are zero (soft switching). Thus, v′c goes to zero, and iL1 behaves as an off-timebuck converter.

To summarize, the first-time interval is off-time, the second, third, and fourth areon-time intervals, and the fifth is an off-time interval. The voltage transfer function can beobtained as it was in the buck converter when v′c(t2) ∼= v′c(t3) ∼= v′c(t4) ∼= v′c(t5) = nVSC:

M =Vo

VSC∼= n

t5 − t2TS2

≈ n2φ (8)

This mode is called buck-mode because M approximately follows the same equationas the buck converter; M varies linearly with the control variable φ, where controlling φis sufficient to control the amount of energy that is transferred from the supercapacitor tothe grid.

In order to control the SM, a small-signal analysis is performed. Let us simplify thetime-interval analysis to only two main intervals. One from t2 to t5, where v′c = n ·VSC,called on-state, and the other with the rest of the intervals, where v′c = 0, which is calledthe off-state. The state model for the on-state is (t5 − t2) = φTS:

ddt

[iL1vo

]=

[0 −1/L1

1/C1 −1/(RC1)

]×[

iL1vo

]+

[1/L1

0

].n× vSC. (9)

For the off-state, it is (1-φ)TS:

ddt

[iL1vo

]=

[0 −1/L1

1/C1 −1/(RC1)

]×[

iL1vo

]+

[1/L1

0

].0. (10)

Therefore, using the averaging approach during TS/2, the complete model is obtained:

ddt

[iL1vo

]=

[0 −1

L11

C11

RC1

]×[

iL1vo

]+

[1L10

].2φ.n× vSC, (11)

where the < > represents the average in one switching period, and φ is shown in Figure 4.In addition, to obtain the small signal model, the variables are: x = X + x, where X is theaverage value and x is the small signal perturbation. Thus, the model in (11) becomes:

ddt

[IL1 + iL1Vo + vo

]=

[0 −1

L11

C11

RC1

]×[

IL1 + iL1Vo + vo

]+

[2L10

].(φ + φ).n(VSC + vSC), (12)

then, by considering the perturbations on their own and by linearizing the model, thefollowing expression can be obtained:

ddt

[iL1vo

]=

[0 −1

L11

C11

RC1

]×[

iL1vo

]+

[1L10

].n.(φ.vSC + VSCφ), (13)

Energies 2022, 15, 338 7 of 19

Finally, the Laplace transformation can be used as an output function of the control(control-to-output), and the input voltage can be obtained:

vo(s) =n× (φ× vSC + VSCφ)

s2L1C1 + s L1R + 1

=n.(φ× vSC + VSCφ)

( sω0

)2 + sQω0

+ 1. (14)

Thus, based on the control-to-output transfer function, a controller must be selected inorder to provide in the output a DC signal plus an AC 50 Hz signal. Therefore, a bandwidthof at least 500 Hz is needed for the SM in order to be considered as an ideal transfer functionby a high-level controller, in this case the MMC main controller. A voltage mode controllerwas selected due to its simplicity, but a current mode controller can be utilized as well. Toincrease the bandwidth of the DC/DC converter a type-III controller was used with thefollowing transfer function:

GC(s) = K(sT + 1)

sT× (sα/ωc + 1)

sαωc

+ 1× 1

sωLPF

+ 1, (15)

The type-III controller consists of a PI controller, defined by K and T, a lead-lagcontroller, defined by α and ωc, and a low pass filter with ωLPF as the cut-off frequency.Therefore, the closed loop system to control the output voltage, according to Figure 3b, is:

GCl(s) =vo

ˆvre f(s) =

GC(s) voφ(s)

1 + GC(s) voφ(s)∼=

1

1 + sQω f

+ s2

ω f2

(16)

In order to obtain that transfer function, the controller must have ωc = ω0.(1.1),ωLPF = π fs and α = 2.1 to have almost 50 of phase margin at around 10 kHz and K = 1.5and T = 0.0005. This way, the MMC main controller will consider the SM with a simpletransfer function and the control dynamics will not be coupled. Figure 5 shows the SMBode plot with the described type-III controller and the MMC using a simple PI controllerwhich is sufficient for a 50 Hz or 60 Hz sinusoidal output.


𝑣 (𝑠) = 𝑛 × 𝜙 × 𝑣 + 𝑉 𝜙𝑠 𝐿 𝐶 + 𝑠 𝐿𝑅 + 1 = 𝑛. 𝜙 × 𝑣 + 𝑉 𝜙𝑠𝜔 + 𝑠𝑄𝜔 + 1 . (14)

Thus, based on the control-to-output transfer function, a controller must be selected in order to provide in the output a DC signal plus an AC 50 Hz signal. Therefore, a band-width of at least 500 Hz is needed for the SM in order to be considered as an ideal transfer function by a high-level controller, in this case the MMC main controller. A voltage mode controller was selected due to its simplicity, but a current mode controller can be utilized as well. To increase the bandwidth of the DC/DC converter a type-III controller was used with the following transfer function: 𝐺 (𝑠) = 𝐾 (𝑠𝑇 + 1)𝑠𝑇 × (𝑠𝛼/𝜔 + 1)𝑠𝛼𝜔 + 1 × 1𝑠𝜔 + 1, (15)

The type-III controller consists of a PI controller, defined by K and T, a lead-lag con-troller, defined by 𝛼 and 𝜔 , and a low pass filter with 𝜔 as the cut-off frequency. Therefore, the closed loop system to control the output voltage, according to Figure 3b, is:

𝐺 (𝑠) = 𝑣𝑣 (𝑠) = 𝐺 (𝑠) 𝑣𝜙 (𝑠)1 + 𝐺 (𝑠) 𝑣𝜙 (𝑠) ≅ 11 + 𝑠𝑄𝜔 + 𝑠𝜔 (16)

In order to obtain that transfer function, the controller must have 𝜔 = 𝜔 . (1.1), 𝜔 = 𝜋𝑓 and 𝛼 = 2.1 to have almost 50° of phase margin at around 10 kHz and K = 1.5 and T = 0.0005. This way, the MMC main controller will consider the SM with a simple transfer function and the control dynamics will not be coupled. Figure 5 shows the SM Bode plot with the described type-III controller and the MMC using a simple PI controller which is sufficient for a 50 Hz or 60 Hz sinusoidal output.

(a) (b)

Figure 5. Closed loop transfer function for: (a) SM using a type-III controller and (b) MMC using a PI controller.

2.2. Boost-Mode (Vo → 𝑉 ) In this mode, energy is extracted from the grid and charges the SC. By controlling the

boost voltage, it is possible to extract power from very low input voltage levels, such as those found in a sinusoidal wave close to the zero crossing. In this case, the active bridge is Q5-Q8 and the synchronous rectifier bridge is Q1-Q4. A complete analysis can be done using the same procedure as in the buck mode, here a simple analysis is presented only in order to obtain the voltage conversion ratio, based on the simulated waveforms of Fig-ure 6. As in the buck mode, iL1 is triangular, it is charged when 𝑣′ = 0 and discharged when 𝑣′ ≈ 𝑛 · 𝑉 . Thus, as L1 in this direction is in the “input” side (Vo) and 𝑣′ reflects

Figure 5. Closed loop transfer function for: (a) SM using a type-III controller and (b) MMC using a PIcontroller.

2.2. Boost-Mode (Vo → VSC)

In this mode, energy is extracted from the grid and charges the SC. By controlling theboost voltage, it is possible to extract power from very low input voltage levels, such asthose found in a sinusoidal wave close to the zero crossing. In this case, the active bridgeis Q5–Q8 and the synchronous rectifier bridge is Q1–Q4. A complete analysis can be doneusing the same procedure as in the buck mode, here a simple analysis is presented only inorder to obtain the voltage conversion ratio, based on the simulated waveforms of Figure 6.

Energies 2022, 15, 338 8 of 19

As in the buck mode, iL1 is triangular, it is charged when v′c = 0 and discharged when v′c ≈n ·VSC. Thus, as L1 in this direction is in the “input” side (Vo) and v′c reflects the “output”side (VSC), this behavior matches a boost converter with a voltage conversion ratio of:

M =VSCVo

=TS/2

(t3 − t1).n≈

TS2

(1− D)TS × n=

0.5(1− D)× n

, (17)

where the time interval for transfer the energy to the “output” corresponds to the off-timeof the boost converter, which is approximately t3–t1, and the total time is TS/2 (converter’senergy transfer period is half of the sampling period). Finally, from Figure 6, t3–t1 =(1− D)TS/2. A more detailed analysis can be found in [28].


the “output” side (𝑉 ), this behavior matches a boost converter with a voltage conversion ratio of:

𝑀 = 𝑉𝑉 = 𝑇 /2(𝑡 − 𝑡 ). 𝑛 ≈ 𝑇2(1 − 𝐷)𝑇 × 𝑛 = 0.5(1 − 𝐷) × 𝑛, (17)

where the time interval for transfer the energy to the “output” corresponds to the off-time of the boost converter, which is approximately t3-t1, and the total time is 𝑇 /2 (converter’s energy transfer period is half of the sampling period). Finally, from Figure 6, t3-t1 = (1 − 𝐷)𝑇 /2. A more detailed analysis can be found in [28].

Figure 6. Boost-mode waveforms.

3. Modular Multilevel ESS In the present work, only a single-phase converter is considered, but this can be ex-

tended to a three-phase system by repeating the structure. The proposed modular multi-level ESS is composed of SMs in series, which work as voltage sources, each of them in-cluding the DC/DC converter from Section 2 and an energy storage device (SC). This al-lows the discharge current to be perfectly controlled; this way, the SCs can be balanced using the same DC/DC converter. This section aims to show all of the functions of each submodule inside the MMC.

3.1. Energy Storage Device The submodule includes the energy storage itself, so it is capable of delivering and

absorbing energy using the SC. In this proposal, the energy storage device is a SC, but it can be replaced by a battery in EV applications or islanded microgrids with a high number of renewable sources.

3.2. DC/DC Conversion with Galvanic Isolation The submodule includes an isolated DC/DC converter with a variable output voltage

range. The converter’s output can fluctuate from values that are close to zero to positive values; in the present application, it goes from 1 V to 20 V (at VSC = 2.7 V). The module provides an AC output signal with a DC offset. Then, combining half of the SMs in one direction and the other half in the opposite direction, as shown in Figure 2b, the DC offset is cancelled, and a pure AC signal is obtained.

Figure 6. Boost-mode waveforms.

3. Modular Multilevel ESS

In the present work, only a single-phase converter is considered, but this can beextended to a three-phase system by repeating the structure. The proposed modularmultilevel ESS is composed of SMs in series, which work as voltage sources, each of themincluding the DC/DC converter from Section 2 and an energy storage device (SC). Thisallows the discharge current to be perfectly controlled; this way, the SCs can be balancedusing the same DC/DC converter. This section aims to show all of the functions of eachsubmodule inside the MMC.

3.1. Energy Storage Device

The submodule includes the energy storage itself, so it is capable of delivering andabsorbing energy using the SC. In this proposal, the energy storage device is a SC, but itcan be replaced by a battery in EV applications or islanded microgrids with a high numberof renewable sources.

3.2. DC/DC Conversion with Galvanic Isolation

The submodule includes an isolated DC/DC converter with a variable output voltagerange. The converter’s output can fluctuate from values that are close to zero to positivevalues; in the present application, it goes from 1 V to 20 V (at VSC = 2.7 V). The moduleprovides an AC output signal with a DC offset. Then, combining half of the SMs in onedirection and the other half in the opposite direction, as shown in Figure 2b, the DC offsetis cancelled, and a pure AC signal is obtained.

Energies 2022, 15, 338 9 of 19

From the point of view of control, the MMC includes two control levels with twocontrollers: one controller inside each SM, which follows a voltage reference in the dischargedirection (buck-mode) and a current reference in the charge direction (boost-mode), andone master controller, which measures the MMC’s output signals and controls the energytransfer to the grid or load. In addition, the SM controller performs the balancing of theSCs (detailed in Section 3.3) and establishes the protection limits.

In the discharge direction, see Figure 7, the SM measures the output voltage, the SCvoltage, and current, and it controls the output voltage. The control loop is based on atype-III controller, which was designed in Section 2.


From the point of view of control, the MMC includes two control levels with two controllers: one controller inside each SM, which follows a voltage reference in the dis-charge direction (buck-mode) and a current reference in the charge direction (boost-mode), and one master controller, which measures the MMC’s output signals and controls the energy transfer to the grid or load. In addition, the SM controller performs the balanc-ing of the SCs (detailed in Section 3.3) and establishes the protection limits.

In the discharge direction, see Figure 7, the SM measures the output voltage, the SC voltage, and current, and it controls the output voltage. The control loop is based on a type-III controller, which was designed in Section 2.

In the charge direction, see Figure 8, the DC/DC controls the SC current and keeps the SC voltage within the limits. The type-III controller is limited when the voltage of the SC is approaching its maximum. The comparator creates the PWM signals and the 𝑇 /2 delay, and the NOR gate creates the switching pulses.

Figure 7. Buck-mode Controller.

Figure 8. Boost-mode controller.

3.3. Balancing Method In order to simplify the control of the whole MMC and to add minimal circuitry to

sense and control the SMs, the balancing of the SCs is conducted locally in each SM instead of giving this task to the master controller. Therefore, many SMs can be connected in series without increasing complexity in the control algorithm, as self-balancing is achieved at the SM level.

At hardware level (see Section 5), each SM is composed of a Microcontroller Unit (MCU) and all of the components that are required for operation. By taking advantages of this MCU, an integrated control can be implemented in such a way that the output power can be slightly adjusted for each SM in order to increase or decrease it. Thus, The SCs can be balanced without recirculating energy from one another. This is the main benefit of the proposed balancing control since any other active balancing system relies on the need to transfer the exceeding energy to another SC, and if the system is simple, then this energy might not be directly injected to the lowest voltage SC cell [4].

SCs are balanced when working in the buck-mode. Each SM measures its own SC voltage (𝑉 ) and two adjacent SC voltages (𝑉 and 𝑉 ), as shown in Figure 9. Thus, the DC/DC converter controller checks whether the SC is over or under the average voltage of this local measurement.

An error signal is defined as: 𝜀 = 3 × 𝑉𝑉 + 𝑉 + 𝑉 − 1, (18)


In the charge direction, see Figure 8, the DC/DC controls the SC current and keeps theSC voltage within the limits. The type-III controller is limited when the voltage of the SC isapproaching its maximum. The comparator creates the PWM signals and the TS/2 delay,and the NOR gate creates the switching pulses.


From the point of view of control, the MMC includes two control levels with two controllers: one controller inside each SM, which follows a voltage reference in the dis-charge direction (buck-mode) and a current reference in the charge direction (boost-mode), and one master controller, which measures the MMC’s output signals and controls the energy transfer to the grid or load. In addition, the SM controller performs the balanc-ing of the SCs (detailed in Section 3.3) and establishes the protection limits.

In the discharge direction, see Figure 7, the SM measures the output voltage, the SC voltage, and current, and it controls the output voltage. The control loop is based on a type-III controller, which was designed in Section 2.

In the charge direction, see Figure 8, the DC/DC controls the SC current and keeps the SC voltage within the limits. The type-III controller is limited when the voltage of the SC is approaching its maximum. The comparator creates the PWM signals and the 𝑇 /2 delay, and the NOR gate creates the switching pulses.



3.3. Balancing Method In order to simplify the control of the whole MMC and to add minimal circuitry to

sense and control the SMs, the balancing of the SCs is conducted locally in each SM instead of giving this task to the master controller. Therefore, many SMs can be connected in series without increasing complexity in the control algorithm, as self-balancing is achieved at the SM level.

At hardware level (see Section 5), each SM is composed of a Microcontroller Unit (MCU) and all of the components that are required for operation. By taking advantages of this MCU, an integrated control can be implemented in such a way that the output power can be slightly adjusted for each SM in order to increase or decrease it. Thus, The SCs can be balanced without recirculating energy from one another. This is the main benefit of the proposed balancing control since any other active balancing system relies on the need to transfer the exceeding energy to another SC, and if the system is simple, then this energy might not be directly injected to the lowest voltage SC cell [4].

SCs are balanced when working in the buck-mode. Each SM measures its own SC voltage (𝑉 ) and two adjacent SC voltages (𝑉 and 𝑉 ), as shown in Figure 9. Thus, the DC/DC converter controller checks whether the SC is over or under the average voltage of this local measurement.

An error signal is defined as: 𝜀 = 3 × 𝑉𝑉 + 𝑉 + 𝑉 − 1, (18)


3.3. Balancing Method

In order to simplify the control of the whole MMC and to add minimal circuitry tosense and control the SMs, the balancing of the SCs is conducted locally in each SM insteadof giving this task to the master controller. Therefore, many SMs can be connected in serieswithout increasing complexity in the control algorithm, as self-balancing is achieved at theSM level.

At hardware level (see Section 5), each SM is composed of a Microcontroller Unit(MCU) and all of the components that are required for operation. By taking advantages ofthis MCU, an integrated control can be implemented in such a way that the output powercan be slightly adjusted for each SM in order to increase or decrease it. Thus, The SCs canbe balanced without recirculating energy from one another. This is the main benefit of theproposed balancing control since any other active balancing system relies on the need totransfer the exceeding energy to another SC, and if the system is simple, then this energymight not be directly injected to the lowest voltage SC cell [4].

SCs are balanced when working in the buck-mode. Each SM measures its own SCvoltage (VSCn) and two adjacent SC voltages (VSCn−1 and VSCn+1), as shown in Figure 9.Thus, the DC/DC converter controller checks whether the SC is over or under the averagevoltage of this local measurement.

Energies 2022, 15, 338 10 of 19


Finally, the reference for the output voltage of the n-th SM is: 𝑉 = 𝑉 + 𝑉 𝐾𝜀∆ , (19)

where K is the proportional gain to limit ∆𝑣𝑛 to around 10% of the reference value 𝑉 . This means that ∆𝑣𝑛 can be slightly higher or lower than zero, and it is then added to 𝑉 , generating an individual 𝑉 = 𝑉 + ∆𝑣𝑛 for the n-th SM. As each SM control-ler is based on an MCU, these calculations are included in the SMs, as illustrated in Figure 9. In the boost-mode, the same method can be used if ∆𝑖𝑛 is added to 𝐼 .

Figure 9. Balancing control integrated in each SM to achieve self-balancing.

3.4. DC/AC Conversion Figure 2b shows two branches of SMs, the top and the bottom. The top branch deliv-

ers the positive half sinewave, and the bottom branch delivers the negative half sinewave. The master controller needs to sense the output voltage and current of the MMC (vMMC and iMMC) to properly command the whole array of SMs by sending only two variables to each SM: the operation mode (buck or boost-mode) and 𝑉 (for buck-mode) or 𝐼 (for boost-mode). These signals are sent to every SM in the corresponding active branch.

The master controller combines two 180° sinusoidal signals to achieve the DC/AC conversion. Figure 10 shows the controller details. In the proposed approach, the dq-frame method was used. The phase-locked loop (PLL) block obtains the grid angle and frequency [29] in order to extract the DC component to a low pass filter using a cut-off frequency of 5 Hz. The dq block includes the low pass filter, the DC signal, and the or-thogonal signals, so its outputs are the dq signals and the DC component: dq0 signals.

Figure 9. Balancing control integrated in each SM to achieve self-balancing.

An error signal is defined as:

ε =3×VSCn

VSCn+1 + VSCn + VSCn−1− 1, (18)

Finally, the reference for the output voltage of the n-th SM is:

VREFn = VREF + VREFKε︸︷︷︸∆vn

, (19)

where K is the proportional gain to limit ∆vn to around 10% of the reference value VREF.This means that ∆vn can be slightly higher or lower than zero, and it is then added to VREF,generating an individual VREFn = VREF + ∆vn for the n-th SM. As each SM controller isbased on an MCU, these calculations are included in the SMs, as illustrated in Figure 9. Inthe boost-mode, the same method can be used if ∆in is added to IREF.

3.4. DC/AC Conversion

Figure 2b shows two branches of SMs, the top and the bottom. The top branch deliversthe positive half sinewave, and the bottom branch delivers the negative half sinewave.The master controller needs to sense the output voltage and current of the MMC (vMMCand iMMC) to properly command the whole array of SMs by sending only two variables toeach SM: the operation mode (buck or boost-mode) and VREF (for buck-mode) or IREF (forboost-mode). These signals are sent to every SM in the corresponding active branch.

The master controller combines two 180 sinusoidal signals to achieve the DC/ACconversion. Figure 10 shows the controller details. In the proposed approach, the dq-frame method was used. The phase-locked loop (PLL) block obtains the grid angle andfrequency [29] in order to extract the DC component to a low pass filter using a cut-offfrequency of 5 Hz. The dq block includes the low pass filter, the DC signal, and theorthogonal signals, so its outputs are the dq signals and the DC component: dq0 signals.

The main controller shown in Figure 10a consists of three PI controllers: two of themfor the dq components and one more to minimize the DC value and the cross id–iq couplingelements (see Figure 10b). The resultant signal is processed and is divided by the numberof SMs and is shifted by 180 to provide the signals to the lower half of the SMs. In order toclarify the control loop and to design the controller parameters, the d-axis control loop isshown Figure 10b. The PI values can be obtained by cancelling the rC–LC pole with the PIzero at −1/τ and by finally selecting K in order to provide stability and decent bandwidth.For this case, K/(rC·τ) = ω0/10 was selected, whereω0 was 2·π·10 kHz.

Energies 2022, 15, 338 11 of 19Energies 2022, 15, x FOR PEER REVIEW 11 of 20

(a)

(b)

Figure 10. MMC controller (a) general scheme, (b) detail of d-component loop.

The main controller shown in Figure 10a consists of three PI controllers: two of them for the dq components and one more to minimize the DC value and the cross id-iq coupling elements (see Figure10b). The resultant signal is processed and is divided by the number of SMs and is shifted by 180° to provide the signals to the lower half of the SMs. In order to clarify the control loop and to design the controller parameters, the d-axis control loop is shown Figure 10b. The PI values can be obtained by cancelling the rC-LC pole with the PI zero at −1/τ and by finally selecting K in order to provide stability and decent band-width. For this case, K/(rC·τ) = 𝜔 /10 was selected, where ω0 was 2·π·10 kHz.

3.5. Grid Connection with Bidirectional Power Flow As the converter can work in buck or boost-mode, Figure 11 shows a flow diagram

that explains how the mode selector works. To absorb power, the DC/DC converter in each SM can operate in boost or buck-mode. In boost-mode, an IREF signal is used to control the amount of power that is absorbed from the grid. It is preferable for only active power to be absorbed when working in the boost-mode, mainly because the losses can be higher when reactive power is being absorbed.

The mode selector retrieves the SC voltage from any SM (since all of them should be balanced automatically) and checks whether the voltage is lower than a predefined value (1.5 V in this case). If so, the boost-mode is activated to absorb active power from the grid and to recharge the SCs. This voltage level was selected to charge the SCs when they are close to their lowest limit and when they can no longer deliver energy in the buck-mode. After charging the SCs and once they reach a valid working level (2.25 V), the master controller selects the buck-mode. The buck-mode works in a voltage-controlled scheme, where the controller supervises vMMC and iMMC (Figures 7 and 10) and where each SM can deliver or absorb active or reactive power by controlling id or iq.

Since the proposed ESS is based on a series chain of DC/DC converters, it can also be used in DC microgrids, and as mentioned before, if batteries are the primary energy stor-age device, then a different control strategy can be used [30,31]. The present work is

Figure 10. MMC controller (a) general scheme, (b) detail of d-component loop.

3.5. Grid Connection with Bidirectional Power Flow

As the converter can work in buck or boost-mode, Figure 11 shows a flow diagramthat explains how the mode selector works. To absorb power, the DC/DC converter in eachSM can operate in boost or buck-mode. In boost-mode, an IREF signal is used to control theamount of power that is absorbed from the grid. It is preferable for only active power to beabsorbed when working in the boost-mode, mainly because the losses can be higher whenreactive power is being absorbed.


limited to demonstrating the capabilities of the proposed ESS, and more advanced control techniques should be addressed in future work.

Figure 11. Mode selector diagram.

4. Simulation Results The ESS design was validated using a PSIM simulator. Four simulations were per-

formed for a total of 62 SMs (31 SMs for each branch, top and bottom) to obtain an output voltage of 220VAC at 50 Hz. Table 1 shows the components for each SM and the coupling inductor (LC). To reduce the simulation time, a SC with a capacitance value of 10F was used if not specified in the figure.

The first simulation was performed to validate the DC/DC converter that was deliv-ering a DC signal. The waveforms in Figure 4 correspond to a simulation of the converter with 𝑉 = 5 V in the buck-mode, which was used during converter analysis.

The second simulation consisted of a discharge process with a forced unbalanced condition in the SC voltages to verify the self-balancing algorithm that was working in the buck-mode. To that end, the capacitance and the initial voltage values of the SCs were set to be slightly different. The converter was commanded to deliver 10.2 kW to a resistive–inductive load (4.9 Ω-7 mH). The initial voltage difference between the ten plotted SC voltages (of the 62 SCs in the whole chain) was 200 mV. Figure 12 shows the voltage of these ten SCs, including the initial voltage and capacitance. Notice that around 0.3 s after the discharging process started, the voltage difference between the maximum and mini-mum values was reduced to 10mV, which is small enough to consider the SCs to be bal-anced. In the MMC, the upper half modules have a different voltage than the bottom half modules, as the zoom in Figure 12 shows. This is because the energy is transferred from the upper half modules during the positive half cycle and from the bottom half modules during the negative half cycle. Thus, the upper and the bottom half modules are balanced (voltage difference less than 10 mV) at different voltages, but both groups are close, around 20 mV for the 10F case.

Although the SCs were initially unbalanced, vMMC stayed stable for the whole time that the algorithm presented in Section 3.3 was balancing the SCs. This test also validates AC operation using the MMC configuration and the wide input operating voltage range of each SM, from 2.7 V to 1.0 V, where vMMC is slightly reduced when the SC voltage is lower than 1.5 V.

The third simulation consisted of connecting the MMC to the grid to validate the operations of the four quadrants involved in the buck-mode. Figure 13 demonstrates the capabilities of the MMC under different MMC voltage angles and amplitudes. In the sim-ulations, the angles and amplitudes were controlled by IREF_dq. Thus, different power trans-fers could be obtained. This simulation was created using the controller proposed in

Figure 11. Mode selector diagram.

The mode selector retrieves the SC voltage from any SM (since all of them should bebalanced automatically) and checks whether the voltage is lower than a predefined value(1.5 V in this case). If so, the boost-mode is activated to absorb active power from the gridand to recharge the SCs. This voltage level was selected to charge the SCs when they are

Energies 2022, 15, 338 12 of 19

close to their lowest limit and when they can no longer deliver energy in the buck-mode.After charging the SCs and once they reach a valid working level (2.25 V), the mastercontroller selects the buck-mode. The buck-mode works in a voltage-controlled scheme,where the controller supervises vMMC and iMMC (Figures 7 and 10) and where each SM candeliver or absorb active or reactive power by controlling id or iq.

Since the proposed ESS is based on a series chain of DC/DC converters, it can alsobe used in DC microgrids, and as mentioned before, if batteries are the primary energystorage device, then a different control strategy can be used [30,31]. The present work islimited to demonstrating the capabilities of the proposed ESS, and more advanced controltechniques should be addressed in future work.

4. Simulation Results

The ESS design was validated using a PSIM simulator. Four simulations were per-formed for a total of 62 SMs (31 SMs for each branch, top and bottom) to obtain an outputvoltage of 220VAC at 50 Hz. Table 1 shows the components for each SM and the couplinginductor (LC). To reduce the simulation time, a SC with a capacitance value of 10F wasused if not specified in the figure.

Table 1. Components used for simulation and prototype tests.

Component Value Details

SC 10F PSIM and 3000F prototype ESR = 0.4 mΩQ1 to Q4 3 × BSC009NE2LS5 rDS(on) = 0.9 mΩ

Q5 to Q8 and Qc 2 × BSC022N04LS6 rDS(on) = 2.2 mΩT1 core and LMAG 5.7 µH ELP32, N87 material

Turns ratio 1:8 -CC 6 × 0.068 µF in parallel 0805 X7RL1 10 µH EPCOS B82559C1 2 × 100 µF in parallel Solid tantalumTS 10 µS 1/TS = Fsw = 100 kHzLC 1 mH Coupling inductor

The first simulation was performed to validate the DC/DC converter that was deliver-ing a DC signal. The waveforms in Figure 4 correspond to a simulation of the converterwith VREF = 5 V in the buck-mode, which was used during converter analysis.

The second simulation consisted of a discharge process with a forced unbalancedcondition in the SC voltages to verify the self-balancing algorithm that was working inthe buck-mode. To that end, the capacitance and the initial voltage values of the SCswere set to be slightly different. The converter was commanded to deliver 10.2 kW to aresistive–inductive load (4.9 Ω-7 mH). The initial voltage difference between the ten plottedSC voltages (of the 62 SCs in the whole chain) was 200 mV. Figure 12 shows the voltageof these ten SCs, including the initial voltage and capacitance. Notice that around 0.3 safter the discharging process started, the voltage difference between the maximum andminimum values was reduced to 10mV, which is small enough to consider the SCs to bebalanced. In the MMC, the upper half modules have a different voltage than the bottomhalf modules, as the zoom in Figure 12 shows. This is because the energy is transferred fromthe upper half modules during the positive half cycle and from the bottom half modulesduring the negative half cycle. Thus, the upper and the bottom half modules are balanced(voltage difference less than 10 mV) at different voltages, but both groups are close, around20 mV for the 10F case.

Although the SCs were initially unbalanced, vMMC stayed stable for the whole timethat the algorithm presented in Section 3.3 was balancing the SCs. This test also validatesAC operation using the MMC configuration and the wide input operating voltage range ofeach SM, from 2.7 V to 1.0 V, where vMMC is slightly reduced when the SC voltage is lowerthan 1.5 V.

Energies 2022, 15, 338 13 of 19

The third simulation consisted of connecting the MMC to the grid to validate theoperations of the four quadrants involved in the buck-mode. Figure 13 demonstratesthe capabilities of the MMC under different MMC voltage angles and amplitudes. Inthe simulations, the angles and amplitudes were controlled by IREF_dq. Thus, differentpower transfers could be obtained. This simulation was created using the controllerproposed in Figure 10. Figure 13 shows the voltage in two SMs from different half branches(top and bottom), iMMC and vMMC. In the first interval, the MMC delivers 4 kVAr ofreactive power with IREF_dq = (IREF_d, IREF_q) = (0, 25 A). Then, the MMC absorbs 4 kVAr,so IREF_dq = (0, −25 A). Then, at t=1s, active power is delivered, so for 0.2 s, the systemdelivers 4kW-3.2kVAr, IREF_dq = (25 A, −20 A). After that, the reactive current is set to zero,and only active power is delivered. Finally, 4 kW of active power is absorbed. This testshows the MMC is capable of absorbing and delivering active and reactive power. Noticethe balancing process in the SC voltages and the increase and decrease in the SC voltageswhen they are absorbing and delivering power, respectively.


Figure 10. Figure 13 shows the voltage in two SMs from different half branches (top and bottom), iMMC and vMMC. In the first interval, the MMC delivers 4 kVAr of reactive power with IREF_dq = (IREF_d, IREF_q) = (0, 25 A). Then, the MMC absorbs 4 kVAr, so IREF_dq = (0, −25 A). Then, at t=1s, active power is delivered, so for 0.2 s, the system delivers 4kW-3.2kVAr, IREF_dq = (25 A, −20 A). After that, the reactive current is set to zero, and only active power is delivered. Finally, 4 kW of active power is absorbed. This test shows the MMC is capable of absorbing and delivering active and reactive power. Notice the balancing process in the SC voltages and the increase and decrease in the SC voltages when they are absorbing and delivering power, respectively.

The fourth simulation validated the boost-mode (or absorbing mode), as shown In Figure 14, where the SC in each SM recharges from 1.4 V to 2.25 V and where the SCs are balanced at the same time.

Table 1. Components used for simulation and prototype tests.

Component Value Details SC 10F PSIM and 3000F prototype ESR = 0.4 mΩ

Q1 to Q4 3 × BSC009NE2LS5 rDS(on) = 0.9 mΩ Q5 to Q8 and Qc 2 × BSC022N04LS6 rDS(on) = 2.2 mΩ

T1 core and LMAG 5.7 µH ELP32, N87 material Turns ratio 1:8 -

CC 6 × 0.068 µF in parallel 0805 X7R L1 10 µH EPCOS B82559 C1 2 × 100 µF in parallel Solid tantalum TS 10 µS 1/TS = Fsw = 100 kHz LC 1 mH Coupling inductor

Figure 12. Balancing process (10 kW, discharge mode) in the whole voltage range. Figure 12. Balancing process (10 kW, discharge mode) in the whole voltage range.


Figure 13. Delivering or absorbing active or reactive power in buck-mode with zoomed sections.

Figure 14. Boost-mode recharging the SCs.

5. Experimental Results A down-scaled prototype for two SMs from each half branch was constructed, with

a maximum power transfer of 175W per SM. Figure 15 shows the complete MMC, which is composed of the top branch, the bottom branch, a vMMC and iMMC sensor board, and a microcontroller unit (MCU), which acts as the master controller. Each SM integrates all of the components that are listed in Table 1; the power switches are at the bottom and are attached to a heatsink. In addition, the TI TMS320F28027 DSP was used as the SM control-ler, which includes the proportional controller for balancing the SCs and the PWM gener-ator. The SM planar transformer was designed and developed specifically for the proto-type. The master controller was implemented in a TI TMS320F28379D MCU, which gives the references to the SMs.


Energies 2022, 15, 338 14 of 19

The fourth simulation validated the boost-mode (or absorbing mode), as shown InFigure 14, where the SC in each SM recharges from 1.4 V to 2.25 V and where the SCs arebalanced at the same time.




5. Experimental Results A down-scaled prototype for two SMs from each half branch was constructed, with

a maximum power transfer of 175W per SM. Figure 15 shows the complete MMC, which is composed of the top branch, the bottom branch, a vMMC and iMMC sensor board, and a microcontroller unit (MCU), which acts as the master controller. Each SM integrates all of the components that are listed in Table 1; the power switches are at the bottom and are attached to a heatsink. In addition, the TI TMS320F28027 DSP was used as the SM control-ler, which includes the proportional controller for balancing the SCs and the PWM gener-ator. The SM planar transformer was designed and developed specifically for the proto-type. The master controller was implemented in a TI TMS320F28379D MCU, which gives the references to the SMs.


5. Experimental Results

A down-scaled prototype for two SMs from each half branch was constructed, witha maximum power transfer of 175W per SM. Figure 15 shows the complete MMC, whichis composed of the top branch, the bottom branch, a vMMC and iMMC sensor board, and amicrocontroller unit (MCU), which acts as the master controller. Each SM integrates allof the components that are listed in Table 1; the power switches are at the bottom andare attached to a heatsink. In addition, the TI TMS320F28027 DSP was used as the SMcontroller, which includes the proportional controller for balancing the SCs and the PWMgenerator. The SM planar transformer was designed and developed specifically for theprototype. The master controller was implemented in a TI TMS320F28379D MCU, whichgives the references to the SMs.


Figure 15. Complete MMC prototype.

Three experimental tests were performed. The first test was the validation of the SM waveforms in buck-mode and boost-mode, as shown in Figure 16. These waveforms are consistent with the theoretical and simulated ones (Figures 4 and 5).

The second test shows the operation of the MMC. Figure 17 shows the discharge mode (buck-mode) with a resistive load; the test depicts vMMC and iMMC. It shows that the voltage stayed stable during a step change in the load.

The third test shows the operation of the MMC when the load changes from R to RL and from R to RC, as shown in Figure 18, which validates the operation with reactive current flow. As the grid connection was validated in the simulation section, only the MMC was tested with different experimental loads to generate the experimental results, and thus the MMC was the only AC grid generator.

Finally, the fourth test demonstrated the efficiency of the whole MMC in both oper-ation modes, as shown in Figure 19. The efficiency at high power is not as good as it is in a high-voltage DC/DC converter because of the large currents and low input voltages; however, it can be improved by paralleling the DC/DC converters in each submodule and by using wide band semiconductors, such as GaN or SiC. The prototype shows how the circuit works; however, the efficiency is not optimized and can be improved further.

(a) (b)

Figure 16. Experimental waveforms for each SM in (a) buck and (b) boost-mode.


Three experimental tests were performed. The first test was the validation of the SMwaveforms in buck-mode and boost-mode, as shown in Figure 16. These waveforms areconsistent with the theoretical and simulated ones (Figures 4 and 5).

Energies 2022, 15, 338 15 of 19



Three experimental tests were performed. The first test was the validation of the SM waveforms in buck-mode and boost-mode, as shown in Figure 16. These waveforms are consistent with the theoretical and simulated ones (Figures 4 and 5).

The second test shows the operation of the MMC. Figure 17 shows the discharge mode (buck-mode) with a resistive load; the test depicts vMMC and iMMC. It shows that the voltage stayed stable during a step change in the load.

The third test shows the operation of the MMC when the load changes from R to RL and from R to RC, as shown in Figure 18, which validates the operation with reactive current flow. As the grid connection was validated in the simulation section, only the MMC was tested with different experimental loads to generate the experimental results, and thus the MMC was the only AC grid generator.

Finally, the fourth test demonstrated the efficiency of the whole MMC in both oper-ation modes, as shown in Figure 19. The efficiency at high power is not as good as it is in a high-voltage DC/DC converter because of the large currents and low input voltages; however, it can be improved by paralleling the DC/DC converters in each submodule and by using wide band semiconductors, such as GaN or SiC. The prototype shows how the circuit works; however, the efficiency is not optimized and can be improved further.

(a) (b)

Figure 16. Experimental waveforms for each SM in (a) buck and (b) boost-mode. Figure 16. Experimental waveforms for each SM in (a) buck and (b) boost-mode.

The second test shows the operation of the MMC. Figure 17 shows the discharge mode(buck-mode) with a resistive load; the test depicts vMMC and iMMC. It shows that the voltagestayed stable during a step change in the load.


Figure 17. MMC output voltage and current for a step change in the load.

(a) (b)

Figure 18. Step response from (a) R to RL and (b) R to RC.

Figure 19. Efficiency of a single SM for the Buck-mode and Boost-mode.

Comparsion with Other ESSs In order to summarize the advantages and disadvantages of the proposed converter,

Table 2 is presented. To make a fair comparison between the proposed ESS, only systems that require one additional stage to operate in the same way as the one proposed here are analysed.

The converter that is proposed in [17] requires an additional balancing system for the SC cells but provides isolation and the DC/DC and DC/AC conversions in a single cell. The main drawback is that the efficiency is not as high as the proposed converter.

A highly efficient multi-cell converter is presented in [18]; however, a balancing sys-tem is required in order to accommodate the SC cells. However, the complexity of the converter’s transformer design and control operation can be the main drawbacks, and the high efficiency can be reduced with the incorporation of the balancing system.

A comparable ESS is presented in [25] since it is based on the traditional control scheme of MMC. A high THD is presented at the output, but because of this, the efficiency is high due the fact that less switching stress is presented. However, this ESS lacks isola-tion, and if required, a bulky transformer should be placed at the output and efficiency could be further reduced.

Since the proposed ESS can accomplish all of the required stages in a single SM and since the balancing control is embedded and is relatively simple to operate, the main con-cern relays in the efficiency of the system. For this reason, the only drawback would be


The third test shows the operation of the MMC when the load changes from R toRL and from R to RC, as shown in Figure 18, which validates the operation with reactivecurrent flow. As the grid connection was validated in the simulation section, only the MMCwas tested with different experimental loads to generate the experimental results, and thusthe MMC was the only AC grid generator.



(a) (b)










Finally, the fourth test demonstrated the efficiency of the whole MMC in both operationmodes, as shown in Figure 19. The efficiency at high power is not as good as it is in a high-voltage DC/DC converter because of the large currents and low input voltages; however, itcan be improved by paralleling the DC/DC converters in each submodule and by using

Energies 2022, 15, 338 16 of 19

wide band semiconductors, such as GaN or SiC. The prototype shows how the circuitworks; however, the efficiency is not optimized and can be improved further.



(a) (b)










Comparsion with Other ESSs

In order to summarize the advantages and disadvantages of the proposed converter,Table 2 is presented. To make a fair comparison between the proposed ESS, only systemsthat require one additional stage to operate in the same way as the one proposed here areanalysed.

The converter that is proposed in [17] requires an additional balancing system for theSC cells but provides isolation and the DC/DC and DC/AC conversions in a single cell.The main drawback is that the efficiency is not as high as the proposed converter.

A highly efficient multi-cell converter is presented in [18]; however, a balancingsystem is required in order to accommodate the SC cells. However, the complexity of theconverter’s transformer design and control operation can be the main drawbacks, and thehigh efficiency can be reduced with the incorporation of the balancing system.

A comparable ESS is presented in [25] since it is based on the traditional controlscheme of MMC. A high THD is presented at the output, but because of this, the efficiencyis high due the fact that less switching stress is presented. However, this ESS lacks isolation,and if required, a bulky transformer should be placed at the output and efficiency could befurther reduced.

Since the proposed ESS can accomplish all of the required stages in a single SM andsince the balancing control is embedded and is relatively simple to operate, the mainconcern relays in the efficiency of the system. For this reason, the only drawback would bethe cost if efficiency has to be increased, as GaN or SiC transistors should be integrated ineach SM.

Table 2. Components used for simulations and prototype’s tests.

ESS Efficiencyat 50%

AdditionalStages Drawbacks

[17] 84~86% Balancing system Medium THD[18] 95~97% Balancing system Complexity[25] 91~94% * Output transformer High THD

Proposed 85~88% None Cost* Obtained by numerical simulations.

6. Conclusions

In a traditional supercapacitor (SC)-based ESS, four stages are needed: energy storagedevices, the balancing system, and the DC/DC and DC/AC converters that connect thestorage devices to the grid. The SC-based ESS that is proposed in this article uses a modularmultilevel converter (MMC) that is able to reduce the number of stages by performingthe self-balancing process and the DC/DC and DC/AC conversions in a single stage.Each submodule (SM) of the MMC consists of a DC/DC converter and a single SC. TheDC/DC converter is a bidirectional full-bridge that has an active clamp and soft-switchingtechniques and works at 100 kHz and at low input voltages. In addition, the DC/DC

Energies 2022, 15, 338 17 of 19

converter includes a planar transformer, galvanic isolation is also achieved, and a bulky50 Hz transformer can be avoided.

The MMC that was proposed here can be implemented using a large number of SMsin series without increasing the complexity of the main controller. This is because thebalancing process is performed in each SM, and the main controller only governs the powerflow between the SCs and the grid. This makes the proposed MMC attractive for SC-basedESS designs.

The proposed design was validated in simulations and in a real prototype. Four-quadrant operation with low distortion was achieved. Although the efficiency was notgreater than those of the compared topologies, further work should overcome this limitationby using GaN or SiC transistors.

Author Contributions: Conceptualization, F.D.H. and F.M.I.; methodology, F.M.I.; software, F.D.H.and R.S.; validation, F.D.H., F.M.I. and F.M.; formal analysis, R.S.; investigation, F.D.H.; resources,F.M.I.; data curation, R.S.; writing—original draft preparation, F.D.H.; writing—review and editing,F.D.H., F.M.I. and F.M.; visualization, F.D.H.; supervision, F.M.I.; project administration, F.M.I.; fund-ing acquisition, F.M.I. All authors have read and agreed to the published version of the manuscript.

Funding: This work was carried out as a part of the AMPaC Megagrant project supported by TheMinistry of Education and Science of Russian Federation, Grant Agreement No 075-10-2021-067,Grant identification code 000000S707521QJX0002.

Institutional Review Board Statement: Not applicable.

Informed Consent Statement: Not applicable.

Data Availability Statement: Not applicable.

Acknowledgments: The authors would like to thank W. Baldwin for the great help.

Conflicts of Interest: The authors declare no conflict of interest.

Abbreviations

ESS Energy storage systemMMC Modular multilevel converterSM SubmoduleSC SupercapacitorTHD Total harmonic distortionMCU Microcontroller unit

Nomenclature

vMMC Output voltage port of the MMCLC Coupling inductorvgrid Grid voltageL1 Output inductor at SM levelC1 Output capacitor at SM levelVSC Supercapacitor voltage at SM levelVo Output voltage at SM levelCc Clamp capacitor at SM levelQc Clamp switch at SM levelQ1 to Q4 Full-bridge voltage-fed section switches at SM levelT1 High-frequency transformer at SM level.Q5 to Q8 Full-bridge current-fed section switches at SM level.t1 to t6 time intervals for the DC/DC converter operationTS Switching periodφ Phase-shift angle

Energies 2022, 15, 338 18 of 19

D Duty cycle at boost-modeLlk Leakage inductanceLmag Magnetizing inductancevtp Transformer’s primary voltagevts Transformer’s secondary voltagev′c Clamp voltage noden Transformer’s turn-ratioVCc Clamp capacitor’s voltageiLlk Leakage inductor’s currentiL1 Output inductor’s currentiCc Clamp capacitor’s currentvLlk Leakage inductor’s voltageω0 Resonant frequency between the capacitor’s clamp and the leakage inductanceIo Output current at SM levelM Voltage transfer function at SM levelfs Switching frequencyGC Type-III controller transfer function at SM levelα Lead-lag alfa parameter of the type-III controllerK Gain parameter of the type-III controllerT Time constant of the type-III controllerωc Lead-lag frequency parameter of the type-III controllerωLPF Low pass filter frequency of the type-III controllerε Error signal for the supercapacitor balancing embedded controller at each SMVREF Voltage reference for each SM at MMC leveliREF Current reference for each SM at MMC leveliMMC MMC current

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